JP2001196865A - Wireless communication apparatus and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress thermal runaway, to enhance the efficiency and to prevent the oscillation. SOLUTION: The wireless communication apparatus that has a high frequency power amplifier module incorporating a single stage amplifier employing a hetero-junction bipolar transistor(HBT) of a multi-finger structure or a multi- stage amplifier consisting of a plurality of HBTs in cascade connection at its sender side output stage and has an antenna connected to the high frequency power amplifier module, is provided with a 1st capacitor and a 1st resistor placed in series between an input terminal of the high frequency power amplifier module and each control finger of the HBT and with a 2nd resistor that is inserted between a control terminal of the high frequency power amplifier module and each control finger of the HBT and connected to a node between the 1st resistor and the 1st capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless communication device such as a portable telephone and a semiconductor device incorporated in the wireless communication device, and more particularly to a single-stage configuration using one high-power amplifier having a plurality of transistors connected in parallel. A radio communication device having a multi-stage high-frequency power amplification module in which a plurality of high-power amplifiers are sequentially connected in a dependent manner at a transmission-side output stage, and having an antenna connected to the high-frequency power amplification module. The present invention relates to an effective technique applied to an oscillation prevention technique.

[0002]

2. Description of the Related Art A high-frequency power amplifier module (high-frequency power amplifier circuit) is incorporated in an output stage of a mobile communication device (wireless communication device) such as a mobile phone or a mobile phone. The output (transmission power) of this high-frequency power amplification module is supplied to a bias control circuit (APC: Automati
c Automatically controlled by the Power Control circuit.

In general, a mobile phone performs a call by changing the output so as to be applied to the surrounding environment by a power level instruction signal transmitted from a base station in accordance with the usage environment, and causes interference with other mobile phones. A system has been built to prevent this. The mobile phone receives the power level instruction signal and outputs a predetermined signal (control signal) from the bias control circuit to the amplifier of the high-frequency power amplifier module, thereby adjusting the output of the wireless communication device.

The high-frequency power amplifier module has a single-stage configuration in which one semiconductor amplifying element (transistor) is used or a multi-stage configuration in which a plurality of transistors are sequentially connected in cascade. As transistors, bipolar transistors,
MOSFET (Metal Oxide Semiconductor Field-Effec
t-Transistor), GaAs-MES (Metal-Semiconducto)
r) FET, HEMT (High Electron Mobility Transis
tor), HBT (Heterojunction Bipolar transistor) and the like are used.

[0005] US Patent No. 5,629,648 discloses a heterojunction bipolar transistor high power amplifier circuit. According to this document, in a plurality of transistors connected in parallel, a resistor for supplying a DC bias and a capacitor for supplying an AC signal are provided for each transistor in each base, and thermal runaway is suppressed by a voltage drop of the resistor for supplying DC. A high-power bipolar transistor circuit is described.

On the other hand, Japanese Patent Application Laid-Open No. 7-7014 (US Pat.
No. 321,279) discloses a multi-finger Si having an emitter finger (emitter terminal), a base finger (base terminal), and a collector finger (collector terminal) in order to operate the device reliably.
In a bipolar transistor, a power HB for connecting a ballast impedance to a base finger to suppress thermal runaway (current hopping: hot spot)
T is disclosed. That is, by providing a ballast impedance (resistor) for each base finger, a hot spot caused by current concentration is suppressed.

In this document, a capacitor (bypass capacitor) is connected in parallel with the ballast impedance (resistor) in order to ensure the minimum gain loss of the transistor. It also states that the power HBT can be used as a high power amplifier and can be used for a cellular telephone.

On the other hand, JP-A-7-94975 discloses a MOS
High-frequency HIC module (high-frequency power amplifier module) with a three-stage configuration in which FETs are cascaded in the first, middle, and final stages
Is disclosed. This high frequency HIC module is
"The first bias circuit is configured to bias a gate of a predetermined MOSFET among a plurality of MOSFETs based on an output control voltage, and the predetermined MOSF
A second bias circuit for biasing the gates of the remaining MOSFETs other than the ET based on a fixed power supply, and switch means for switching a path between the fixed power supply and the second bias circuit in accordance with the output control voltage. Provided. " Thereby, the controllability of the output is improved and the efficiency is improved. Each bias circuit is composed of three resistors and one capacitor.

[0009]

Since the HBT has excellent characteristics such as high speed and low power consumption, it is being used as a semiconductor amplifying element of a high frequency power amplifying module incorporated in a wireless communication device such as a portable telephone. .

During the development of a power amplifier module (high-frequency power amplifier module) for a portable telephone using an HBT, the inventor studied means for improving efficiency while suppressing both thermal runaway and oscillation of the HBT element. It has been confirmed that the following problems occur in a wireless communication device employing a conventionally known circuit.

FIG. 18 is a schematic circuit diagram of a part of a wireless communication apparatus incorporating a single-stage amplifier (high-frequency power amplifier module) using one HBT having a multi-finger structure.
This circuit employs the circuit configuration of U.S. Pat. No. 5,629,648 (conventional example 1). Here, for the sake of convenience in the following description, a portion composed of one emitter terminal (emitter finger), a base terminal (base finger) and a collector terminal (collector finger) is called a transistor (unit cell). A transistor group in which the plurality of transistors are connected in parallel is referred to as a multi-finger transistor or a multi-finger transistor. Therefore, the HBT becomes one multi-finger transistor.

The high-frequency power amplification module 1 has, as external terminals, an input terminal (RFin), an output terminal (RFout),
A first voltage terminal (Vcc) also serving as a collector terminal, a second voltage terminal (ground: GND) also serving as an emitter terminal, and a bias terminal (control terminal: Vap) also serving as a base terminal
c) has. The antenna 2 is connected to the output terminal (RFout) via a filter or the like (not shown).

The HBT is a multi-finger transistor, and has a structure in which N transistors are connected in parallel. Each of the transistors Q1A to Q1N includes an emitter terminal 5, a base terminal 6, and a collector terminal 7.

This circuit has a structure in which an input terminal and a control terminal are separated, and each of the transistors Q1A to Q1N
Between the base terminal 6 and the input terminal of the capacitor C2A to C2N
And ballast resistors R2A to R2A are connected between the base terminal 6 and the control terminal of each transistor Q1A to Q1N.
2N is inserted and connected.

The first voltage terminal (Vcc) and each collector terminal 7 are connected to a single inductor Lc, and each emitter terminal 5 is connected to ground (GND). A matching circuit 9 is provided on the output side of the high-frequency power amplifier module 1 for impedance matching with the antenna 2.

In this wireless communication device, since the AC signal is supplied only through the capacity, the efficiency of the wireless communication device is about 60% (equivalent to about 70% in the efficiency of the high frequency power amplifier module). ), There is no loss in the signal path, so that the stability of the element is degraded, and the oscillation phenomenon is likely to occur, so that stable communication may not be performed. That is, the impedance that allows the external circuit to be seen at high frequencies is small, the stabilization coefficient K is extremely small, and the transistor becomes unstable.

FIG. 6 is a graph showing the correlation between the stabilization coefficient K and the collector current. In the same graph, Conventional Example 1 is a curve showing the stabilization coefficient value. The stabilization coefficient K is about 0.15 when the collector current is 0.01 A, and further increases as the collector current value increases. Becomes smaller.

FIG. 7 is a graph showing the relationship between input power (dBm) and power added efficiency (%). In this graph, Conventional Example 1 is a curve showing the additional efficiency, and the maximum value is a point where the input power is large, that is, the maximum value is 68.25 at about 25 dBm.
It reaches about 5%.

FIGS. 19 and 20 are schematic circuit diagrams of a part of a wireless communication apparatus incorporating a single-stage amplifier (high-frequency power amplifier module) using one HBT having a multi-finger structure. This is a circuit adopting the circuit configuration described in Japanese Patent No. 7014, respectively. In the circuit configuration of FIG. 19, the base terminals 6 of the transistors Q1A to Q1N are simply
And a control terminal (Vapc) between the ballast resistor R1
A to R1N is inserted, but if a value sufficient to prevent thermal runaway is used as a ballast resistor, high frequency signals will be attenuated,
Amplification characteristics may be significantly impaired.

The circuit of FIG. 20 includes bypass capacitors C1A to C1C in parallel with resistors R1A to R1N to prevent attenuation of a high-frequency signal.
Although this is a circuit in which 1N is inserted (conventional example 2), the value of the bypass capacitance needs to be increased (for example, about 50 pF) in order to reduce the performance degradation, and the area of the semiconductor chip in which the HBT is incorporated increases. I hate it,
Due to a decrease in the number of semiconductor chips obtained from one semiconductor substrate (wafer), the manufacturing cost of semiconductor chips (semiconductor elements, that is, semiconductor devices) increases. In addition, it has been found that the impedance for anticipating the external circuit at a high frequency is reduced, so that the stabilization coefficient K is reduced, and the circuit easily oscillates. As shown in the graph of FIG. 6, the stabilization coefficient K is better than that of the conventional example 1, but is far from the stabilization coefficient 1 at which oscillation hardly occurs, and is stabilized when the collector current is between 0.01 and 1 A. The coefficient K is about 0.5 to about 0.75.
Capacitors C1A to C1N connected in parallel with the resistors R1A to R1N
Is for increasing the high-frequency gain. However, if the capacitance value is increased for the purpose of increasing the gain, oscillation becomes easy. Conversely, when the capacitance value is reduced, the effect of the high-frequency gain is reduced, and it becomes difficult to optimize the design.

An object of the present invention is to provide a radio communication device in which an oscillation phenomenon hardly occurs even in a high efficiency region of the radio communication device, and a semiconductor device (semiconductor element) incorporated in the radio communication device.

Another object of the present invention is to provide a radio communication device which suppresses thermal runaway, has high efficiency and hardly causes an oscillation phenomenon, and a semiconductor device (semiconductor element) incorporated in the radio communication device.
Is to provide.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0024]

SUMMARY OF THE INVENTION A brief description of typical inventions disclosed in the present application is as follows.
It is as follows.

(1) A high-frequency power amplifier module including a single-stage amplifier using one hetero-junction bipolar transistor (HBT) having a multi-finger structure or a multi-stage amplifier in which a plurality of HBTs are sequentially connected in cascade, is provided on a transmission-side output stage; A wireless communication device having an antenna connected to the high-frequency power amplifier module, a first capacitor and a first resistor inserted in series between an input terminal of the high-frequency power amplifier module and each control terminal of the HBT; The high-frequency power amplification module has a second resistor inserted between a control terminal of the high-frequency power amplifier module and each control terminal of the HBT, and connected to a node between the first resistor and the first capacitor. A semiconductor device (semiconductor element) incorporated in a wireless communication device includes an input terminal, an output terminal, a bias terminal,
A high-output amplifier configured by connecting a plurality of transistors each including a first terminal and a second terminal and a control terminal for controlling a current flowing between the first terminal and the second terminal in parallel; First capacitors C2A to C2N connected to the input terminals and first resistors C2A to C2N connected in series to the first capacitors C2A to C2N and connected to the control terminals of the transistors; R1A ~
R1N, and the first resistors R1A to R1R are respectively disposed between the bias terminal and the control terminals of the transistors.
1N and second resistors R2A to R2N connected to nodes between the first capacitors C2A to C2N, and the output terminal is connected to each first terminal of the transistor.

(2) In the configuration of the means (1), a second capacitor is connected in parallel with the first resistor. The semiconductor device incorporated in such a wireless communication device has a configuration in the configuration of (1) above, including second capacitors C1A to C1N connected in parallel to the first resistors R1A to R1N.

(3) In the means (1) or (2), an inductor is inserted and connected to the base terminal and / or the emitter terminal.

(4) A high-frequency power amplifying module having a built-in single-stage amplifier using one hetero-junction bipolar transistor (HBT) having a multi-finger structure or a multi-stage amplifier in which a plurality of HBTs are sequentially connected in cascade, is provided on a transmission-side output stage; In a wireless communication apparatus having an antenna connected to the high-frequency power amplifier module, a difference in thermal resistance between a plurality of terminals (fingers) of an HBT constituting one stage of the amplifier is determined by an average thermal resistance of the fingers. A first resistor inserted in series between an input terminal of the high-frequency power amplifier module and each control terminal of the HBT; and a first resistor connected in series between the input terminal of the high-frequency power amplifier module and each control terminal of the HBT. A first capacitor connected between a terminal and a node to which the plurality of first resistors are connected; A second resistor and which are respectively connected to the first resistor and the Control terminal to a node between the first capacitor.

According to the means (1), (a) the second resistor causes a base voltage drop with an increase in the base current due to the temperature rise of the HBT chip. Therefore, the increase in the current of each transistor is suppressed and the thermal runaway occurs. Is suppressed. Therefore, the same effect is exerted also in a semiconductor device (semiconductor element).

(B) The first resistor stabilizes each transistor by preventing an excessive increase in gain due to high-frequency loss, thereby preventing oscillation. Therefore, the same effect is exerted also in the semiconductor device.

(C) By inserting and connecting the first resistor, the second resistor, and the first capacitor, a highly efficient wireless communication device can be provided. For example, in a high-frequency power amplifier module, if an HBT is used, the number of transistors is about 100, and the emitter size is about 2 μm × 20 μm, an output of about 4 W can be obtained. At this time, if the current gain is about 80, the first capacitance is about 0.15 pF,
The resistance is about 100 ohms, and the second resistance is about 1 kohm, and the efficiency can be about 70% (see FIGS. 7 and 8). During this high-efficiency operation, the DC current flowing through the first resistor is about 0.2 to 0.5 mA, and the voltage drop at the first resistor is sufficiently small, 20 to 50 mV, and the loss is small. According to FIG. 9, the value of the first resistor is 2.5 times, that is, 2 times.
The change in efficiency is small up to about 50Ω (2.5Ω when 100 pieces are paralleled), and the voltage drop at the first resistor at this time is sufficiently small, 50 to 25 mV. This means that the efficiency of the wireless communication device is about 60%, and a highly efficient wireless communication device can be achieved.

(D) Runaway and oscillation of the amplifier due to temperature fluctuations and power supply fluctuations are less likely to occur, and stable communication can be performed without interrupting transmission of radio signals.

(E) The high-frequency gain can be increased by connecting a capacitor to the first resistor in parallel, but oscillation occurs when the capacitance value is increased. According to the present invention, since the capacitor is not connected to the first resistor, oscillation of the base ballast resistor can be suppressed. Therefore, the same effect is exerted also in the semiconductor device.

According to the means (2), (a) the first resistor and the second resistor are connected in series, connected to the base terminal, and the second capacitor is connected in parallel to the first resistor. By doing so, the resistance value of the first resistor can be reduced. As a result, the bypass capacitance (second capacitance) connected in parallel with the first resistor can be reduced. Conventionally, for example, the capacitance was about 50 pF, but it can be reduced to about 1/10 of that, about 5 pF, and the chip area can be reduced by the capacitance. Therefore, cost reduction of the semiconductor amplifying element (semiconductor element: semiconductor chip) can be achieved.

(B) Since the circuit configuration is a combination of the first resistor, the second resistor, the first capacitor, and the second capacitor, the degree of freedom in circuit design in the semiconductor chip is increased. Meanwhile, the first
Since it is necessary to arrange a resistor, a second resistor, a first capacitor, and a second capacitor, the arrangement of elements on a chip is limited.

Further, the attenuation of the high-frequency signal by the first resistor is reduced by bypassing through the second capacitor, and the efficiency of the amplifier is increased. For example, in FIG. 7, the same efficiency as that of the first conventional example can be obtained.

Even in the case of the means (2), the condition that the gain of the amplifier is saturated, that is, the point where the input power is large as shown in FIG. And there is almost no difference in efficiency. This reduces the loss of the high frequency signal at the first resistor to the second
This is because an increase in gain caused by bypassing the capacitor and an increase in efficiency accompanying the increase are canceled out by the effect of gain saturation of the amplifier.

Therefore, in the case where the gain of the amplifier is saturated during use, taking into account the difficulty of chip design due to the complicated arrangement of elements and the increase in chip area due to the increase in the number of elements, the means of (2) is adopted. In other words, the configuration shown in FIG. 1 is preferable, and when the gain of the amplifier is not saturated, high efficiency can be obtained by the means (2).

According to the above-mentioned means (3), negative feedback can be applied by the insertion connection of the inductor, and the circuit is stabilized.

According to the means (4), (a) the second resistor causes a base voltage drop with an increase in the base current due to the temperature rise of the entire multi-finger HBT. Suppressed and thermal runaway is suppressed.

(B) The first resistor stabilizes each transistor by preventing an excessive increase in gain due to high-frequency loss, thereby preventing oscillation.

(C) In addition, the first resistor causes a different base voltage drop for each finger with a difference in base current increase due to a temperature rise difference between each HBT finger (unit transistor). This reduces the concentration of current on one finger and allows each finger to operate uniformly.

(D) By inserting and connecting the first resistor, the second resistor, and the first capacitor, it is possible to provide a highly efficient and small wireless communication device. For example, in a high-frequency power amplifier module, an HBT is used and the number of transistors is reduced to one.
When the number is about 00 and the emitter size is about 2 μm × 20 μm, an output of about 4 W can be obtained. At this time,
When the current amplification factor is about 80, the first capacitance is 0.15 pF.
The first resistance is about 100 ohms, and the second resistance is about 1 kohm, which can achieve an efficiency of about 70% (see FIGS. 7 and 8). During this high-efficiency operation, the DC current flowing through the first resistor is about 0.2 to 0.5 mA, and the voltage drop at the first resistor is sufficiently small, 20 to 50 mV, and the loss is small. As shown in FIG. 9, the change in efficiency is small until the value of the first resistor is 2.5 times, that is, about 250 Ω (2.5 Ω when 100 pieces are connected in parallel). 25 mV, which is sufficiently small. This means that the efficiency of the wireless communication device is about 60%, and a highly efficient wireless communication device can be achieved.

(E) In the element arrangement, only the first resistor needs to be arranged for each HBT, and the second resistor and the first capacitor are arranged in such a manner that the difference in thermal resistance between them is reduced. HBTs may be provided for each block of HBTs, thereby increasing the degree of freedom in element arrangement. Also, the area of the isolation region between the elements is reduced by reducing the total number of the resistance / capacitance elements. This facilitates designing a low-cost chip (semiconductor device) with a reduced area.

[0045]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIGS. 1 to 9 relate to a wireless communication apparatus and a semiconductor device (semiconductor element) according to an embodiment (Embodiment 1) of the present invention. In the first embodiment, an example of a semiconductor element (semiconductor chip) using a heterojunction bipolar transistor (HBT) as a semiconductor amplifying element will be described.

FIG. 1 shows a single-stage amplifier (high-frequency power amplification module 1) incorporating one HBT at the output side on the transmission side, and an antenna 2 connected to the high-frequency power amplification module 1 via a filter (not shown). FIG. 3 is a schematic circuit diagram of a part of the wireless communication device. FIG. 2 is a schematic diagram showing a state in which the high-frequency power amplification module 1 packaged on a wiring board 10 of a wireless communication device such as a mobile phone is mounted. External terminals (electrodes) are provided on the lower surface of the high-frequency power amplifier module 1, respectively, and these electrodes are mechanically and electrically connected to predetermined wirings 11 provided on the wiring board 10 via bonding materials. The antenna 2 is connected to the wiring 11 that is electrically connected to the output terminal of the high-frequency power amplification module 1 via the conducting wire 12.

The high-frequency power amplification module 1 has, as external terminals, an input terminal (RFin), an output terminal (RFout),
It has a first voltage terminal (Vcc: collector terminal), a second voltage terminal (GND: emitter terminal), and a control terminal (Vapc: base terminal) as a bias terminal. The antenna 2 is connected to the output terminal via a filter or the like (not shown).

The amplifier of the high-frequency power amplification module 1
It is composed of a heterojunction bipolar transistor (HBT) incorporated in a semiconductor chip (semiconductor element).
This HBT becomes a multi-finger transistor, and N
It has a structure in which a number of transistors are connected in parallel, and constitutes a high-output amplifier. The transistors Q1A to Q1N have an emitter terminal 5, a base terminal 6, and a collector terminal 7, respectively.
It is constituted by. Each terminal (finger) is bundled into one, and becomes a base terminal, an emitter terminal, and a collector terminal, respectively. The collector terminal is connected to an output terminal (RFout) via a matching circuit 9. The collector electrode is connected to a first voltage terminal (Vcc: collector terminal) via an inductor Lc. Leakage of a high frequency (RF) signal is suppressed by the inductor Lb, and the power supply potential is stabilized.

The circuit according to the first embodiment has a structure in which an input terminal and a bias terminal (control terminal) are separated, and a first capacitance as a junction capacitance is provided between the base terminal 6 of each of the transistors Q1A to Q1N and the input terminal. C2A to C2N and first resistors R1A to R1N as ballast resistors are inserted and connected in series. Further, the first resistors R1A to R1N
Second resistors R2A to R2N that cause a voltage drop are inserted and connected between a node between the first capacitors C2A to C2N and the bias terminal (control terminal).

The second resistors R2A to R2N are connected to the first resistors R1A to R1N.
The resistance value is larger than that. This is because, when the temperature of the semiconductor chip rises and the current flowing through the HBT increases, a voltage drop occurs to suppress thermal runaway of the HBT. In order to suppress this thermal runaway,
For example, the resistance values of the second resistors R2A to R2N are about ten times larger than the resistance values of the first resistors R1A to R1N. Second resistors R2A-R
By inserting and connecting 2N, the first resistors R1A to R1N can be reduced.

The multi-finger HBT is, for example, an HBT having InGaP as an emitter and GaAs as a base and a collector.

FIG. 3 is a schematic plan view showing a part of a semiconductor element (semiconductor chip) constituting an amplifier including an HBT, and corresponds to the circuit of FIG. FIG. 4 shows A-
FIG. 5 is a cross-sectional view along the line A ′, and FIG. 5 is a cross-sectional view along the line BB ′ in FIG.

As shown in FIG. 3, a plurality of first capacitors C2A to C2N (also simply referred to as a capacitor C2) are arranged side by side in the center of the drawing.
Is arranged. One electrode of the first capacitors C2A to C2N (capacitor lower layer wiring metal 16) is connected to the input terminal (RFin). The other capacitor electrode (wiring metal 15) is connected to one end of first resistors R1A to R1N (also simply referred to as resistor R1) of the transistor. Capacitor lower layer wiring metal 16
The capacitance C2 (see FIG. 5) is formed by interposing the capacitance insulating film 14 in the intersecting region of the wiring metal 15 and the capacitor C2. The other end of the resistor R1 is connected to another independent wiring metal 15, and this wiring metal 15 is connected to transistors Q1A to Q1N.
Are connected to the base terminal 6 (portion indicated by 41 in FIG. 5).

Each of the collector terminals 7 (portion 40 in FIG. 5) of the transistors Q1A to Q1N is connected to another independent wiring metal 15. This wiring metal 15 is connected to an output terminal (RFout). Also, the emitter terminal 5
(A part indicated by 42 in FIG. 5) is another independent wiring metal 1
5 (ground line) is connected. This ground line is connected to the back surface electrode 22 (provided on the back surface (lower surface) of the semiconductor chip (semiconductor element: semiconductor amplifying element) via the conductor 19 filled in the via hole and the etching stopper 21 made of the conductor provided thereunder. GND) (see FIG. 4).

On the other hand, the other electrode (wiring metal 15) of the capacitor C2 is connected to one end of second resistors R2A to R2N (also simply referred to as a resistor R2). Another independent wiring metal 15 is connected to the other end of the resistor R2. The wiring metal 15 is connected to a bias terminal (control terminal: base terminal). With such a structure, the amplifier circuit of FIG. 1 is configured.

Next, referring to FIGS. 4 and 5,
A cross-sectional structural relationship between the HBT, the capacitor C2, the resistor R1, and the resistor R2 will be described. A semiconductor amplifying element incorporating these capacitance C2, resistor R1 and resistor R2 is:
It is formed monolithically on a semi-insulating GaAs substrate 30. It should be noted that dimensions and the like of each part that are not particularly required in the present invention are omitted.

An n ⁺ -type GaAs sub-collector layer 31 is provided on a semi-insulating GaAs substrate 30, and an n-type GaAs sub-collector layer 31 is provided on the n ⁺ -type GaAs sub-collector layer 31.
An aAs collector layer 32 is provided. Further, the n
The type GaAs collector layer 32 has a mesa portion which is selectively removed by etching to an intermediate depth and partially protrudes. In a region where the thin n-type GaAs collector layer 32 deviated from the mesa portion is formed, the n-type GaAs collector layer 32 is partially etched away, and a collector electrode 40 is provided in the removed portion.

On the mesa portion, a p ⁺ -type GaAs base layer 33, an n-type InGaP emitter layer 34, an n ⁺ -type GaAs
The cap layers 35 are provided so as to sequentially overlap. p
^{The +} type GaAs base layer 33 and the n type InGaP emitter layer 34 coincide and overlap with substantially the same size, but the n ⁺ type GaAs cap layer 35 is formed in an elongated rectangular shape at the center of the mesa portion.

In the mesa region deviating from the n ⁺ -type GaAs cap layer 35, the n-type InGaP emitter layer 34 and the n ⁺ -type GaAs cap layer 35 are selectively etched away to form contact holes. Is provided with a base electrode 41.

The upper surface of the semi-insulating GaAs substrate 30 is covered with an insulating film 45 for protecting the surface, and a middle layer of the insulating film 45 has a resistor R as shown in FIG.
1, a resistor R2 and a capacitor C2 are formed. When a laminated film of SiO ₂ and SiN is used as the capacitance insulating film 14, a capacitance with low leakage current can be formed. Further, by using a high dielectric substance such as strontium titanate (STO) or barium strontium titanate (BST) or tantalum oxide (Ta ₂ O ₅ ) as another material, the area of the capacitor C2 can be reduced, and the chip area can be reduced. Can be reduced. When a nitride of a high melting point metal such as WN, WSiN, TiN, or TaN is used as a resistor material, a resistor having excellent reliability can be formed. Also, a NiCr alloy or the like can be applied to the resistor.

The insulating film 45 is partially etched away to form a contact hole, and the wiring metal 15 formed by patterning the electrodes of the HBT, the electrodes of the resistors R1 and R2, and the electrodes of the capacitor C2. Make electrical contact. Before the uppermost insulating film is formed, the n ⁺
An emitter electrode 42 (two layers in the figure) is formed on the type GaAs cap layer 35. Then, by forming the wiring metal 15 after the formation of the contact hole, each wiring metal 15 is connected to the emitter electrode 42, the base electrode 41, and the collector electrode 40, and also connected to each electrode of each capacitor and resistor, and FIG. The circuit shown in FIG.

The HBT according to the first embodiment includes a transistor Q1A
The number of Q1N is, for example, 100 (N = 100). And, for example, the emitter size is 2 μm × 2
0 μm, the current amplification factor is approximately 80,
The capacitances C2A to C2N are about 0.15 pF, and the first resistors R1A to R1R
1N is about 100 ohm, and the second resistors R2A to R2N are about 1 kohm. In this configuration, the output of the high-frequency power amplification module 1 is about 4 W. In this case, the efficiency of the high-frequency power amplifier module 1 is about 70%, and as a result, the efficiency of the wireless communication device is as high as about 60%.

FIG. 6 shows the first embodiment (the present invention).
FIG. 7 is a graph showing the change of the stabilization coefficient with respect to the collector current by the circuits of the conventional example 1 and the conventional example 2, and FIG. Efficien
FIG. 8 is a graph showing the correlation between the input power (Pin) and the collector current and the additional efficiency by the circuits of Conventional Example 1 and Conventional Example 2, and FIG.
Is the first resistor R1 in the difference between the total resistance (Rtotal) of the first resistor and the second resistor according to the circuit of the first embodiment.
4 is a graph showing a correlation between a stabilization coefficient K and an addition efficiency. These data are comparisons of a circuit in which the efficiency of the high-frequency power amplifier module is as high as about 70% and that of the wireless communication device is about 60%.

As shown in the graph of FIG. 6, the stabilization coefficient K of the conventional example 1 is less than 0.5, and the oscillation phenomenon easily occurs. Also, in the conventional example 2 in which the capacitors C1A to C1N are connected in parallel to the resistors R1A to R1N, the collector current is 0.01 A to 0.1.
At about 04A, the stabilization coefficient K is about 0.5, and even when the collector current is about 1.5A, the stabilization coefficient K is less than 0.9 at most, and oscillation may occur.

In the circuit configuration of the conventional example 2, the resistance R1A
Capacitors C1A to C1N connected in parallel to R1N increase to about 50 pF, and the area for forming the capacitances C1A to C1N increases, so that the semiconductor chip (semiconductor device) incorporating the HBT, the resistor, and the capacitor also increases.

FIG. 8 is a graph showing the case of the circuit of the prior art 1 and the graph of FIG.
It is a comparison of the additional efficiency between the case where the capacitances C1A to C1N are 25 pF in the conventional example 2 and the case where the capacitance is set to 50 pF. It can be seen that when the capacitances C1A to C1N are 25 pF, the additional efficiency is low, and the device cannot be used.

FIG. 7 is a curve showing the additional efficiency in the case of the circuit of the first embodiment (the present invention) and in the case of the circuit of the conventional example 1. When the input power is 23 dBm or less, the circuit of the first conventional example has a somewhat higher addition efficiency (PAE) than the circuit of the present invention. However, when the input power is about 25 dBm, the circuit of the present invention does not. However, as in the case of the circuit of the conventional example 1, it can be seen that the additional efficiency is as high as about 70% and there is no inferior. If the input power is 25 dBm, the output power can be 35 dBm.

FIG. 9 shows the first embodiment of the circuit of the first embodiment.
A resistance value obtained by connecting 100 resistors in parallel is represented by R1, and a resistance value obtained by connecting 100 series of the first resistor and the second resistor is represented by Rtota.
l, and Rtotal is 7Ω, 10Ω, 1
Resistor R1 at 3Ω, 16Ω and 20Ω
Is changed to 0.5Ω to 3Ω (PA)
It is a graph which shows E).

In order not to cause an oscillation phenomenon, it is necessary to set the stabilization coefficient K to 1 or more. When the stabilization coefficient K is 1, Rtotal is 7Ω, 10Ω, 13Ω, 16Ω.
The additional efficiency can be increased to about 64% even in the state of Ω and 20Ω. Even when the stabilization coefficient K is 2, Rto
When tal is smaller than 16Ω, the additional efficiency is 63
% Can be kept high.

The wireless communication device according to the first embodiment has the following effects by incorporating the semiconductor device (semiconductor element) according to the first embodiment.

(1) Since the second resistor causes a base voltage drop with an increase in the base current due to the temperature rise of the HBT chip (semiconductor device), the increase in the current of each transistor is suppressed and the thermal runaway is suppressed.

(2) Further, the first resistor causes high-frequency loss and prevents an excessive increase in gain, thereby stabilizing each transistor and preventing oscillation.

(3) A highly efficient wireless communication device can be provided by inserting and connecting the first resistor, the second resistor, and the first capacitor. For example, in a high-frequency power amplifier module, if an HBT is used, the number of transistors is about 100, and the emitter size is about 2 μm × 20 μm, an output of about 4 W can be obtained. At this time, if the current gain is about 80, the first capacitance is about 0.15 pF,
The resistance can be about 100 ohms, the second resistance can be about 1 kohm, and an efficiency of about 70% can be achieved. This means that the efficiency of the wireless communication device is about 60%, and a highly efficient wireless communication device can be achieved.

(4) Runaway and oscillation of the amplifier due to temperature fluctuations and power supply fluctuations are unlikely to occur, and stable communication can be performed without interrupting transmission of radio signals.

(Embodiment 2) FIGS. 10 and 11 are diagrams relating to a wireless communication apparatus according to another embodiment (Embodiment 2) of the present invention, and FIG. 10 shows a multi-stage high frequency power amplifier module and the like. FIG. 11 is a block diagram, and FIG. 11 is a schematic plan view showing a layout of each electronic component of the high-frequency power amplifier module.

In the second embodiment, an example will be described in which the present invention is applied to a three-stage amplifier (multistage amplifier) in which amplifiers (semiconductor amplifiers) including HBTs, resistors, and capacitors are sequentially cascaded. This multi-stage amplifier is incorporated in the transmission-side output stage of the wireless communication device.

As shown in FIG. 10, the radio communication apparatus includes an impedance matching circuit MN1, amp1 (first-stage amplifier), an impedance matching circuit MN2, amp2 (middle-stage amplifier) between an input terminal (RFin) and an output terminal (RFout).
The configuration is such that an impedance matching circuit MN3, amp3 (final stage amplifier) and an impedance matching circuit MN4 are inserted and connected in series. Each high power amplifier (amp1 to a
mp3) control terminal (base terminal: bias1, bias)
2, bias3) are bias terminals (control voltages: Vapc1, Vapc1, which are output signals of the base bias circuit 50).
2, Vapc3) is input to control the amplification factor. Each of the high-output amplifiers (amp1 to amp3) has the circuit configuration according to the first embodiment.

FIG. 11 is a layout of each electronic component in the high-frequency power amplifier module 1. A base bias circuit 50 is configured as a semiconductor chip (semiconductor element).
There are biascircuit, amp1, amp2, and amp3.
Each electrode of the semiconductor chip and a predetermined wiring are conductive wires 5
1 is connected. The electrodes of the chip capacitor and the chip inductor are electrically connected to predetermined wirings by means of solder (not shown) or the like.

In the amplifiers amp1, amp2, and amp3, a transistor and first, second, and first capacitors connected to the transistor are schematically illustrated.

In the first embodiment, the base bias circuit 50
Although not particularly specified, it is assumed that, for example, the high-output amplifier of each stage is controlled by a constant control voltage (Vapc). Depending on the base bias circuit 50, it is also possible to control each stage of the high-output amplifier with a predetermined control voltage, an example of which will be described later.

The wireless communication apparatus incorporating the multi-stage amplifier high-frequency power amplification module 1 of the second embodiment has the same effect as that of the first embodiment. It is possible to provide a wireless communication device with high communication performance by increasing the output, increasing the output controllability by the bias control circuit, and linearizing the output.

(Embodiment 3) FIG. 12 is a circuit diagram showing a part of a wireless communication apparatus according to another embodiment (Embodiment 3) of the present invention. In the third embodiment, in the circuit configuration of the amplifier of the first embodiment, the inductor Lb is provided between the base terminal and the second resistor group, and the inductor Le is provided between the emitter and GND.
Is inserted and connected. By inserting and connecting the inductor Lb, the impedance in anticipation of the base power supply circuit increases, and the high frequency (R
F) Signal leakage can be suppressed, and loss due to leakage can be reduced, so that high efficiency can be achieved. Also, by inserting and connecting the inductor Le, negative feedback is applied and the circuit is stabilized. Since the effects of the inductor Lb and the inductor Le are independent of each other, it goes without saying that the above-described effects are produced even when only the inductor Lb or only the inductor Le is provided.

(Embodiment 4) FIG. 13 is a circuit diagram showing a part of a wireless communication apparatus according to another embodiment (Embodiment 4) of the present invention. In the fourth embodiment, in the circuit configuration of the first embodiment, a bypass capacitor for passing a high-frequency component signal in parallel to the first resistors R1A to R1N, which are ballast resistors,
It has a structure in which capacitors C1A to C1N are connected. In the fourth embodiment, by providing the second resistors R2A to R2N between the base terminal and the base terminal 6, the first resistors R1A to R1N are provided.
Can be reduced, the second capacitance C1A which is a bypass capacitance
To C1N can also be reduced. For example, the first resistor R
Since 1A to R1N can be about 100Ω, the second
The capacitance values of the capacitors C1A to C1N can be reduced to about 5 pF.
Conventionally, for example, the capacitance was about 50 pF, but it can be reduced to about 1/10 of that, about 5 pF, and the chip area can be reduced by the capacitance. As a result,
The area for forming the capacitor is reduced, the size of the semiconductor chip is reduced, and the number of semiconductor chips obtained from one semiconductor substrate (wafer) is increased, so that the manufacturing cost of the semiconductor amplifier can be reduced.

Further, since the circuit configuration is a combination of the first resistor, the second resistor, the first capacitor, and the second capacitor, the degree of freedom in designing a semiconductor amplifier and a high-frequency power amplifier module is increased.

[0086] The inductor Lb increases impedance in anticipation of the base power supply circuit, suppresses leakage of high frequency (RF) signals to the base power supply circuit, and reduces loss due to leakage, thereby achieving high efficiency. The inductor Le applies negative feedback to stabilize the circuit. Therefore, in this circuit, high efficiency and stabilization can be achieved.

Since the effects of the inductor Lb and the inductor Le are independent of each other, it goes without saying that the above-described effects are produced even when only the inductor Lb or only the inductor Le is provided. Also, if a transmission line or the like is formed on the substrate instead of these inductances and designed so that the impedance seen from each terminal becomes an appropriate value, it goes without saying that the inductance element is not necessarily used.

(Embodiment 5) FIGS. 14 to 16 relate to a wireless communication apparatus according to another embodiment (Embodiment 5) of the present invention. FIG. FIG. 15 is a circuit diagram showing a bias control circuit incorporated in the high-frequency power amplifier module, and FIG. 16 is a schematic plan view showing a layout of each electronic component of the high-frequency power amplifier module.

In the fifth embodiment, as shown in FIG. 14, a current mirror diode (sensor diode) 56 is monolithically integrated on the same semi-insulating semiconductor substrate on which the amplifier body transistor 55 is formed. ing. The main body transistor 55 has the same circuit configuration as that of the first embodiment, and connects first capacitors C2A to C2N and first resistors R1A to R1N in series between an input terminal (RFin) and a base terminal 6, and A node between the first capacitors C2A to C2N and the first resistors R1A to R1N and a control terminal (Vap
c), the second resistors R2A to R2N are inserted and connected.

The sensor diode 56 comprises a diode-connected transistor Qs. This transistor Qs is made of HBT. A resistor Rs1 and a resistor Rs2 are inserted and connected in series between the base and the collector of the transistor Qs for diode connection. The collector terminal of the transistor Qs becomes Vd and the emitter terminal becomes G
ND.

Since the current mirror diode 56 is provided on the same semi-insulating semiconductor substrate, the temperature of the semi-insulating semiconductor substrate rises, and the current amount of the main body transistor 55 increases. Since the amount of current of the diode 56 also increases, the current flowing through the current mirror diode 56 is controlled to be constant, so that the current flowing through the body transistor 55 can be controlled to be constant even when the temperature fluctuates, so that the bias controllability is improved. I do. That is, the sensor diode is on the same chip as the amplification transistor, and experiences the same temperature fluctuation as the amplification transistor. The current-voltage characteristics between the base and the emitter of the transistor and the diode have strong temperature dependence, but show the same current-voltage characteristics at the same temperature.
Therefore, a constant current Id in the sensor diode
And drive the base of the transistor with the same voltage as the voltage generated there, so that the current flowing through the transistor is constant (regarding the junction area ratio between the sensor diode of Id and the base-emitter of the body transistor) regardless of the temperature change. Times) can be controlled. Note that the same effect as described above can be obtained by using a sensor transistor instead of the sensor diode.

In FIG. 10, the base bias circuit 50
As shown in FIG. 15, unlike the case of the second embodiment, the first-stage amp1 has a bias (Vapc1) that generates control in by controlling the voltage divided by the resistors Rc1 and Rc2.
And the middle and final stages of amps 2 and 3 are biased (Vapc2, Vapc2) for generating control-in via an emitter follower by transistors Qb1 and Qb2.
Control in 3). The transistor Qs2 connected to the transistor Qb1 is the main body transistor 55 of the amp2.
The transistor Qs3 connected to the transistor Qb2 is a current mirror diode 56 monolithically formed with the main transistor 55 of the amp3. These transistors Qs2 and Qs3 are used as reference voltages when the control-in is generated via the emitter followers by the transistors Qb1 and Qb2.

The inductors Lb1 to Lb3 are provided to suppress the leakage of the high frequency signal component from each control terminal (Vapc1, Vapc2, Vapc3).

In the base bias circuit 50, the control terminal Vapc1 receives a control voltage obtained by voltage division of a resistor, the control terminal Vapc2 receives a control current amplified by the amplification factor of the transistor Qb1, and the control terminal Vapc3. Is the transistor Q
The control current amplified by the amplification factor of b2 is input.

FIG. 16 is a layout of each electronic component in the high-frequency power amplifier module 1 according to the fifth embodiment. As the semiconductor chip, there are a bias circuit, amp1, amp2, and amp3 that constitute the base bias circuit 50. Each electrode of the semiconductor chip and a predetermined wiring are connected by a conductive wire 51. The electrodes of the chip capacitor and the chip inductor are electrically connected to predetermined wirings by means of solder (not shown) or the like.

[0096] In amp1, amp2 and amp3, a transistor and a first resistor, a second resistor, and a first capacitor connected to the transistor are schematically illustrated. In addition, in amp2 and amp3, the current mirror diode is clearly shown without reference numeral. The current mirror diode 56 shown in FIG.
Rs2 is omitted.

(Embodiment 6) FIG. 17 is a circuit diagram showing a part of a wireless communication apparatus according to another embodiment (Embodiment 6) of the present invention. In the sixth embodiment, in the circuit configuration of the first embodiment, a ballast resistor and a circuit stabilizing resistor of some (all in the case of FIG. 17) transistors arranged so that the difference in thermal resistance therebetween is small. 1 resistor R1A-R
1N is connected to one node on the side opposite to the side connected to the base terminal 6, and a second resistor R2 is inserted and connected as a single resistor between the node and the bias supply terminal. And a first capacitance C2 as a single junction capacitance
Is inserted and connected.

In the sixth embodiment, (a) R2 causes a base voltage drop with an increase in the base current due to the temperature rise of the whole multi-finger HBT. Therefore, the current increase of the whole multi-finger HBT is suppressed and the thermal runaway is suppressed. Is done.

(B) In addition, the first resistors R1A to R1N become high-frequency losses and prevent an excessive increase in gain, thereby stabilizing each transistor and preventing oscillation.

(C) The first resistors R1A to R1N are connected to each HB
A difference in base current increase due to a difference in temperature rise of the T-finger causes a different base voltage drop for each finger. Therefore, a difference in collector current is reduced, and current is prevented from being concentrated on one finger. Operate uniformly.

(D) In the element arrangement, only the first resistors R1A to R1N need to be arranged for each HBT, and a plurality of R2 and C2 are arranged so that the difference in thermal resistance between them is small. Since it may be provided for each block of the HBT, the degree of freedom of element arrangement is increased, and the area of the isolation region between elements is reduced by reducing the total number of resistance / capacitance elements. Further, since R2 and C2 need only be provided for each block composed of a plurality of HBTs, not only the area can be reduced, but also there is a degree of freedom in externally providing a capacitance.

In the present embodiment, “disposed so that the difference in thermal resistance between them is small” means that the thermal resistance between the elements is approximately 1/5 or less of the thermal resistance of the entire element. In this case, thermal stability can be obtained if the ratio of the resistance and the resistance R2 when N pieces of R1 are connected in parallel is about twice the ratio of the thermal resistance difference between the elements and the thermal resistance of the entire element. This has been shown experimentally. For example, if the thermal resistance of the entire device is 20 ° C./W and the thermal resistance difference between the devices is 2 ° C./W, the parallel resistance of the first resistors R1A to R1N to 2 ohms, R2 = 8
Thermal stability was obtained at about ohms. Assuming that the number of transistors is 100, R1A = R1N = 200Ω, and R2
= 8Ω and a case where 100 R2A = R2N = 800Ω are arranged as in the first embodiment, the former can reduce the element area to 60% of the latter.

In this embodiment, the first resistors R1A to R1N
Is connected to one node between the input terminal and
It is not necessary to integrate 2 and C2 with the transistor, and it is possible to place the R2 and C1 elements on the substrate outside the transistor chip. In this case, the transistor chip area can be significantly reduced, and the transistor chip area of the first embodiment can be reduced.
The chip area could be reduced to 0%.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof. Needless to say. For example, in the embodiment, the semiconductor amplifying element used for the amplifier is HB
Although T was used, a bipolar transistor made of silicon can be applied in the same manner, and the same effect can be obtained. The invention is applicable at least to high frequency amplification techniques.

[0105]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) It is possible to provide a wireless communication device that can suppress thermal runaway, has high efficiency, and hardly causes an oscillation phenomenon.

(2) Since the capacitance value of the capacitance to be used can be reduced, the size of the semiconductor chip (semiconductor device) can be reduced and the manufacturing cost can be reduced.

(3) The stability and efficiency of the wireless communication device can be improved by inserting and connecting an inductor to the base terminal and the emitter terminal.

(4) By adopting the current mirror configuration,
Bias controllability can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a part of a wireless communication device according to an embodiment (Embodiment 1) of the present invention.

FIG. 2 is a schematic perspective view showing a part of the wireless communication device according to the first embodiment.

FIG. 3 illustrates a part of a semiconductor chip (semiconductor device) in which an HBT having a multi-finger structure and an amplifier including a first capacitor, a first resistor, a second resistor, and the like, which are incorporated in the wireless communication device according to the first embodiment, are formed. It is a schematic plan view shown.

FIG. 4 is a cross-sectional view taken along line AA ′ of FIG.

FIG. 5 is a sectional view taken along the line BB ′ in FIG. 3;

FIG. 6 is a graph showing a correlation between a collector current and a stabilization coefficient K.

FIG. 7 is a graph showing the correlation between input power and collector current and additional efficiency.

FIG. 8 is a graph showing a correlation between input power (Pin) and collector current and load efficiency (PAE).

FIG. 9 shows a total resistance (Rtota) of a first resistor and a second resistor.
l) The difference between the first resistor R1 and the stabilization coefficient K
6 is a graph showing a correlation between the load efficiency and the load efficiency (PAE).

FIG. 10 is a block diagram showing a multi-stage high-frequency power amplification module and the like in a wireless communication device according to another embodiment (Embodiment 2) of the present invention.

FIG. 11 is a schematic plan view showing a layout of each electronic component of the high-frequency power amplifier module according to the second embodiment.

FIG. 12 is a circuit diagram showing a part of a wireless communication apparatus according to another embodiment (Embodiment 3) of the present invention.

FIG. 13 is a circuit diagram showing a part of a wireless communication apparatus according to another embodiment (Embodiment 4) of the present invention.

FIG. 14 is a circuit diagram showing a part of a wireless communication apparatus according to another embodiment (Embodiment 5) of the present invention.

FIG. 15 is a bias control circuit diagram of a high-frequency power amplifier module incorporated in the wireless communication device of the fifth embodiment.

FIG. 16 is a schematic plan view showing a layout of each electronic component of the high-frequency power amplifier module according to the fifth embodiment.

FIG. 17 is a circuit diagram showing a part of a wireless communication apparatus according to another embodiment (Embodiment 6) of the present invention.

FIG. 18 is a circuit diagram showing a part of a wireless communication device employing a conventional circuit.

FIG. 19 is a circuit diagram showing a part of a wireless communication device employing a conventional circuit.

FIG. 20 is a circuit diagram showing a part of a wireless communication device employing a conventional circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... High frequency power amplification module, 2 ... Antenna, 5 ... Emitter terminal, 6 ... Base terminal, 7 ... Collector terminal, 9 ...
Matching circuit, 10: wiring board, 11: wiring, 12: conducting wire,
14: Capacitive insulating film, 15: Wiring metal, 16: Capacitor lower layer wiring metal, 19: Conductor, 20: Wiring, 21: Etching stopper, 22: Back electrode, 30: Semi-insulating GaAs substrate, 31: n ⁺ type GaAs subcollector layer, 32 ... n-type GaAs collector layer, 33 ... p ⁺ -type GaAs base layer,
34 ... n-type InGaP emitter layer, 35 ... n ⁺ type GaA
s cap layer, 40 ... collector electrode, 41 ... base electrode, 42 ... emitter electrode, 45 ... insulating film, 50 ... base bias circuit, 51 ... wire, 55 ... body transistor, 56 ... diode for current mirror (sensor diode), 57: current mirror transistor (sensor transistor), C2A to C2N: first capacitance, C1A to C1N
... second capacitor, GND ... second voltage terminal (emitter terminal),
R1A to R1N: first resistor, R2A to R2N: second resistor, RFin
... Input terminal, RFout ... Output terminal, Vapc ... Control terminal (base terminal), Vcc ... First voltage terminal (collector terminal).

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04B 1/04 H04B 1/04 N

Claims (23)

[Claims] 1. A wireless communication device having a high-frequency power amplification module at a transmission-side output stage and having an antenna connected to the high-frequency power amplification module, wherein the high-frequency power amplification module has an input terminal and an output terminal. A control terminal, a first voltage terminal, a second voltage terminal, a first terminal, a second terminal, and a control terminal for controlling a current flowing between the first terminal and the second terminal. A plurality of high-output amplifiers connected in parallel; a first capacitor connected between the input terminal and the control terminal of each of the transistors; a first capacitor connected to the input terminal; and a series connected to the first capacitor. A first resistor connected and connected to the control terminal; a first resistor disposed between the control terminal and a control terminal of each of the transistors; A second resistor connected to a node between the first capacitors, the output terminal is connected to each first terminal of the transistor, and the first voltage terminal is connected to a first terminal of each transistor. A wireless communication device, wherein the second voltage terminal is a high-frequency power amplifier module connected to a second terminal of each of the transistors. 2. A wireless communication device having a high-frequency power amplification module in a transmission-side output stage and having an antenna connected to the high-frequency power amplification module, wherein the high-frequency power amplification module has an input terminal and an output terminal. A control terminal, a first voltage terminal, a second voltage terminal, a first terminal, a second terminal, and a control terminal for controlling a current flowing between the first terminal and the second terminal. A plurality of high-output amplifiers connected in parallel; a first capacitor connected between the input terminal and the control terminal of each of the transistors; a first capacitor connected to the input terminal; and a series connected to the first capacitor. A first resistor connected and connected to the control terminal; a second capacitor connected in parallel to the first resistor; controlling the control terminal and each of the transistors; A second resistor connected to a node between the first resistor and the first capacitor, wherein the output terminal is connected to a first terminal of each of the transistors; A wireless communication device comprising a high-frequency power amplifier module having one voltage terminal connected to a first terminal of each of the transistors, and the second voltage terminal connected to a second terminal of each of the transistors. 3. The method according to claim 2, wherein a DC voltage drop during operation of each of said transistors is about 0.15 V or less, a resistance value of said first resistor is about 1 Ω or less, and a capacitance value of said second capacitor is about 5 pF or less. The wireless communication device according to claim 2, wherein 4. The high-frequency power amplifier module has a multi-stage configuration in which a plurality of the high-power amplifiers are sequentially connected in cascade. Each control terminal of a first-stage high-power amplifier is connected to the input terminal. Each first terminal is connected to the output terminal, each control terminal of the middle-stage high-power amplifier is connected to the first terminal of the previous-stage high-power amplifier, and each first terminal is connected to the control terminal of the subsequent-stage high-power amplifier. The first capacitor, the first resistor, and the second resistor are incorporated in at least one of a first stage, a middle stage, and a final stage, and a control terminal of each stage of the high output amplifier has a predetermined The wireless communication device according to claim 1, wherein a control voltage is applied. 5. The high-frequency power amplifier module has a multi-stage configuration in which a plurality of the high-output amplifiers are sequentially connected in cascade, each control terminal of a first-stage high-output amplifier is connected to the input terminal, Each first terminal is connected to the output terminal, each control terminal of the middle-stage high-power amplifier is connected to the first terminal of the previous-stage high-power amplifier, and each first terminal is connected to the control terminal of the subsequent-stage high-power amplifier. And the first capacitor, the first resistor, the second resistor, and the second capacitor are incorporated in at least one of a first stage, a middle stage, and a last stage, and a control terminal of the high output amplifier in each stage. The wireless communication device according to claim 2, wherein a predetermined control voltage is applied to each of the wireless communication devices. 6. The wireless communication apparatus according to claim 1, wherein an inductance is connected between the control terminal and the second resistor. 7. The wireless communication device according to claim 1, wherein an inductance is connected between the second voltage terminal and the second terminal. 8. The wireless communication apparatus according to claim 1, wherein the transistors constituting the high-power amplifier are formed monolithically on a single semiconductor substrate. 9. The wireless communication device according to claim 8, wherein a sensor transistor constituting a current mirror circuit is monolithically formed on the semiconductor substrate. 10. The wireless communication apparatus according to claim 8, wherein a sensor diode constituting a current mirror circuit is monolithically formed on said semiconductor substrate. 11. A wireless communication device having a high-frequency power amplifier module at a transmission-side output stage and having an antenna connected to the high-frequency power amplifier module, wherein the high-frequency power amplifier module has an input terminal, an output terminal A control terminal, a first voltage terminal, a second voltage terminal, a first terminal, a second terminal, and a control terminal for controlling a current flowing between the first terminal and the second terminal. A plurality of high-output amplifiers connected in parallel; a first resistor connected to a control terminal of each of the transistors; and a single first resistor connected in series to each of the first resistors and connected to the input terminal. A second resistor connected in series with each of the first resistors and connected to the control terminal, and the output terminal is connected to a first terminal of each of the transistors. Is, the first voltage terminal connected to the first terminal of each transistor, the second voltage terminal to a wireless communications apparatus that a high-frequency power amplifier module connected to the second terminal of the respective transistors. 12. A high-power amplifier comprising a plurality of transistors arranged in one or a plurality of blocks, each of which has the first capacitance and the second resistor. Item 12. The wireless communication device according to item 11. 13. The wireless communication apparatus according to claim 12, wherein a difference in heat radiation heat resistance between the transistors in each block is smaller than a heat radiation heat resistance of the high-power amplifier. 14. The ratio of the heat dissipation thermal resistance of the high-power amplifier to the deviation of the heat dissipation thermal resistance between the transistors in each of the blocks, wherein the ratio of the heat dissipation thermal resistance of the plurality of first resistors connected in parallel to each block is the second resistance. 14. The wireless communication apparatus according to claim 13, wherein the ratio is about 1/2 or less of the ratio of the sum of the two resistances and the parallel resistance of the first resistor. 15. A plurality of transistors each comprising an input terminal, an output terminal, a bias terminal, a first terminal, a second terminal, and a control terminal for controlling a current flowing between the first terminal and the second terminal. A high-output amplifier configured to be connected in parallel; first capacitors C2A to C2N and first capacitors C2A to C2N connected between the input terminals and the control terminals of the transistors, respectively, and connected to the input terminals. To C2N, connected in series to the control terminal, and first resistors R1A to R1N, respectively disposed between the bias terminal and the control terminal of each of the transistors, the first resistors R1A to R1N and A second resistor R connected to a node between one capacitor C2A to C2N
2A to 2N, wherein the output terminal is connected to each first terminal of the transistor. 16. The semiconductor device according to claim 15, further comprising second capacitors C1A to C1N connected in parallel to said first resistors R1A to R1N. 17. A plurality of transistors each comprising the terminal, an output terminal, a bias terminal, a first terminal, a second terminal, and a control terminal for controlling a current flowing between the first terminal and the second terminal. A high-power amplifier configured to be connected in parallel, a single first capacitor C2 disposed between the input terminal and the control terminal of each transistor, and connected to the input terminal; A first resistor R1A to R1N connected in series to C2 and connected to the control terminal; and a first resistor R1A to R1N disposed between the bias terminal and the control terminal of each transistor, respectively. A single second resistor R connected to a node between the capacitors C2
2. The semiconductor device according to claim 1, wherein the output terminal is connected to each first terminal of the transistor. 18. The semiconductor device according to claim 17, further comprising second capacitors C1A to C1N connected in parallel to said first resistors R1A to R1N. 19. A DC voltage drop during operation of each of the transistors is about 0.15 V or less, a resistance value of the first resistor is about 1 Ω or less, and a capacitance value of the second capacitor is about 5 pF or less. 16. The method according to claim 15, wherein
Alternatively, the semiconductor device according to claim 17. 20. The semiconductor device according to claim 15, wherein a sensor circuit forming a current mirror circuit is monolithically formed on a semiconductor substrate forming the semiconductor device. 21. A high-power amplifier comprising a plurality of transistors arranged in one or a plurality of blocks, each of which has the first capacitance and the second resistor. 17. The semiconductor device according to claim 15 or 16. 22. The semiconductor device according to claim 21, wherein a difference in heat radiation heat resistance between transistors in each of said blocks is smaller than a heat radiation heat resistance of said high power amplifier. 23. The ratio of the heat dissipation thermal resistance of the high-output amplifier to the deviation of the heat dissipation thermal resistance between the transistors in each of the blocks is different from the parallel resistance value of the plurality of first resistors connected in parallel for each block. 22. The semiconductor device according to claim 21, wherein the ratio is not more than about 1/2 of a ratio of a sum of two resistance values and a parallel resistance value of the first resistor.