JP4219433B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a field effect transistor (FET) and a heterojunction bipolar transistor (HBT) used at high frequencies.
[0002]
[Prior art]
In recent years, with the rapid development of mobile communication and satellite communication fields, high frequency devices from microwave band to millimeter wave band have been actively developed. In these devices, gain in a high frequency band is an important characteristic. In such a high frequency band, a field effect transistor (hereinafter referred to as FET) using gallium arsenide (GaAs), a heterojunction bipolar transistor (hereinafter referred to as HBT), or the like is used.
[0003]
The structure of the above device will be described by taking an FET as an example.
FIG. 4 is a structural diagram for explaining a conventional FET. In the conventional FET shown in FIG. 4, a channel layer 2 is formed on a substrate 1, a gate electrode 4 is formed on the channel layer 2, and a source electrode 3 and a drain electrode 5 are formed on both sides thereof. . Here, the distance between the source electrode 3 and the gate electrode 4 is 2 to 2.5 μm, the distance between the gate electrode 4 and the drain electrode 5 is 3 μm, and the width of the gate electrode 4 is 0.5 to 1 μm.
[0004]
In general, the gate-drain capacitance C _gd includes the gate-drain capacitance C _gd (int) caused by the depletion layer in the channel layer 2 and the gate-drain capacitance C _gd ( ext). The gate-drain capacitance C _gd (ext) is generated by electric lines of force between the gate electrode 4 and the drain electrode 5, as shown in FIG. In the example shown in FIG. 4, the gate-drain capacitance C _gd (ext) is approximately 0.1 pF per unit gate width.
[0005]
By the way, the maximum available power gain (G _amax ) at a certain frequency can be approximately expressed by the following equation.
G _amax = (g _m / 2πfC _gs ) ² · (1 / (K ₁ C _gd + K ₂ ))
here,
f: Frequency C _gs : Capacitance between gate and source C _gd : Capacitance between gate and drain g _m : Mutual conductance K ₁ and K ₂ : From the above equation, in order to increase the gain of the FET, the mutual conductance g _m It is necessary to increase or reduce the gate-source capacitance C _gs and the gate-drain capacitance C _gd .
[0006]
A conventional FET in which measures for improving the maximum available power gain (G _amax ) are taken will be described below with reference to FIGS. For the convenience of explanation, the following description will be given focusing on the reduction of the gate-drain capacitance C _gd .
FIG. 5 is a structural diagram of an FET showing an example in which the gate-drain capacitance C _gd is reduced by cutting off the electric lines of force shown in FIG. In the conventional FET shown in FIG. 5, a channel layer 12 is formed on a substrate 11, and a source electrode 13, a gate electrode 14, and a drain electrode 15 are formed on the channel layer 12. Further, the insulating film 16 is formed so as to cover the gate electrode 14. In this example, as shown in FIG. 5, since the source electrode 13 is formed and arranged so as to cover the gate electrode 14, the electric lines of force generated from the gate electrode 14 and the drain electrode 15 are respectively generated from the source electrode 13. Terminate at. Therefore, the gate electrode 14 and the drain electrode 15 are electrically separated from each other, and the gate-drain capacitance C _gd (ext) is ideally “0”. However, in the case of the structure shown in FIG. 5, the gate-source capacitance C _gs increases.
[0007]
Thus, an FET having a structure as shown in FIG. 6 has been proposed. FIG. 6 is an example proposed to compensate for the drawbacks of the FET shown in FIG. 5, and shows an example in which the gate-drain capacitance C _gd is reduced without increasing the gate-source capacitance C _ds. It is a structural diagram of FET. In the conventional FET shown in FIG. 6, a channel layer 22 is formed on a substrate 21, and a source electrode 23, a gate electrode 24 and a drain electrode 25 are formed on the channel layer 22. An insulating film 26 is formed, and a source electrode 27 is formed on the insulating film 26 and at an intermediate position between the gate electrode 24 and the drain electrode 25. As shown in FIG. 6, in this example, the lines of electric force generated from the gate electrode 24 and the drain electrode 25 respectively terminate at the source electrode 27 disposed at an intermediate position between the gate electrode 24 and the drain electrode 25. Therefore, the gate-drain capacitance C _gd can be reduced without increasing the gate-source capacitance C _gs , which is the capacitance between the gate electrode 24 and the source electrode 23.
[0008]
[Problems to be solved by the invention]
Incidentally, even with the FET having the structure shown in FIG. 6, the electric field blocking effect is not perfect. That is, as indicated by a broken line between the gate electrode 24 and the drain electrode 25 in FIG. 6, electric lines of force are generated between them, so that the gate-drain capacitance C _gd is not sufficiently reduced. ing. Therefore, a sufficient increase in FET gain cannot be obtained.
[0009]
An object of the present invention is to increase the gain of an FET by sufficiently reducing the gate-drain capacitance C _gd in view of the above problems.
[0010]
[Means for Solving the Problems]
The above-described problem is the first invention, the first electrode and the second electrode through which current flows in and out as an output signal, and the intermediate position between the first electrode and the second electrode, and the input signal In a semiconductor device in which a third electrode for controlling current is formed on one or different semiconductor layers, a shield electrode connected to the first electrode connected to a ground potential is provided above the second electrode. And a semiconductor device characterized in that it is formed in the same width as the second electrode and in a completely overlapping state ,
Solved by the semiconductor device according to the first invention, wherein an insulating film is formed between the shield electrode and the second electrode, which is the second invention,
According to a third aspect of the invention, the first electrode is a source electrode, the second electrode is a drain electrode, and the third electrode is a gate electrode. Solved by a semiconductor device according to any of the inventions,
According to a fourth aspect of the invention, the first electrode is an emitter electrode, the second electrode is a collector electrode, and the third electrode is a base electrode. This is solved by the semiconductor device according to any of the inventions.
[0011]
According to the semiconductor device of the present invention, the first electrode and the second electrode through which current flows in and out as the output signal, and the first current and the second electrode that are in the middle position between the first electrode and the second electrode are controlled by the input signal. A shield electrode connected to the first electrode connected to the ground potential is formed above the second electrode.
That is, since a shield electrode connected to the first electrode connected to the ground potential is formed on the second electrode, when a potential difference occurs between the second electrode and the third electrode, the second electrode The electric field lines from the third electrode to the third electrode, or conversely from the third electrode to the second electrode, are shielded by the shield electrode.
[0012]
Thereby, the capacity between the second electrode and the third electrode, that is, the input / output capacity can be greatly reduced. For example, when the second electrode is a drain electrode and the third electrode is a gate electrode, C _gd can be reduced. For this reason, the maximum available power gain can be improved. In addition, since the isolation characteristics between the input and the output can be improved, the stability of the element increases and the degree of freedom in circuit design increases.
[0013]
Further, the shielding effect can be further enhanced by setting the first electrode and the second electrode to have substantially the same width.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a structural sectional view for explaining a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a plan view thereof.
[0015]
In the FET shown in FIGS. 1 and 2, a channel layer 102 is formed on a substrate 101, and a source electrode (first electrode) 103 and a gate electrode (third electrode) 104 are sandwiched on the channel layer 102. A drain electrode (second electrode) 105 is formed. An insulating film 106 is formed so as to cover them, and a shield electrode 107 having the same width as that of the drain electrode 105 is formed on the insulating film 106 and at a position directly above the drain electrode 105.
[0016]
Here, the shield electrode 107 is connected to the source electrode 103, and both the source electrode 103 and the shield electrode 107 are connected to the ground potential.
The gate electrode 104 is connected to the signal input unit, and the drain electrode 105 is connected to the signal output unit. The drain electrode 105 is preferably made of AuGe / NiAu or AuGe / Au (<1 μ), and the shield electrode 107 is preferably made of Ti / Au or TiW / Au (<1 μ). The drain electrode 105 and the shield electrode 107 are preferably 10 μm in width and have the same structure.
[0017]
In this example, as shown in FIG. 1, the drain electrode 105 and the shield electrode 107 having the same width are vertically arranged, and the gap between the gate electrode 104 and the shield electrode 107 is, for example, the conventional FET shown in FIG. The electric lines of force generated at the gate electrode 104 are only slightly terminated at the shield electrode 107 and the drain electrode 105 because they are arranged so as to be separated from each other.
[0018]
That is, unlike the conventional FET shown in FIG. 6, there are no electric lines of force that occur at the gate electrode 24 and reach the drain electrode 25 beyond the source electrode 27. In the example of the FET shown in FIG. 1 of this embodiment, there is no electric line of force generated at the gate electrode 104 and reaching the drain electrode 105 beyond the shield electrode 107. The electric lines of force generated at the drain electrode 105 terminate at the shield electrode 107 disposed almost directly above.
[0019]
Therefore, it is possible to reduce the gate-source capacitance C _{gs so as} to be almost negligible, and to significantly reduce the gate-drain capacitance C _gd .
By reducing C _gd , the maximum available power gain can be improved. Furthermore, since the isolation between the input and the output can be improved, the stability of the element is increased and the degree of freedom in circuit design is increased.
[0020]
(Second Embodiment)
FIG. 3 is a structural diagram of an HBT according to the second embodiment of the present invention.
The HBT shown in FIG. 3 is made of a collector layer 202 made of i-GaAs or n-GaAs on a substrate 201 made of n ⁺ -GaAs, a base layer 213 made of p-GaAs, and n ⁺ -AlGaAs or InGaAs. The emitter layer 214 is sequentially laminated.
[0021]
An emitter electrode (first electrode) 212 is formed on the emitter layer 214, base electrodes (third electrodes) 207 and 208 are formed on the base layer 213, and a collector electrode (second electrode) is formed on the collector layer 202. Electrode) 205 and 206 are formed. Further, diffusion layers 203 and 204 are formed in the collector layer 202, and the diffusion layers 203 and 204 and the collector electrodes 205 and 206 are connected.
[0022]
An insulating film 211 is formed so as to cover them. On this pre-insulation 211, shield electrodes 209 and 210 having substantially the same width as the collector electrodes 205 and 206 are formed almost directly above the collector electrodes 205 and 206, respectively.
Here, the shield electrodes 209 and 210 and the emitter electrode 212 are both connected to the ground potential, the base electrodes 207 and 208 are connected to the signal input unit, and the collector electrodes 205 and 206 are connected to the signal output unit. The
[0023]
In this example, as shown in FIG. 3, since the shield electrode 209 and the collector electrode 205 having the same width, and the shield electrode 210 and the collector electrode 206 are arranged vertically, respectively, the base electrodes 207 and 208 are respectively A small amount of generated lines of electric force are only terminated at the shield electrodes 209 and 210.
That is, in the example of the HBT shown in FIG. 3 of the present embodiment, there are no electric lines of force that occur at the base electrodes 207 and 208 and reach the collector electrodes 205 and 206 beyond the shield electrodes 209 and 210. The electric lines of force generated at the collector electrodes 205 and 206 terminate at the shield electrodes 209 and 210 disposed almost directly above.
[0024]
Therefore, the base-emitter capacitance Cbe can be reduced to a negligible level, and the base-collector capacitance Cbc can be greatly reduced. For this reason, the maximum available power gain can be improved.
Furthermore, since the isolation between input and output can be improved by reducing Cbc, the stability of the element is increased and the degree of freedom in circuit design is increased.
[0025]
In the above embodiment, the present invention is applied to a junction type FET or a bipolar transistor, but it can also be applied to an insulated gate FET.
[0026]
【The invention's effect】
According to the semiconductor device of the present invention, the first electrode and the second electrode through which current flows in and out as the output signal, and the first current and the second electrode that are in the middle position between the first electrode and the second electrode are controlled by the input signal. A shield electrode connected to the first electrode connected to the ground potential is formed above the second electrode.
[0027]
Thereby, the capacity between the second electrode and the third electrode, that is, the input / output capacity can be greatly reduced. For this reason, the maximum available power gain can be improved, and the isolation characteristic between the input and output can be improved, so that the stability of the element increases and the degree of freedom in circuit design increases.
Further, the shielding effect can be further enhanced by making the first electrode and the second electrode substantially the same width.
[Brief description of the drawings]
FIG. 1 is a structural cross-sectional view of an FET according to a first embodiment of the present invention.
FIG. 2 is a plan view of an FET according to the first embodiment of the present invention.
FIG. 3 is a structural cross-sectional view of an HBT according to the first embodiment of the present invention.
FIG. 4 is a structural cross-sectional view of a conventional FET.
FIG. 5 is a structural cross-sectional view of a conventional FET.
FIG. 6 is a structural cross-sectional view of an FET according to a conventional example.
[Explanation of symbols]
101, 201 substrate,
102 channel layer,
103, 107 source electrode,
104 gate electrode,
105 drain electrode,
106 insulating film,
202 collector layer,
203, 204 diffusion layer,
205,206 Collector electrode,
207, 208 Base electrode,
209, 210 shield electrode,
211 insulating film,
212 emitter electrode;
213 base layer,
214 Emitter layer.

Claims (4)

A first electrode and a second electrode through which current flows in and out as an output signal, and a third electrode that is in an intermediate position between the first electrode and the second electrode and controls the current by an input signal Or in a semiconductor device formed on a different semiconductor layer,
The shield electrode connected to the first electrode connected to the ground potential is formed on the upper portion of the second electrode in the same width and completely overlapping with the second electrode. A semiconductor device.   The semiconductor device according to claim 1, wherein an insulating film is formed between the shield electrode and the second electrode. 3. The device according to claim 1, wherein the first electrode is a source electrode, the second electrode is a drain electrode, and the third electrode is a gate electrode. 4. Semiconductor device. The first electrode is the emitter electrode, the second electrode is a collector electrode, according to any one of claims 1 or 2, characterized in that said third electrode is a base electrode Semiconductor device.

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