JP2626209B2 - Wiring structure of field effect transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an element pattern of a semiconductor device used in microwaves and millimeter waves or a method of manufacturing the same.

(Prior Art) It is known that the noise figure of a semiconductor device generally used in the micro and millimeter wave ranges follows the following equation.

Here, F is the noise figure, Kf is the fitting constant, f is the operating frequency, Cgs is the gate-source capacitance, Rg is the gate resistance, Rs is the source resistance, and gm is the transconductance.
In recent years, low-noise devices in the microwave and millimeter-wave bands represented by 2DEGFETs generally require high gm,
Low Rs, low Rg, low Cgs, etc. are required. In recent years, methods for shortening the unit gate finger length have been studied by various research institutions for the purpose of lowering the Rg. In this method, in order to connect each gate finger, an air bridge technique is used for any one of the three terminals. At the lecture number C-625 of the Spring Institute of Electronics, Information and Communication Engineers, 1988, Ito et al. Increased the gate feed point to 6 points for a 2DEGFET with a total gate width of 300 μm and reduced the gate resistance to 12 GHz.
The characteristic of noise figure 0.49dB in z was shown. Yamane et al. Reported on page 13 of ED89-153 of IEICE Technical Report 1989 that MMICs using 2DEGFETs were reported. I have. According to this report, it is shown that the noise characteristic is improved as the number of feeding points is increased, but the parasitic capacitance at the gate lead-out electrode is also increased. From these reports, the effect of shortening the unit gate finger length on the noise characteristics can be confirmed. In these prototype reports, the connection of the increased gate lead-out points or the electrical connection of the source electrode is performed by using the air bridge technology for the fabrication of the device. As can be seen from this example, the air bridge technology is necessarily used for any one of the three terminals in order to connect each gate finger as the number of gate feeding points increases. If electrical conduction is achieved by using an interlayer insulating film instead of an air bridge, the capacity of the device is rather deteriorated, resulting in deterioration of device characteristics.

(Problems to be Solved by the Invention) As shown in the conventional example, the connection technology by the air bridge technology is indispensable for shortening the unit gate finger length intended to improve the noise characteristics of the element, that is, increasing the number of gate fingers. is there. There is no guideline in what pattern this air bridge is performed.

An object of the present invention is to provide a wiring structure of a field effect transistor having excellent high frequency characteristics represented by noise characteristics.

(Means for Solving the Problems) The element pattern according to the present invention is to eliminate as much as possible the reduction in parasitic capacitance due to the formation of air bridges due to the shortening of the unit gate finger length, and to improve the noise characteristics of the element. The wiring structure of the field effect transistor of the present invention has three terminals of a drain electrode, a gate electrode, and a source electrode,
In a field effect transistor in which the gate electrode is divided into two or more independent finger portions in a single element, the source electrode and the drain electrode sandwiched between the gate fingers are electrically connected to each other. The wiring metal of the drain electrode straddles over the source electrode in a portion other than on each of the gate finger electrodes and on the extraction electrode from the gate finger in order to obtain electrical conduction,
The drain electrode is electrically connected by an air bridge wiring without contacting the source electrode. Alternatively, in a field-effect transistor having three terminals of a drain electrode, a gate electrode, and a source electrode, wherein the gate electrode is divided into two or more independent finger portions in a single element, In order to electrically connect the source electrode and the drain electrode sandwiched between the respective gate fingers, the wiring metal of the source electrode is formed on portions other than on the respective gate finger electrodes and on the extraction electrodes from the gate fingers. The source electrode is electrically connected to the drain electrode by air bridge wiring without contacting the drain electrode.

(Operation) The purpose of the air bridge element pattern of the present invention is to shorten the unit gate finger length and increase the number of gate fingers, thereby reducing gate resistance and improving element characteristics such as noise characteristics. .
As the number of gate fingers increases, it is necessary to electrically connect one of the three terminals by an air bridge. However, in the present invention, the parasitic capacitance of the gate electrode is eliminated by disposing the air bridge electrode on the gate electrode. Not to increase. As in the present invention, either the drain electrode or the source electrode is formed on the air bridge at a position not above the gate electrode and not below the gate electrode so that no parasitic capacitance is generated.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In a pattern in which the number of gate fingers is set to eight and each is arranged in parallel with each other, in a portion other than the gate electrode 2 and the gate electrode pad, the drain electrode 1 is air-blown and the source electrode 3 is arranged below the drain electrode 1 (first pattern). 1 (a)), two types of patterns (FIG. 1 (a)) in which the source electrode 3 is air-blown and the drain electrode 1 is disposed below the source electrode 3 together with a generally used π-type pattern (FIG. 4) Formed on the same wafer. First
4A and 4B show a wiring structure of the present invention, and FIG. 4 shows a conventional structure, which are called a first pattern, a second pattern, and a π-type pattern, respectively. All three have a total gate width of 200 μm. As shown in FIG. 3, the wafer used was a MBE wafer having a modulation-doped structure using GaAs / AlGaAs as a material. The structure is such that a undoped GaAs layer 34 and a 15-nm thick undoped InGaAs layer 3 are formed on a semi-insulating GaAs substrate 35.
³ , an AlGaAs layer 32 with a thickness of 40 nm doped to 1.5 × 10 ¹⁸ cm ⁻³ ,
An 80 nm-thick GaAs layer 31 doped to 3 × 10 ¹⁸ cm ⁻³ is sequentially grown. A mesa is formed on the MBE wafer by using an etchant obtained by mixing sulfuric acid, a hydrogen peroxide solution, and water to separate elements. Next, the ohmic electrode is AuGu / Ni / Au
And then a high-temperature heat treatment alloy at about 450 ° C. Next, a gate pattern is formed of a photoresist, and a recess is formed while measuring the ohmic current. The etchant used in the formation of the mesa can be used for the etching. When a desired ohmic current is obtained, a gate electrode is formed by vapor deposition lift-off of a gate metal. Examples of the gate metal include Ti / Al, Ti / Pt / Au, and Al. In the case of a low-noise element, a method using electron beam exposure is considered to be effective in order to reduce the Cgs in order to reduce the gate length as much as possible. In this case, a gate length of 0.2 μm has been achieved by this electron beam exposure.

Thereafter, the first pattern and the second pattern enter an air bridging process with the intention of electrically connecting the divided electrodes. FIG. 2 shows a manufacturing process diagram relating to a first pattern in which a drain electrode and a drain electrode pad are air-bridged wiring over a source electrode. First, a drain electrode 41, a source electrode 40, and a drain electrode pad 42 are formed (FIG. 2 (a)), and an opening is formed on each electrode pad with a photoresist 43 (FIG. 2 (b)). A metal film 44 of Pt is deposited (FIG. 2C). Subsequently, the bridge portion of the electrode to be air-bridged is opened with a photoresist 45 (FIG. 2 (d)), and Au plating (plating) 46 is performed (FIG. 2 (e)). This thickness is about 2-3 μm. At this time, patterning such that Au plating is always applied to each electrode pad portion. Next, the upper photoresist used at the time of Au plating is removed by, for example, a method such as oxygen plasma treatment (FIG. 2 (f)). When the surface of the metal film is exposed, the metal film is removed by ion milling using, for example, Ar gas 47 using the Au-plated portion as a mask (FIG. 2 (g)). After ion milling, the lower photoresist is completely removed by, for example, a method such as oxygen plasma treatment (FIG. 2 (h)).
Thus, the fabrication of the device is completed. The second pattern and the π-type pattern are also manufactured in a similar process procedure.

The pattern did not show any dependence on the DC characteristics for each device pattern sample produced by this method. However, when the noise characteristics of each sample at 12 GHz were evaluated, a clear element pattern dependence was observed as shown in FIG. That is, the first putter and the second pattern are significantly lower than the noise figure of the π-type pattern, and are higher in terms of incidental gain. In general, the gate resistance is determined, for example, by the American Telephone and Telegraph Company, 1979, The Bell System Technical Journal.
ram Company the Bell System Technical Journal) No. 5
As shown by Fukui in Vol. 8, No. 3, page 791, the following formula can be used.

Where Rg is the gate resistance, ρg is the resistivity of the gate metal,
z indicates a unit gate finger length, Sg indicates a gate cross-sectional area, and Z indicates a total gate width. In this series of air bridge patterns, the gate finger length is half and the number of fingers is twice that of the π type, so that the gate resistance is 1/4 according to the above equation. The improvement of the noise characteristics in the first pattern and the second pattern as shown in FIG. 5 could be explained by simple estimation using Fukui's equation. The capacitance between the source electrode and the drain electrode did not significantly affect the noise characteristics and the gain characteristics.

From the above results, no other electrode is located above or below the gate electrode as in the case of the first and second patterns, and other electrodes than the gate electrode do not cause an increase in gate parasitic capacitance. In the element where the wiring metal of the source electrode straddles the drain electrode at the point of, or the wiring metal of the drain electrode straddles the source electrode, the improvement of the noise characteristic and the gain characteristic of the element which is air-bridged is π-type. It was confirmed that the pattern was compared with the pattern.

(Effects of the Invention) As described above, in the element pattern using the air bridge technology required by increasing the gate power supply point and shortening the gate finger length, a portion other than the gate electrode is provided so as not to increase the gate parasitic capacitance. With the wiring metal of the source electrode straddling the drain electrode, or the wiring metal of the drain electrode straddling the source electrode, the air-bridge wiring element improves the high-frequency characteristics represented by the noise characteristics without lowering the gain Can be done.

[Brief description of the drawings]

1 (a) and 1 (b) are diagrams showing an FET element pattern according to an embodiment of the present invention. FIG. 2 is a diagram for explaining a manufacturing process using the air bridge technology according to the embodiment of the present invention. FIG. 3 is a structural view of a semiconductor wafer used for manufacturing in this embodiment. FIG. 4 is a view showing a conventional general-purpose π-type pattern. FIG. 5 is a diagram showing evaluation results of noise characteristics of each element pattern sample at 12 GHz. DESCRIPTION OF SYMBOLS 1 ... Drain electrode 2 ... Gate electrode 3 ... Source electrode 4 ... Air bridge part 31 ... n ⁺ -GaAs layer 32 ... n ⁺ -AlGaAs layer 33 ... i-InGaAs layer 34 ... i-GaAs layer 35 ... Semi-insulating GaAs substrate 40 ... Source electrode 41 ... Drain electrode 42 ... Drain electrode pad 43 ... Photoresist 44 ... Metal film 45 ... Photoresist 46 ... Gold plating 47 ... Ar ⁺ ion

Claims (2)

(57) [Claims] 1. A field effect transistor having three terminals of a drain electrode, a gate electrode and a source electrode, wherein the gate electrode is divided into two or more independent finger portions in a single device. The source electrode and the drain electrode sandwiched between the respective gate fingers to electrically connect the drain electrode to the source electrode and the drain electrode at portions other than on the respective gate finger electrodes and other than on the extraction electrode from the gate finger. The wiring metal of (1) straddles at least a part of the source electrode, and electrically connects the drain electrode by an air bridge wiring without contacting the source electrode. 2. A field effect transistor having three terminals of a drain electrode, a gate electrode, and a source electrode, wherein the gate electrode is divided into two or more independent finger portions in a quasi-element, and The source electrode and the drain electrode sandwiched between the gate fingers in order to establish electrical continuity with the source electrode and the drain electrode, respectively. Wherein the wiring metal crosses at least a part of the drain electrode, and the source electrode is electrically connected by an air bridge wiring without contacting the drain electrode.