JPS62273755A - Field-effect transistor and manufacture of the same - Google Patents

Abstract

PURPOSE:To reduce a large parasitic capacitance and obtain a field-effect transistor with excellent radio frequency characteristics by a method wherein a gate electrode is formed on a semiconductor channel layer or on an insulating film formed on the channel and a wiring floated spatially above the upper surface of the gate electrode is formed and an external lead wiring is composed of the floated wiring. CONSTITUTION:A thick photoresist pattern 11 in which an aperture is made at a gate pad part is formed and baked at a high temperature to be fluidized and its surface is made to be flat. Then the photoresist 11 is etched by dry etching with 02 and the top surface of a gate is exposed and, further, metal 12, which is used as a gate lead wiring, a foundation layer of the pad and also as a wiring forplating, for instance TiPt, is evaporated. Then, a photoresist pattern 13 which has apertures at the gate lead part and at the pad for plating is formed and an Au plating layer 14 is formed. Finally, the photoresist 13 for plating is removed and the foundation metal layer 12 is etched with the Au plating layer 14 as a mask and, further, the lower photoresist layer 11 is removed to complete the device.

Description

DETAILED DESCRIPTION OF THE INVENTION Detailed Description of the Invention (Field of Industrial Application) The present invention particularly relates to a field effect transistor for use in an ultra-high frequency band and a method for manufacturing the same.

(Prior Art) In recent years, demands for higher frequency operation and higher performance of transistors have been increasing. InP field effect transistor (
FET) especially insulation game) FET (MISFET) is
It has high electron velocity and high gate breakdown voltage, and is expected to be a new FET that can meet these demands.

Its general structure is shown in the perspective view of FIG. 3, in which a channel layer 2 is provided on a high-resistance substrate 1, a gate electrode 4 is formed via a gate insulating film 3, and source electrodes 5, A drain electrode 6 is formed. The gate is led out from the device operating area by a wiring 8 and connected to a bonding pad 7. Further, the cross-sectional structure of the gate electrode in the drawing direction is as shown in FIG.

(Problems to be Solved by the Invention) The surface potential of InP is small, and therefore, especially when a positive voltage is applied to the 4-electrode, as shown by e in the cross section of the device in FIG. An electronic layer is also induced under the gate lead-out portion 8 and the gate pad 7. therefore,
Large area pads create extremely large parasitic capacitances and
It has the disadvantage of greatly impairing high frequency characteristics.

The present invention provides a field effect transistor that reduces the large parasitic capacitance in the prior art as described above and has excellent high frequency characteristics, and a method for manufacturing the same.

(Means for Solving the Problem) According to the present invention, a wiring (air bridge) that is spatially suspended from the upper surface of a gate electrode formed on a semiconductor channel layer or an insulating film formed on a channel. As a result, a field effect transistor characterized in that an external lead wiring is formed is obtained.

Further, according to the present invention, after a gate electrode is formed on a semiconductor channel layer or a gate insulating film formed on a channel, a fluid resin is applied, the surface is flattened, and the resin layer is etched by gas etching. There is obtained a method for manufacturing a field effect transistor characterized in that the upper surface of the gate electrode is exposed and an external lead wiring section is formed by connecting to the exposed upper surface of the gate electrode.

(Function) FIG. 1 is a perspective view of a transistor chip showing an example of a high frequency field effect transistor according to the present invention. A lead-out portion 8 extending from the upper surface of the gate to a gate pad 7 formed on the semi-insulating substrate 1 via an insulating film 3 is formed by an air bridge. As can be seen from the figure, the main body of the gate electrode 4 and the gate wiring parts other than the gate pad 7 are all floating in space, so there is almost no charge induced in the channel or substrate as in the conventional example, and the parasitic capacitance is reduced. becomes extremely small. This effect becomes greater as the gate electrode is formed higher, since the gate lead-out portion is further away from the substrate surface, and as will be described later, manufacturing becomes easier. Furthermore, in the conventional example, it is necessary to have a plurality of source electrodes.When wiring the gate lead-out part and the source by crossing over using a normal air bridge or insulating film, the gate lead-out part is connected to the channel l In contrast, in the present invention, as is clear from FIG. 5. Both can be made into extremely simple shapes and arrangements. This further increases parasitic capacitance and parasitic resistance (
Source resistance can be reduced. Furthermore, the fact that there is no restriction on where the external wiring of the gate can be drawn out further enhances the above effect.

(Example) The method for manufacturing a field effect transistor of the present invention will be described below with reference to Examples. FIG. 2 is a cross-sectional view of an element showing steps in one example of the manufacturing method of the present invention.
P channel layer 2 top 2 top VD SiO2 gate insulating film 3
For example, the gate electrode 4 is formed to have a thickness of 500 mm.
(Fig. 2(a)). In this case, for example, Au
/WSi T-type gate is shown. Subsequently, using this T-shaped gate as a mask, source 5 and drain 6 ohm electrodes are formed using self-aligned lines. Furthermore, 5A
is a metal layer deposited on the gate electrode (FIG. 2(b)). Next, a thick photoresist pattern 11 is formed that opens the gate pad area, and is baked at high temperature to fluidize the photoresist and flatten the surface (Fig. 2(C)).
). Next, the photoresist 11 is etched by dry etching in step 02 to expose the upper surface of the gate, and a metal 12, for example, TiPT, which also serves as the lower layer of the gate lead-out wiring and pad and the plating wiring is vapor-deposited on the entire surface (
Figure 2(d).

Next, a photoresist pattern 13 for opening gate lead-out portions and pads is formed for plating, and the Au plating layer 1 is formed.
4 (FIG. 2(e)).Finally, the plating photoresist 13 is removed, the base metal layer 12 is etched using the Au plating layer as a mask, and the lower photoresist layer 11 is etched.
The device is completed by removing (FIG. 2(f)). Note that although the gate lead-out portion and the gate pad are formed at the same time in the above description, the gate pad may be formed in advance.

Moreover, any commonly used method can be applied to the gate, source, and drain electrodes, and is not limited to this method. The method for forming the gate lead-out portion is similar and need not be limited to the plating method. As can be seen from the above description, according to this manufacturing method, as long as the upper surface of the gate is high, the wiring can be easily drawn out from any gate electrode using an air bridge.

(Effects of the Invention) As described above, according to the present invention, a high-performance, ultra-high frequency field effect transistor with reduced parasitic factors, particularly small parasitic capacitance, can be realized, and can be mass-produced by a simple method. Note that although the case of InP as the semiconductor has been explained above, GaA
It is clear that the present invention can also be applied to other semiconductors such as S.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing an example of a field effect transistor of the present invention, FIGS.
The cross-sectional view of FIG. 4 is a diagram illustrating a conventional field effect transistor. Here, 1: high resistance substrate, 2: channel layer, 3: insulating film 4: gate, 5: source, 6: drain 7: gate pad, 8:
Gate drawer, 11 and 13: Photoresist, 12:
Wiring base layer 14: Au plating layer. Figure 1 5 1: Collection I: Naya Furunoso Figure 2 (a) (C) Engraving of the drawing (no change in content) Figure 2 (d) (e) Figure 3 Figure 4 Procedure amendment Type (method) % formula % 1. Indication of incident 1985 Patent application No. 1177
No. 75 No. 2, Name of the invention Field-effect transistor and its manufacturing method 3, Relationship to the amended case Applicant 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative Tadahiro Sekimoto 4; Agent 6, Drawing subject to amendment 7, Contents of amendment

Claims (1)

[Claims] 1) From the upper surface of the gate electrode formed on the semiconductor channel layer or the gate insulating film formed on the channel,
A field effect transistor characterized in that external lead wiring is formed by spatially floating wiring (air bridge). 2) After forming a gate electrode on the semiconductor channel layer or the gate insulating film formed on the channel, apply a fluid resin to flatten the surface, and then etch the resin layer using gas etching to form the gate electrode. 1. A method for manufacturing a field effect transistor, comprising exposing the upper surface and forming an external lead wiring section by connecting to the exposed upper surface of the gate electrode.