JPS60167471A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive the increase in integration and speed by a method wherein source and drain regions have a high concentration part and a low concentration part, the latter of which parts is positioned under an insulation film formed on the side surface of a polycrystalline Si gate, and most parts of this insulation film and the high concentration part and a metallic electrode come into contact with each other. CONSTITUTION:The source-drain electrode 211 is in contact with a gate poly Si side surface oxide film 207 and a field oxide film region 202. This enables the reduction in source-drain area without the need of contact margins. Thereby, the speed and the integration can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a silicon gate semiconductor device whose gate is formed of polycrystalline silicon.

[Prior art]

Recently, there is a strong demand for lower power consumption and higher integration in semiconductor devices, and as a result, miniaturization of transistors has become more and more active.

In order to meet such requirements, a device as shown in FIG. 1 is used. To explain this along with its manufacturing process, first, an oxide film 102 is formed on the entire surface of the first conductive type conductor substrate 101 by selective oxidation technology, and a portion thereof is buried in the substrate.
t-selectively formed (FIG. 1(a)). Next, a gate oxide film 103 and polysilicon 104t are sequentially formed, leaving a portion of the polysilicon 104 to be used as a gate, and removing the other portions. A second conductivity type impurity is introduced into the source and drain regions 105 by, for example, ion implantation.
An oxide film 106' is formed on the top and side surfaces of the gate polysilicon 104 (FIG. 1(-).Next, a ringer 2s 107t- is formed (FIG. 1(C)).
9x107K contact hole t14ff source.

A drain aluminum electrode 108 is formed (FIG. 1(d)).

In such a conventional manufacturing method, in order to open a contact hole in the phosphor glass 107, the oxidation layer 11 in the field region is
1 [Between 102 and the contact hole and between the side oxide film 106 of the gate polysilicon 104 and the contact hole,
A margin that takes into account misalignment is required, and as a result,
If the source/drain area is large, problems arise such as a decrease in the degree of integration and a decrease in speed due to an increase in parasitic capacitance.

[Purpose of the invention]

An object of the present invention is to provide a conductor device having a structure suitable for high integration and high speed, and a method for manufacturing the same.

[Structure of the invention]

In the present invention, the source and drain regions have a high concentration portion, a low concentration portion, and tvLl. Characterized by the fact that most of the metal electrode is in contact with the metal electrode.

Furthermore, the present invention provides a polycrystalline silicon gate (low concentration source and drain regions #JR' are formed on a mask, an insulating film is formed on the side surface of the polycrystalline silicon gate, and this is used as a mask to form a high f.
Form source and drain regions.

The method is characterized in that a metal gate is formed in contact with the high S degree part and the insulating film on the side surface of the gate.

In other words, the present invention achieves high integration and high speed by bringing the highly doped source and drain regions into contact with the metal electrode in a self-aligned manner.

[Example]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Figure 82 shows a manufacturing method according to one embodiment of the present invention. First, an oxide film 202 partially buried in the substrate 201 is selectively formed on the entire surface of a g-conducting semiconductor (silicon) substrate 201 to a thickness of t-8000 to 1000 mm using selective oxidation technique IIu. (Figure 2(a)).

Next, the gate oxide film 203 is made to have a thickness of 400 to 600 t.

Polysilicon layer 204 t-4000 to 8000 thick.

A silicon oxide film 2 (l i - is formed 111 times to a thickness of about 500 to 500A (FIG. 2(b)).Other parts are formed so that the oxide film 205 remains on the polysilicon layer in the part to be used as a gate. oxide film 205 is removed.

Subsequently, the remaining common sense film 205t is selectively removed as a mask (FIG. 2(C)).
.

This forms a silicon gate pattern.

Next, a second conductive wall impurity is introduced at a low concentration by ion implantation to form a low concentration source and drain region 206 (
Figure 82(d)). After co, soo.

5- ~8000 thickness (DCVD silicon: xy oxidation 11 [207
Cover the whole surface (Fig. 2(e)). Anisotropic etching is performed to remove the oxide 11203 remaining between the oxide film 207 and the gate polysilicon 204, and further remove the oxide 11203 on the drain region 206 with a low S degree. Gate polycricon gI
In the region from the i-plane oxidation $207 to the field oxide film region 202, a second conductivity type impurity is introduced at a higher concentration and deeper than the low II 1 degree drain region 206 to form a high concentration drain region 208. Figure 2 (f))
. Due to the presence of the gate polysilicon side oxide film 207,
The end portions of the source and drain regions on the channel side form a low a degree region 1206. Next, 8oo of Arunnik A209.

A photoresist 210 is applied to a thickness of about 1 μm. In this case, the shape of the aluminum layer 209 is undulating, and the gate polysilicon layer 209 is undulating.
4. The resist at the top is thinner than other parts (Fig. 2 (g)). By dry etching, the resist on the upper part of the gate voltage is removed, and the resist on other parts is removed.
210 will remain (#I2 figure (h)). After that, the aluminum on the top of the 1-gate polysilicon 204 is removed by dry etching, and the resist 210t is removed to form a source.
A drain electrode 211t is formed (FIG. 2(i)).

In the device formed by the above manufacturing method, the source.

The drain electrode 211 has a round shape that contacts the gate polysilicon side oxide film 207 and the field oxide film region 202.
It is possible to reduce the drain area without requiring the above-mentioned contact margin. This rounding has advantages as a manufacturing method for high speed and high integration.

It is a matter of course that the present invention can be applied to other silicon gate MO8 devices such as complementary 11MO8 and E/DMO8. The conductivity Wt of each region can be replaced, and the dimensions and materials are not limited to those shown in the practical example.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) show cross-sectional views of the conventional manufacturing process. 101...-th conductivity type medium conductor substrate, 102...
... Oxide film, 103 ... Oxide film, 104.
... No. 1 - Conductive Pear Polysilicon, 105...
・Second conductive impurity distribution, 106...Oxide film,
107...Lingarasu. 108... Aluminum electrode. FIG. 2 (!I) to (ri) show cross-sectional views of embodiments of the present invention. 201... First conductivity type semiconductor substrate, 202...
... Oxide film, 203 ... Oxide film, 204.
...No. 1 conductive polysilicon, 205...
- Oxide film, 206... Second conductive impurity low concentration region, 207... Oxide film. 208...Second conductive impurity high fIk degree region,
209...aluminum, 210...
(Register), 211... Source, drain electrode. Cow 2 hair ■ (ku) Mine 2 times (to 2

Claims (2)

[Claims] (1) In a semiconductor device whose gate is made of polycrystalline silicon, the source and drain regions each have a low concentration part and a high 111 degree part, and the low concentration part is formed on the side surface of the polycrystalline silicon and is formed under an insulating film. t- A semiconductor device characterized in that the insulating film and most of the high-performance portion are in contact with a metal electrode. (2) A step of forming a field insulating film and a gate insulating film on one main surface of the semiconductor substrate, a step of selectively forming polycrystalline silicon on the gate insulating film, and a step of selectively forming the polycrystalline silicon gate and the pongee. forming low concentration source and drain regions in the semiconductor substrate using the field insulating film as a mask;
a step of covering with an insulating film, a step of forming highly doped source and drain regions using this insulating film and the field insulating film as a mask, and a step of forming highly doped source and drain regions and an insulating film on the sides of the polycrystalline silicon gate. A method for manufacturing a semiconductor device, comprising: forming a metal electrode in contact with a film;