JPH04162729A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To shorten the length of bonding wirings for connecting a gate electrode, a drain electrode to an external terminal, and to reduce its inductance by providing a conductor layer provided on a surface lower than the gate electrode, side face and rear surface of a semiconductor chip and electrically connected to a source electrode on the outer periphery of an element forming region. CONSTITUTION:A gate electrode 2, a source electrode 1, a drain electrode 3 are provided on an element forming region of a semiconductor chip 4, a metallized layer 1a is provided on the outer periphery of the forming region including a step formed by partly etching the chip 4, the side face and the rear surface of the chip 4, and electrically connected to a source electrode 1. The layer 1a formed on the outer periphery of the forming region is formed lower by one stage than a flat surface including the electrodes 2, 3. Accordingly, a bonding wiring for connecting the electrode 2 or 3 to an external terminal is not connected to the layer 1a. Thus, the length of the bonding wiring for connecting the electrode 2 or 3 to the terminal is shortened, and its inductance is reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to field effect transistors.

[Conventional technology]

A conventional field effect transistor is shown in FIG. 2(a).

As shown in (b), strip-shaped gates t[, 2 are arranged and connected to each other in the element formation region of the semiconductor chip 4, and comb-shaped source electrodes are arranged to face each other with the gate electrode 2 in between. 1 and a drain electrode 3 are provided, and a metallized layer 1a is provided around the element formation region and on the side and back surfaces of the semiconductor chip 4.
is provided and electrically connected to the source electrode 1, and has a configuration in which the source electrode 1 is installed when it is mounted on a package.

[Problem to be solved by the invention]

In the conventional field effect transistor described above, the gate electrode and drain electrode provided in the element formation region and the surrounding metallized layer are formed in the same plane, but in high frequency elements, the gate electrode and drain electrode and the external terminal are formed in the same plane. The connecting bonding wire acts as an inductance, and to reduce the inductance, the length of the bonding wire must be shortened.

However, when the length of the bonding line is shortened, there is a point where the bonding line and the surrounding metallized layer come into contact, causing a short circuit between the gate electrode or the drain electrode and the source electrode.

[Means to solve the problem]

A field effect transistor of the present invention includes a gate electrode provided in an element formation region of a semiconductor chip, and a source electrode and a drain electrode provided opposite to each other with the gate electrode in between. A conductor layer is provided on the outer periphery of the semiconductor chip and is provided on a surface lower than the gate electrode and on the side and back surfaces of the semiconductor chip and electrically connected to the source electrode.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of the present invention.

As shown in FIG. 1, as in the conventional example, a gate electrode 2. Source electrode 1. Drain electrodes 3 are respectively provided, and a metallized layer 1a is provided on the outer periphery of the element forming region including a stepped portion formed by partially etching the surface of the semiconductor chip 4 and the inner and rear surfaces of the semiconductor chip 4. connected.

Here, the metallized layer 1a provided on the outer periphery of the element forming region
is formed one step lower than the plane containing the gate electrode 2 and the drain electrode 3, and the gate electrode 2 or the train electrode 3
The bonding wire connecting the external terminal to the metallized layer 1a
can be prevented from coming into contact with.

〔Effect of the invention〕

As explained above, the present invention reduces the length of the bonding line connecting the gate electrode or drain electrode and the external terminal by making the metallized layer provided on the outer periphery of the element forming region lower than the position of the gate electrode or drain electrode. By shortening the length, the inductance can be reduced, and the high frequency characteristics of the field effect transistor can be improved.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention, and FIGS. 2(a) and 2(b) are a plan view and a sectional view taken along the line A-A′ of an example of a conventional field effect transistor. . 1... Source electrode, 1a... Metallized layer, 2...
- Gate electrode, 3...Drain electrode, 4...Semiconductor chip.

Claims (1)

[Claims] A gate electrode provided in an element formation region of a semiconductor chip;
In a field effect transistor having a source electrode and a drain electrode provided opposite to each other with the gate electrode in between, the field effect transistor is provided on a surface lower than the gate electrode at the outer periphery of the element formation region and on a side surface and a back surface of the semiconductor chip. A field effect transistor further comprising a conductor layer electrically connected to the source electrode.