JPH05291478A - Plastic sealed semiconductor device - Google Patents

Plastic sealed semiconductor device

Info

Publication number
JPH05291478A
JPH05291478A JP4121359A JP12135992A JPH05291478A JP H05291478 A JPH05291478 A JP H05291478A JP 4121359 A JP4121359 A JP 4121359A JP 12135992 A JP12135992 A JP 12135992A JP H05291478 A JPH05291478 A JP H05291478A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor element
resin layer
grounding
outside
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4121359A
Other languages
Japanese (ja)
Inventor
Minoru Kikuchi
稔 菊池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4121359A priority Critical patent/JPH05291478A/en
Publication of JPH05291478A publication Critical patent/JPH05291478A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the number of grounding terminals by forming at least two grounding terminals of inner leads on a surface of a semiconductor element, which is used for the formation of a circuit, in a plastic sealed semiconductor device that has a plurality of inner leads extending to the outside from the inside of an encapsulating resin. CONSTITUTION:A plastic sealed semiconductor device has a plurality of inner leads 3 extending from the inside of an encapsulating resin layer 1 to the outside and used for leading out an external electrode. An external lead 4 is integrated with each inner lead 3, and extends from the exterior of the resin layer 1. In such a semiconductor device, grounding terminals 5 are formed to lie across a surface of a semiconductor element 2 used for the formation of a circuit between two out of four sides in the vicinity of electrodes of this surface. The electrodes of the element 2 are electrically connected to inner lead bonds by metal fine lines 6. This makes it possible to connect a grounding electrode of the element 2 with the grounding terminal 5 at an arbitrary location by means of the metal fine line 6, whereby the freedom of connection of signal lines is improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、樹脂封止型半導体装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device.

【０００２】[0002]

【従来の技術】図５は、従来の樹脂封止型半導体装置を
示す平面図、図６は、図５のＣ−Ｃ′線断面図である。2. Description of the Related Art FIG. 5 is a plan view showing a conventional resin-sealed semiconductor device, and FIG. 6 is a sectional view taken along the line CC 'of FIG.

【０００３】図において、１は仮想線で示す封止樹脂
層、２は半導体素子、３は樹脂層１内部から外部へ延在
する内部リード、４は内部リード３に一体に形成され樹
脂層１外部から延在する外部リード、１０は半導体素子
２がＡｇペースト等の接着剤１１を介して固着される半
導体素子搭載部、６は半導体素子２の電極部と内部リー
ドボンディング部とを電気的に接続する金属細線であ
る。In the drawing, 1 is a sealing resin layer indicated by phantom lines, 2 is a semiconductor element, 3 is an internal lead extending from the inside to the outside of the resin layer 1, and 4 is a resin layer formed integrally with the internal lead 3. External leads extending from the outside, 10 are semiconductor element mounting portions to which the semiconductor element 2 is fixed via an adhesive 11 such as Ag paste, and 6 electrically connect the electrode portion of the semiconductor element 2 and the internal lead bonding portion. It is a thin metal wire to be connected.

【０００４】[0004]

【発明が解決しようとする課題】上述した従来の樹脂封
止型半導体装置は、半導体素子に多大な電流を流す際、
多数本の電源端子，接地端子を設けることによって、電
源，接地の電位の変動に対応していたため、信号線を増
やす場合、一定の数の端子を電源，接地端子に割り当て
なければならなかった。The above-mentioned conventional resin-encapsulated semiconductor device has the following problems when a large amount of current is applied to a semiconductor element.
Since a large number of power supply terminals and ground terminals are provided to cope with fluctuations in the potential of the power supply and ground, a certain number of terminals must be assigned to the power supply and ground terminals when increasing the number of signal lines.

【０００５】特に、２００ピンを超えるゲートアレイに
ついては顕著であり、電源，接地端子数が合計で数十本
となり、信号線の接続をすることが困難となりつつある
という問題点を有していた。In particular, the gate array having more than 200 pins is remarkable, and the total number of power supply terminals and ground terminals is several tens, which makes it difficult to connect the signal lines. ..

【０００６】本発明の目的は、信号配線の接続の自由度
を増すようにした樹脂封止型半導体装置を提供すること
にある。An object of the present invention is to provide a resin-encapsulated semiconductor device in which the degree of freedom in connecting signal wiring is increased.

【０００７】[0007]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る樹脂封止型半導体装置は、封止樹脂層
内部から外部へ延在する外部電極取出用の複数の内部リ
ードを有する樹脂封止型半導体装置であって、内部リー
ドのうち少なくとも２本の接地用端子を半導体素子の回
路形成面上に配置し、かつ電気絶縁性接着層により半導
体素子の回路形成面上に固着したものである。To achieve the above object, a resin-encapsulated semiconductor device according to the present invention has a plurality of internal leads for extracting external electrodes which extend from the inside of the encapsulating resin layer to the outside. In a resin-sealed semiconductor device, at least two grounding terminals of internal leads are arranged on a circuit forming surface of a semiconductor element, and fixed on the circuit forming surface of a semiconductor element by an electrically insulating adhesive layer. It is a thing.

【０００８】また、前記電気絶縁性接着層は、ポリイミ
ドフィルムの両面に電気絶縁性接着剤を設けた構造のも
のである。The electrically insulating adhesive layer has a structure in which an electrically insulating adhesive is provided on both surfaces of a polyimide film.

【０００９】[0009]

【作用】接地端子を半導体素子の回路形成面上に形成
し、接地端子の本数を減らし、信号配線の接続の自由度
を増す。The ground terminal is formed on the circuit formation surface of the semiconductor element, the number of ground terminals is reduced, and the degree of freedom in connecting signal wiring is increased.

【００１０】[0010]

【実施例】次に、本発明について図面を用いて説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【００１１】（実施例１）図１は、本発明の実施例１を
示す平面図、図２は、図１のＡ−Ａ′線断面図である。(Embodiment 1) FIG. 1 is a plan view showing Embodiment 1 of the present invention, and FIG. 2 is a sectional view taken along the line AA 'in FIG.

【００１２】図において、１は仮想線で示す封止樹脂
層、２は半導体素子、３は樹脂層１内部から外部へ延在
する内部リード、４は内部リード３と一体に形成され樹
脂層１の外部から延在する外部リード、５は半導体素子
２の回路構成面の電極部の近傍の４辺の内の２辺を横断
する接地端子、６は半導体素子２の電極部と内部リード
ボンディング部とを電気的に接続する金属細線である。In the drawing, 1 is a sealing resin layer indicated by imaginary lines, 2 is a semiconductor element, 3 is an internal lead extending from the inside to the outside of the resin layer 1, and 4 is a resin layer 1 formed integrally with the internal lead 3. External leads extending from the outside, 5 is a ground terminal that crosses two of the four sides near the electrode portion of the circuit configuration surface of the semiconductor element 2, and 6 is an electrode portion of the semiconductor element 2 and an internal lead bonding portion. It is a thin metal wire that electrically connects with.

【００１３】本実施例において、接地端子５は、半導体
素子２の回路形成面上に固着されている。その固着方法
としては、両面絶縁性接着剤８を有するポリイミドフィ
ルム等の絶縁フィルム７を介して行われる。In this embodiment, the ground terminal 5 is fixed on the circuit forming surface of the semiconductor element 2. The fixing method is performed through an insulating film 7 such as a polyimide film having a double-sided insulating adhesive 8.

【００１４】このような構造であれば、接地端子５が半
導体素子２の電極部の近傍を横断しているので、半導体
素子２の接地用電極を接地端子５に任意の位置で金属細
線６にて接続できる。With such a structure, the grounding terminal 5 crosses the vicinity of the electrode portion of the semiconductor element 2, so that the grounding electrode of the semiconductor element 2 is connected to the grounding terminal 5 at the metal thin wire 6 at an arbitrary position. Can be connected.

【００１５】本実施例では、接地電極端子が４本で、ペ
レット側は、何本でも接地用電極と接続することが可能
となるため、電源接地線の耐ノイズ性は、従来と同等
で、信号配線の接続の自由度が増すという効果を有す
る。In this embodiment, since the number of ground electrode terminals is four, and the pellet side can be connected to any number of ground electrodes, the noise resistance of the power ground line is equivalent to that of the conventional one. This has the effect of increasing the degree of freedom in connecting the signal wiring.

【００１６】（実施例２）図３は、本発明の実施例２を
示す平面図、図４は、図３のＢ−Ｂ′線断面図である。(Embodiment 2) FIG. 3 is a plan view showing Embodiment 2 of the present invention, and FIG. 4 is a sectional view taken along the line BB 'in FIG.

【００１７】図において、１は仮想線で示す封止樹脂
層、２は半導体素子、３は樹脂層１内部から外部へ延在
する内部リード、４は内部リード３と一体に形成され樹
脂層１の外部から延在する外部リード、５は半導体素子
２の回路構成面の電極部の近傍の４辺の内の２辺を横断
する接地端子、６は半導体素子２の電極部と内部リード
ボンディング部とを電気的に接続する金属細線である。In the drawing, 1 is a sealing resin layer indicated by phantom lines, 2 is a semiconductor element, 3 is an internal lead extending from the inside to the outside of the resin layer 1, and 4 is a resin layer formed integrally with the internal lead 3. An external lead extending from the outside of the semiconductor element 2, a ground terminal traversing two of the four sides near the electrode portion of the circuit configuration surface of the semiconductor element 2, and 6 an electrode portion of the semiconductor element 2 and an internal lead bonding portion. It is a thin metal wire that electrically connects with.

【００１８】本実施例において、接地端子５は、半導体
素子２の回路形成面上に固着されている。その固着方法
としては、接地端子が横断している回路形成面の接地電
極部以外では両面絶縁性接着剤８を有するポリイミドフ
ィルム等の絶縁フィルム７を介して行い、接地端子が横
断している回路形成面の接地電極にバンプ９を形成し、
そのバンプ９と接地端子５とを物理的に圧着し、電気的
に接続する。In this embodiment, the ground terminal 5 is fixed on the circuit formation surface of the semiconductor element 2. As the fixing method, a circuit where the ground terminal is traversed is performed through an insulating film 7 such as a polyimide film having a double-sided insulating adhesive 8 except for the ground electrode portion of the circuit forming surface where the ground terminal is traversed. Bump 9 is formed on the ground electrode on the forming surface,
The bump 9 and the ground terminal 5 are physically pressure-bonded and electrically connected.

【００１９】このような構造であれば、半導体素子２を
リードフレームに固着した時に、複数の半導体素子２の
接地電極は電気的に接続され、かつ、接地電位安定化の
ために、半導体素子２に接地電極があれば、接地端子５
が半導体素子２の近傍を横断しているので、接地用電極
を任意の位置で金属細線６にて接続できる。With such a structure, when the semiconductor element 2 is fixed to the lead frame, the ground electrodes of the plurality of semiconductor elements 2 are electrically connected and the semiconductor element 2 is stabilized for ground potential stabilization. If there is a ground electrode on the ground terminal 5
Since it crosses the vicinity of the semiconductor element 2, the grounding electrode can be connected by the thin metal wire 6 at an arbitrary position.

【００２０】実施例２においては、接地端子との接続を
バンプで行うため、接地端子とペレット面との接続を金
属細線で行う必要が少なくなり、実施例１に比べ、信号
端子の接続の自由度が、更に増すという効果を有する。In the second embodiment, since the connection to the ground terminal is made by the bump, it is less necessary to make the connection between the ground terminal and the pellet surface by the fine metal wire, and the connection of the signal terminal can be made more freely than in the first embodiment. This has the effect of further increasing the frequency.

【００２１】[0021]

【発明の効果】以上説明したように本発明は、半導体素
子の回路形成面上に接地端子を横断させることにより、
従来１００ピン程度の樹脂封止型半導体装置には、１０
本必要であった接地端子を４本で実現できるという効果
を有し、従って、信号配線の接続の自由度が増すという
効果を有する。As described above, according to the present invention, the ground terminal is traversed on the circuit formation surface of the semiconductor element,
The conventional resin-encapsulated semiconductor device with about 100 pins has 10
This has the effect that the four required ground terminals can be realized, thus increasing the degree of freedom in connecting the signal wiring.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例１を示す平面図である。FIG. 1 is a plan view showing a first embodiment of the present invention.

【図２】図１のＡ−Ａ′線断面図である。FIG. 2 is a sectional view taken along the line AA ′ of FIG.

【図３】本発明の実施例２を示す平面図である。FIG. 3 is a plan view showing a second embodiment of the present invention.

【図４】図３のＢ−Ｂ′線断面図である。FIG. 4 is a sectional view taken along line BB ′ of FIG.

【図５】従来の樹脂封止型半導体装置を示す平面図であ
る。FIG. 5 is a plan view showing a conventional resin-sealed semiconductor device.

【図６】図５のＣ−Ｃ′線断面図である。6 is a cross-sectional view taken along the line CC ′ of FIG.

【符号の説明】[Explanation of symbols]

１ 封止樹脂層 ２ 半導体素子 ３ 内部リード ４ 外部リード ５ 接地端子 ６ 金属細線 ７ 絶縁フィルム ８ 両面絶縁性接着剤 ９ バンプ １０ 半導体素子搭載部 １１ Ａｇペースト DESCRIPTION OF SYMBOLS 1 Sealing resin layer 2 Semiconductor element 3 Internal lead 4 External lead 5 Ground terminal 6 Metal thin wire 7 Insulating film 8 Double-sided insulating adhesive 9 Bump 10 Semiconductor element mounting part 11 Ag paste

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 封止樹脂層内部から外部へ延在する外部
電極取出用の複数の内部リードを有する樹脂封止型半導
体装置であって、 内部リードのうち少なくとも２本の接地用端子を半導体
素子の回路形成面上に配置し、かつ電気絶縁性接着層に
より半導体素子の回路形成面上に固着したことを特徴と
する樹脂封止型半導体装置。1. A resin-sealed semiconductor device having a plurality of internal leads for extracting external electrodes, which extend from the inside of a sealing resin layer to the outside, wherein at least two grounding terminals of the internal leads are semiconductors. A resin-encapsulated semiconductor device, which is arranged on a circuit forming surface of an element and fixed to the circuit forming surface of a semiconductor element by an electrically insulating adhesive layer. 【請求項２】 前記電気絶縁性接着層は、ポリイミドフ
ィルムの両面に電気絶縁性接着剤を設けた構造のもので
あることを特徴とする請求項１に記載の樹脂封止型半導
体装置。2. The resin-encapsulated semiconductor device according to claim 1, wherein the electrically insulating adhesive layer has a structure in which an electrically insulating adhesive is provided on both surfaces of a polyimide film.
JP4121359A 1992-04-15 1992-04-15 Plastic sealed semiconductor device Pending JPH05291478A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4121359A JPH05291478A (en) 1992-04-15 1992-04-15 Plastic sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4121359A JPH05291478A (en) 1992-04-15 1992-04-15 Plastic sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH05291478A true JPH05291478A (en) 1993-11-05

Family

ID=14809309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4121359A Pending JPH05291478A (en) 1992-04-15 1992-04-15 Plastic sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH05291478A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19704343A1 (en) * 1997-02-05 1998-08-20 Siemens Ag Assembly method for semiconductor components
EP0840375A3 (en) * 1996-10-29 1999-10-13 Nec Corporation Chip-lead interconnection structure in a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0840375A3 (en) * 1996-10-29 1999-10-13 Nec Corporation Chip-lead interconnection structure in a semiconductor device
US6016003A (en) * 1996-10-29 2000-01-18 Nec Corporation Chip-lead interconnection structure in a semiconductor device
DE19704343A1 (en) * 1997-02-05 1998-08-20 Siemens Ag Assembly method for semiconductor components

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