JPH04271137A - Semiconductor package for high frequency - Google Patents

Semiconductor package for high frequency

Info

Publication number
JPH04271137A
JPH04271137A JP3260191A JP3260191A JPH04271137A JP H04271137 A JPH04271137 A JP H04271137A JP 3260191 A JP3260191 A JP 3260191A JP 3260191 A JP3260191 A JP 3260191A JP H04271137 A JPH04271137 A JP H04271137A
Authority
JP
Japan
Prior art keywords
semiconductor package
lid
package
chip
high frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3260191A
Other languages
Japanese (ja)
Inventor
Yutaka Miyamoto
裕 宮本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3260191A priority Critical patent/JPH04271137A/en
Publication of JPH04271137A publication Critical patent/JPH04271137A/en
Pending legal-status Critical Current

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  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve characteristics in a high frequency region, and miniaturize a package. CONSTITUTION:Protrusions 11 are formed in the inside of the lid of a semiconductor package, and set so as to be able to come into contact with the bonding area on the surface of a chip and an electrode part of the package. A wiring is formed in the inside the lid of the semiconductor package, so as to connect the bonding area of the chip with the electrode part. The semiconductor package is constituted by combining the lid 10 and a main body 11.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、高周波用半導体パッケ
ージに関し、特にパッケージの小型化ならびに高周波特
性を向上させる構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency semiconductor package, and more particularly to a structure for reducing the size of the package and improving high frequency characteristics.

【0002】0002

【従来の技術】図3は従来のFET用半導体パッケージ
の内部を示した斜視図である。図において、チップ1は
半導体パッケージ2の内部に形成されたソースメタライ
ズ部3上に搭載される。またチップ1に設けられたボン
ディングエリアより、金ワイヤ4でソースメタライズ部
3,ゲートメタライズ部5,ドレインメタライズ部6に
連結されている。各メタライズ部はソースリード7,ゲ
ートリード8,ドレインリード9を介して外部に接続さ
れている。
2. Description of the Related Art FIG. 3 is a perspective view showing the inside of a conventional FET semiconductor package. In the figure, a chip 1 is mounted on a source metallized portion 3 formed inside a semiconductor package 2. As shown in FIG. Further, from a bonding area provided on the chip 1, it is connected to a source metallized portion 3, a gate metallized portion 5, and a drain metallized portion 6 by gold wires 4. Each metallized portion is connected to the outside via a source lead 7, a gate lead 8, and a drain lead 9.

【0003】0003

【発明が解決しようとする課題】従来の半導体パッケー
ジを用いた高周波用FET素子の場合、チップより電極
へ金ワイヤを用いて接続している為、この部分で高周波
領域において、浮遊容量や余分なインダクタンス成分が
発生し、高周波特性に大きな影響を与えるといった問題
点があった。
[Problems to be Solved by the Invention] In the case of high-frequency FET elements using conventional semiconductor packages, since the chip is connected to the electrode using a gold wire, stray capacitance and excess There was a problem in that an inductance component was generated, which greatly affected high frequency characteristics.

【0004】本発明は上記のような問題点を解消するた
めになされたもので、高周波特性を向上させかつ、半導
体パッケージの小型化を図ることを目的とする。
The present invention has been made to solve the above-mentioned problems, and aims to improve high frequency characteristics and reduce the size of a semiconductor package.

【0005】[0005]

【課題を解決するための手段】本発明に係る高周波用半
導体パッケージは、半導体パッケージのふた内部に突起
及び配線を行ない、チップ及び半導体パッケージ内部の
電極に接続できるように構成したものである。
[Means for Solving the Problems] A high-frequency semiconductor package according to the present invention is configured such that projections and wiring are provided inside the lid of the semiconductor package so that they can be connected to a chip and an electrode inside the semiconductor package.

【0006】[0006]

【作用】本発明における半導体パッケージのふたは、こ
のパッケージのふたの部分に突起及び配線を行ない、チ
ップ及び半導体パッケージ内部の電極に接続できるよう
構成したので、高周波特性を向上させ、また、半導体パ
ッケージの大きさを小さくすることができる。
[Function] The lid of the semiconductor package according to the present invention is configured to have protrusions and wiring on the lid portion of the package so that it can be connected to the chip and the electrodes inside the semiconductor package. The size of can be reduced.

【0007】[0007]

【実施例】実施例1.以下、本発明の一実施例を図につ
いて説明する。図1は本発明の実施例1を示すパッケー
ジ本体及びふたの展開斜視図、図2はふたの断面図を示
す。図において、10はふた、11はふた10に設けら
れた通電用突起である。なお、その他の符号は前記従来
のものと同一につきその説明は省略する。
[Example] Example 1. Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an exploded perspective view of a package body and a lid showing a first embodiment of the present invention, and FIG. 2 is a sectional view of the lid. In the figure, 10 is a lid, and 11 is a current-carrying protrusion provided on the lid 10. Note that the other symbols are the same as those of the conventional device, so the explanation thereof will be omitted.

【0008】次に動作について説明する。半導体パッケ
ージのふた10の内部に、図示の如く通電用突起11が
設けられている。この突起11は、チップ1表面のボン
ディングエリア及び半導体パッケージの電極部に合うよ
うにその位置が設定されている。半導体パッケージのふ
た10内部には電極とチップ1のボンディングエリア接
続されるよう、配線がなされている。ふた10をパッケ
ージ本体2と合わせて半導体パッケージを構成する。こ
れにより、チップ1のボンディングエイアとリードが電
気的に接続される。
Next, the operation will be explained. As shown in the figure, a current-carrying projection 11 is provided inside the lid 10 of the semiconductor package. The position of the protrusion 11 is set to match the bonding area on the surface of the chip 1 and the electrode portion of the semiconductor package. Wiring is provided inside the lid 10 of the semiconductor package to connect the electrodes to the bonding areas of the chip 1. The lid 10 and the package body 2 constitute a semiconductor package. As a result, the bonding air and the leads of the chip 1 are electrically connected.

【0009】[0009]

【発明の効果】以上のように本発明によれば、半導体パ
ッケージのふたの部分に信号ラインを構成し、チップ及
びパッケージ内部の電極に接続できるよう構成したので
、高周波特性を向上させ、また半導体パッケージの大き
さを小さくすることができるというすぐれた効果を有す
る。
As described above, according to the present invention, the signal line is formed on the lid of the semiconductor package and is configured to be connected to the chip and the electrodes inside the package. This has the excellent effect of reducing the size of the package.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】この発明の実施例1を示す半導体パッケージの
展開斜視図である。
FIG. 1 is an exploded perspective view of a semiconductor package showing a first embodiment of the present invention.

【図2】図1のII−II線における断面図である。FIG. 2 is a sectional view taken along line II-II in FIG. 1;

【図3】従来のパッケージ本体の斜視図である。FIG. 3 is a perspective view of a conventional package body.

【符号の説明】[Explanation of symbols]

1  チップ 2  パッケージ本体 3  ソースメタライズ 5  ゲートメタライズ 6  ドレインメタライズ 10  ふた 11  突起 1 Chip 2 Package body 3 Source metallization 5 Gate metallization 6 Drain metallization 10 Lid 11 Protrusion

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  半導体パッケージのふたの内部に、前
記パッケージ本体内部に搭載するチップのボンディング
エリアに合うように突起を設け、かつ前記パッケージ本
体内部の電極部に合うように突起を設け、前記半導体パ
ッケージのふた内部に配線を行い、前記各突起を結合す
ることにより、信号及びバイアスをチップに供給できる
ようにしたことを特徴とする高周波用半導体パッケージ
1. A protrusion is provided inside a lid of a semiconductor package to fit a bonding area of a chip mounted inside the package body, and a protrusion is provided to fit an electrode part inside the package body, 1. A high frequency semiconductor package, characterized in that signals and bias can be supplied to the chip by wiring inside the lid of the package and connecting the respective protrusions.
JP3260191A 1991-02-27 1991-02-27 Semiconductor package for high frequency Pending JPH04271137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3260191A JPH04271137A (en) 1991-02-27 1991-02-27 Semiconductor package for high frequency

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3260191A JPH04271137A (en) 1991-02-27 1991-02-27 Semiconductor package for high frequency

Publications (1)

Publication Number Publication Date
JPH04271137A true JPH04271137A (en) 1992-09-28

Family

ID=12363385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3260191A Pending JPH04271137A (en) 1991-02-27 1991-02-27 Semiconductor package for high frequency

Country Status (1)

Country Link
JP (1) JPH04271137A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120372A (en) * 1992-10-08 1994-04-28 Nec Corp Ceramic semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120372A (en) * 1992-10-08 1994-04-28 Nec Corp Ceramic semiconductor device

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