JPS60160637A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPS60160637A
JPS60160637A JP59016410A JP1641084A JPS60160637A JP S60160637 A JPS60160637 A JP S60160637A JP 59016410 A JP59016410 A JP 59016410A JP 1641084 A JP1641084 A JP 1641084A JP S60160637 A JPS60160637 A JP S60160637A
Authority
JP
Japan
Prior art keywords
recess
metallized layers
metallized
rear face
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59016410A
Other languages
Japanese (ja)
Inventor
Naofumi Tsuzuki
都築　直文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59016410A priority Critical patent/JPS60160637A/en
Publication of JPS60160637A publication Critical patent/JPS60160637A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To substantially reduce the parasitic capacity between input and output for improving the high-frequency characteristics, by providing a recess at the center of the rear face of an insulative substrate and arranging a plurality of metallized layers so as to surround the recess. CONSTITUTION:A ceramic base 1 has a recess 18 at the center on the rear face side thereof. This recess 18 preferably has a depth corresponding to at least 50% of the thickness of the ceramic base 1. Rear face metallized layers 12, 13 and 5a, 5b are arranged so as to surround the recess 18. By forming the recess 18 in such a manner, an air gap is provided partially within and in series with the ceramic interposed between the metallized layers 8 and 9. Therefore, the dielectric constant of this section becomes 1/10 of that of alumina, and the electrostatic capacity as a parallel-plate capacitor is substantially reduced. This recess 18 also reduces the gap capacitance generated between the metallized layers 12 and 13 by the same reason. Accordingly, the parasitic capacity can be substantially recuded as a whole.

Description

【発明の詳細な説明】 （発明の技術分野） 本発明はマイクロ波半纏体素子用容器にかかり、特に低
雑音トランジスタ用素子用容器に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a container for a microwave semi-integrated device, and more particularly to a container for a low noise transistor device.

（発明の背ｔ） マイクロ波帯、特にＸ帯のように動作周波数が、高い領
域で動作する低雑音トランジスタでは素子容器の寄生素
子、即ちメタライズ層及びリード等によって形成される
キャパシタンス成分やインダクタンス成分により大幅に
高周波特性の劣化が生じるため、素子容器の形状を可能
な限り小さく設計する必要がおる。(Background of the invention) In low-noise transistors that operate in a high operating frequency region such as the microwave band, especially the Since this causes a significant deterioration of high frequency characteristics, it is necessary to design the shape of the element container as small as possible.

素子容器の製造技術上及び機械的強度のため、おのずと
素子容器の形状の小型化にも制限があり、通常１．５〜
２ｍｍ角で厚さ０．４８〜０．６晒程度のアルミナ材が
素子容器の基本として使用され、各電極のメタライズ層
が表面、側面および裏面上に形成され、谷型極間に上述
の寄生的な静電容量が生じる。特に小型化により厚さに
対して基本のは径が小さくなるため、従来問題とならな
かりｆｃｌｌｌＪ面メタライズによる寄生容量が無視で
きないものとなっており、相対する入力電極用と出力電
極用の側面メタライズ層により、アルミナ材を介して生
じる静１１６．容量は帰還寄生素子として素子特性全大
幅に低下させる問題を生じつつあり、今後の高周波化の
大きな＃否となっている。Due to the manufacturing technology and mechanical strength of the device container, there is a limit to the miniaturization of the device container shape, and it is usually 1.5 to
A 2 mm square alumina material with a thickness of about 0.48 to 0.6 mm is used as the basis of the element container, and the metallized layer of each electrode is formed on the front, side and back surfaces, and the above-mentioned parasitic A static capacitance is generated. In particular, due to miniaturization, the basic diameter becomes smaller compared to the thickness, so the parasitic capacitance due to the fclllJ surface metallization cannot be ignored, which is not a problem in the past, and the side surfaces for the opposing input and output electrodes. The static 116. generated through the alumina material due to the metallized layer. Capacitance, as a feedback parasitic element, is causing the problem of significantly deteriorating all device characteristics, and is becoming a major hindrance to higher frequencies in the future.

（発明の目的ン 本発明は上記問題点に対処してなされたもので、その目
的とする所は入出力間の寄生容量を大幅に低減して、高
周波特性を改善し得るマイクロ波半導体素子用容器を提
供するにある。(Purpose of the Invention) The present invention has been made to address the above-mentioned problems, and its purpose is to significantly reduce the parasitic capacitance between input and output, and to improve the high frequency characteristics of microwave semiconductor devices. There are containers to provide.

（発明の構造） 本発明によれば、絶縁性基体の裏面に凹部が設けられ、
この凹部と対向する表面に半導体素子が載置され、この
半導体素子の電極が絶縁性基体の表面から側面葡介して
裏面に専用されている半尋体累子用答器を得る。このよ
うに本発明の容器によれは、従来の入出力間の寄生容量
を容易に半減することができ、かつ根本的な素子答器製
童のコストアップ戦力を含まないため、高性能で安価な
半導体装置ｍを実現できる。(Structure of the invention) According to the invention, a recess is provided on the back surface of the insulating substrate,
A semiconductor element is placed on the surface facing the recess, and the electrodes of the semiconductor element are dedicated to the back surface of the insulating substrate from the front surface through the side surfaces. In this way, the container of the present invention can easily halve the parasitic capacitance between conventional input and output, and does not involve the fundamental cost-increase of device manufacturing, resulting in high performance and low cost. A semiconductor device m can be realized.

以下、本発明ｔよりよく明確にするため図面を参照して
より詳細に説明する。Hereinafter, the present invention will be described in more detail with reference to the drawings for better clarity.

（従来例） 従来のマイクロ波帯の低雑音ＧａＡｓ　Ｆ／ＥＴの一例
を第１図（ａｌ　、　（ｂｌ　、　（Ｃ）に示す。セラ
ミック基体ｌの上面中央部から端部まで帯状のチップ搭
載用メタライズパターン２が形成され、ソース電極とし
て基体ｌの側面メタライズ層３ａ、３ｂｔ介して裏面の
ソース電極端子４ａ、４ｂ用のメタライＸ層５ａ、５ｂ
と尋通している。またチップ搭載用メタライズパターン
２を中心に、その両側に入力メタライズ層６．出力メタ
ライズ層７が形成され、前記のソース電極と同様にセラ
ミック基体ｌの側面メタ２イズ層８　、９．ｔ−各々介
して裏面の入力端子ｌＯおよび出力端子１１用メタライ
ズ／１ｉＩ１２゜１３に各々場通されている。またセラ
ミック基体ｌの上部にはチップ搭載用メタライズパター
ン２の上にＦＥＴチップ１４が搭載され、チップ上面の
ゲート、ドレインおよびソースの電極からボンディング
＠１５，１６および１７ａ、１７ｂにより各々入力メタ
ライズ層６．出力メタライズ層７およびチップ搭載用メ
タライズノー２に電気的に接続されている。通常ＦＥＴ
テップを内紙するようにセラミック基体ｌの表面上にキ
ャップを接着封止して、使用に供せられる。(Conventional example) An example of a conventional low-noise GaAs F/ET in the microwave band is shown in Figure 1 (al, (bl, (C)).A strip-shaped chip is mounted from the center to the edge of the top surface of the ceramic substrate l. A metallized pattern 2 is formed, and metallized X layers 5a, 5b for source electrode terminals 4a, 4b on the back side are formed as source electrodes via side metallized layers 3a, 3bt of the base l.
I am asking. Furthermore, an input metallization layer 6 is formed on both sides of the metallization pattern 2 for mounting the chip. An output metallization layer 7 is formed on the side metallization layers 8, 9. of the ceramic substrate l, similar to the source electrode described above. t- are connected to the input terminal IO and output terminal 11 metallization/1iI12-13 on the back side through each. Further, an FET chip 14 is mounted on the metallized pattern 2 for chip mounting on the upper part of the ceramic substrate l, and the input metallized layer 6 is connected to the gate, drain, and source electrodes on the upper surface of the chip by bonding@15, 16 and 17a, 17b, respectively. ．． It is electrically connected to the output metallized layer 7 and the chip mounting metallized layer 2. Normal FET
The cap is adhesively sealed on the surface of the ceramic substrate 1 so that the cap is placed inside, and the ceramic substrate 1 is ready for use.

以上の構造において、入力と出力の両端子間に生じる寄
生容量は入力端子１０と接続しているメタライズ層６，
８および１２）出力端子１１と接続しているメタライズ
層７，９．１３との間に誘電体として働くセラミック基
体１ｆｆｉ介して静電容量が生じるが、セラミックの直
径に対して厚さが厚くなる程、平行平板コンデンサーを
形成しているメタライズＩｖ８と９によって生じる静電
容量が増加する。このためセラミック基体ｌを小形化し
てメタライズ層によジ生じるインダクタンス成分を最小
化することは可能ではあるが、キャパ７タンス成分は逆
に増加するという欠点が生じ、Ｘ帝等のマイクロ波帯に
おける利得や、雑音指数等のＲＦ％性の改善に限界が生
じていた。In the above structure, the parasitic capacitance generated between the input and output terminals is the metallized layer 6 connected to the input terminal 10,
8 and 12) Capacitance is generated between the output terminal 11 and the connected metallized layers 7, 9, and 13 through the ceramic substrate 1ffi that acts as a dielectric, but the thickness is large relative to the diameter of the ceramic. As the capacitance increases, the capacitance generated by the metallizations Iv8 and 9 forming a parallel plate capacitor increases. For this reason, although it is possible to minimize the inductance component generated by the metallized layer by downsizing the ceramic substrate l, there is a drawback that the capacitance component increases, and in the microwave band such as There has been a limit to the improvement of RF characteristics such as gain and noise figure.

（発明の実施例） 第２図は本発明の一実施例に示す構造図で、第２図（ａ
ｔ　、　（ｃｌは表口及び裏面の平面図、同図（ｂ）は
断面図である。これらの図において、第１図（ａ）。(Embodiment of the invention) FIG. 2 is a structural diagram showing an embodiment of the present invention.
t, (cl is a plan view of the front and back surfaces, and FIG. 1(b) is a cross-sectional view. In these figures, FIG. 1(a).

（ｂ）　、　（ｃ）と同一の部分は同一の記号を付した
。従来構造と本構造の違いはセラミック基体ｌの構造に
必り１本構造においてはセラミック基体ｌの矢面側の中
央部に凹部１８をＭしている。この凹部１８はセラミッ
ク基体ｌの厚さの少くとも５０％以上の厚さを有してい
ることが望ましい。また凹部１８は裏面メタライズ層１
２．１３および５ａ、５ｂに囲まれた状態に配置される
。こＯ凹部１８の形成、により、メタライズ層８と９の
間に介在するセラミックに直列にエアーギャップが部分
的に押入された形となる。このためこの部分の比訪電率
はアルミナのｌ／ｌＯとなり、平行平板コンデンサーと
しての静電容ｉｔは大幅に低下する。因みにセラミック
基体ｌがアルミナの場合、凹部１８の直径がセラミック
基体ｌの直径の３０％で、深さが基体ｌの厚さの７０チ
の場合では平行平板コンデンサ部分により生じる静電容
ｔは約５０チ減少する。The same parts as in (b) and (c) are given the same symbols. The difference between the conventional structure and the present structure is in the structure of the ceramic substrate 1. In the single structure, a recess 18 is formed in the center of the ceramic substrate 1 on the front side. It is desirable that the recess 18 has a thickness that is at least 50% of the thickness of the ceramic substrate l. Furthermore, the recess 18 is formed by the backside metallized layer 1.
It is placed surrounded by 2.13, 5a, and 5b. By forming the O recess 18, an air gap is partially inserted in series with the ceramic interposed between the metallized layers 8 and 9. Therefore, the specific current visit rate of this portion is 1/1O of alumina, and the capacitance it as a parallel plate capacitor is significantly reduced. Incidentally, if the ceramic substrate l is made of alumina, the diameter of the recess 18 is 30% of the diameter of the ceramic substrate l, and the depth is 70 inches the thickness of the substrate l, then the capacitance t generated by the parallel plate capacitor portion is approximately 50%. decrease.

またとの凹部１８はメタライズ層１２と１３の間に生じ
るギヤツブ容量？同様の理由により減少させ得るため、
総合的に大幅な寄生容量の低減が実現され得る。Also, the recess 18 is a gear capacitance generated between the metallized layers 12 and 13. Because it can be reduced for the same reason,
Overall, a significant reduction in parasitic capacitance can be achieved.

以上のように従来構造では寄生インダクタンス成分’ｋ
ｌｆｆｉ減させるために素子容器を小形化すると入出力
間に生じる寄生容量が増大しＲＦ特性の特性改善を妨害
していたが、本発明の構造では寄生容量を半減すること
が可能となり、ＩＮＦ％性の大幅な改善を実現すること
ができる。As mentioned above, in the conventional structure, the parasitic inductance component 'k
When the element container was downsized to reduce lffi, the parasitic capacitance generated between the input and output increased, which hindered the improvement of RF characteristics. However, with the structure of the present invention, it is possible to reduce the parasitic capacitance by half, and the INF% It is possible to achieve a significant improvement in performance.

尚、以上はＧａＡｓ　ＦＥＴの場合の実施例について説
明を行なったが、ＧａＡｓ　ＦＥＴに限らす、例えはシ
リコンバイポーラトランジスタ、マイクロ波ダイオード
の場合でも同様の効果が得られることは明らかである。Although the above embodiment has been explained in the case of a GaAs FET, it is clear that similar effects can be obtained not only in the case of a GaAs FET, but also in the case of a silicon bipolar transistor or a microwave diode.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ３　、　（ｃｌは従来のマイクロ波帯の低雑
音ＧａＡｓ　ＦＥＴの構造を示す基板上表面および下表
面の平面図、同図１ｂｌはその断面図である。 第２図（ａ）　、　（ｃｌは本発明の一笑施例を示すＧ
ａＡｓＦＥＴの基板上表面および下表面の平面図、同図
（ｂｌはその断面図である。 ｌ・・・・・・セラミック基体％　２・・・・・・テッ
プ搭載用メタライズ層、３・・・・・・側面メタライズ
層、４・・・・・・ソース電極端子、５・・・・・・メ
タライズ層、６・・・・・・入力メタライズ層、７・・
・・・・出力メタライズ層、８．９・・・・・・側面メ
タライズ層％　ｌＯ・・・・・・入力電極端子、１１・
・・・・・出力電極端子、１２．１３・・・・・・メタ
ライズ層、１４・・・・・・ＦＥＴチップ、１５，１６
．１７・・・・・・ボンディング線％　１８・・・・・
・セラミック基体の凹部。 第１図（Ｃ） 箔２囮１（１）Figure 1 (a3, cl is a plan view of the upper and lower surfaces of the substrate showing the structure of a conventional microwave band low-noise GaAs FET, and Figure 1bl is a cross-sectional view thereof. Figure 2 (a), (cl indicates a simple embodiment of the present invention)
A plan view of the upper and lower surfaces of the substrate of the aAsFET, the same figure (bl is the cross-sectional view. l...ceramic substrate% 2... metallized layer for mounting the tip, 3... ... Side metallization layer, 4 ... Source electrode terminal, 5 ... Metallization layer, 6 ... Input metallization layer, 7 ...
...Output metallized layer, 8.9...Side metalized layer% lO...Input electrode terminal, 11.
... Output electrode terminal, 12.13 ... Metallized layer, 14 ... FET chip, 15, 16
．． 17...Bonding wire% 18...
- Concavity in ceramic base. Figure 1 (C) Foil 2 Decoy 1 (1)

Claims (1)

【特許請求の範囲】 ｌ）複数個のメタライズ層が絶縁性基板の上面と底面に
各々形成され、前記上面と底面の相対するメタライズ層
が側面上のメタ２イズ層により接続された半導体素子用
容器において、前記絶縁性基板の前記底面の中央部に凹
部が設けられ、該凹部葡囲むように前記複数個のメタラ
イズ層が配置されていることｖｆ−％徴とする半導体素
子用容器。 ２）前記凹部の深さに前記絶縁性基板の厚さの半分以上
であること′ｌｃ％徴とする特許請求の範囲第１項記載
の半導体素子用容器。[Claims] l) For a semiconductor device in which a plurality of metallized layers are respectively formed on the top and bottom surfaces of an insulating substrate, and opposing metallized layers on the top and bottom surfaces are connected by a metallized layer on the side surface. A container for a semiconductor device, characterized in that a recess is provided in the center of the bottom surface of the insulating substrate, and the plurality of metallized layers are arranged so as to surround the recess. 2) The semiconductor device container according to claim 1, wherein the depth of the recess is equal to or more than half the thickness of the insulating substrate.
JP59016410A 1984-01-31 1984-01-31 Package for semiconductor device Pending JPS60160637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59016410A JPS60160637A (en) 1984-01-31 1984-01-31 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59016410A JPS60160637A (en) 1984-01-31 1984-01-31 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPS60160637A true JPS60160637A (en) 1985-08-22

Family

ID=11915466

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59016410A Pending JPS60160637A (en) 1984-01-31 1984-01-31 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS60160637A (en)

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