JPS6122655A - Ultrahigh-frequency transistor device - Google Patents

Ultrahigh-frequency transistor device

Info

Publication number
JPS6122655A
JPS6122655A JP59144726A JP14472684A JPS6122655A JP S6122655 A JPS6122655 A JP S6122655A JP 59144726 A JP59144726 A JP 59144726A JP 14472684 A JP14472684 A JP 14472684A JP S6122655 A JPS6122655 A JP S6122655A
Authority
JP
Japan
Prior art keywords
input
output
electrode
matching circuit
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59144726A
Other languages
Japanese (ja)
Inventor
Takao Sakayori
酒寄　隆雄
Shigeo Iki
伊木　茂男
Naruhide Kojima
小嶋　考秀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59144726A priority Critical patent/JPS6122655A/en
Publication of JPS6122655A publication Critical patent/JPS6122655A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microwave Amplifiers (AREA)

Abstract

PURPOSE:To enable the substrate block to be the common one to the matching circuit by a method wherein a metal thin plate is inserted between the dielectric substrate constituting the matching circuit and the substrate block. CONSTITUTION:The source electrode 9 of a microwave high-output FET8 is installed on a protrusion part 7 formed at the central part of a substrate block 6 consisting of oxygen free high conductivity copper. A gate electrode 12 and a drain electrode 15 are respectively connected to a first capacitor electrode 11 and a second capacitor electrode 14. The input matching circuit is constituted of the capacitor electrode 11, a capacitor electrode 18, a capacitor, which is formed of a thin metal plate 16, and the inductances of fine conductor wires 19 and 20. The capacitance of the matching circuit can be adjusted by changing the thickness of a dielectric 10 and the height of the installing surfaces of the electrodes 12 and 15 can be adjusted by changing the thickness of the thin plates 16 and 17.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は超高周波トランジスタ装置、特にそのパッケ
ージの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a super high frequency transistor device, and particularly to the structure of its package.

〔従来技術〕[Prior art]

超高周波トランジスタ、特にマイクロ波高出力トランジ
スタにおいては素子自体のインピーダンスが低く、この
素子をパッケージに収納する場合、パッケージの寄生要
素の影響が大きく、パッケージの厳密な回路的設計が必
要となる。しかし、トランジスタ素子のみを収納するパ
ッケージ方式では、周波数が高くなるほど、パッケージ
の回路設計上素子に適合した構造を得るのが困難となり
、特性の劣化は免れなかった。Ultra-high frequency transistors, especially microwave high-power transistors, have low impedance, and when this device is housed in a package, the influence of parasitic elements of the package is large, and strict circuit design of the package is required. However, in a package system that houses only a transistor element, as the frequency increases, it becomes difficult to obtain a structure that is suitable for the element in terms of circuit design of the package, and deterioration of characteristics is inevitable.

そこで、この問題を解決する一方法として、整合回路を
小形化してパッケージ内にトランジスタとともに収納す
る、いわゆる内部整合化が進められている。マイクロ波
回路では一般に特性インピ−ダンス５０Ωの線路が採用
されているので、パッケージの入出力インピーダンスを
上記特性インピーダンスに整合させればよくなり、比較
的構造は簡単になる。Therefore, as a method to solve this problem, so-called internal matching, in which the matching circuit is miniaturized and housed together with the transistor in a package, is being promoted. Since microwave circuits generally employ lines with a characteristic impedance of 50Ω, it is sufficient to match the input/output impedance of the package to the characteristic impedance, resulting in a relatively simple structure.

ところが、各種トランジスタに対してそれぞれ上記要求
に沿った内部整合回路を設計製作する必要がある。そし
て、内部整合回路としては集中定数素子による多段フィ
ルタ構成が採用されており、それを構成する直列インダ
クタンスにはボンディング線のインダクタンスが用いら
れ、また構成を簡単にするため多段複数個の並列キャパ
シタは一枚の誘電体板を用いて構成されている。このよ
うな整合回路をパッケージ内に組込む場合、並列キャパ
シタはトランジスタの特性仕様によって異なるので、誘
電体板の厚さが一定の場合にはその面積従ってパッケー
ジの基体ブロックの寸法が異な勺各種のパッケージを準
備する必要があった。また、誘電体板の厚さを変化させ
て面積を一定に保ったまま各種仕様に対応しようとする
と、フリツ。However, it is necessary to design and manufacture internal matching circuits that meet the above requirements for each type of transistor. A multi-stage filter configuration using lumped constant elements is adopted as the internal matching circuit, and the inductance of a bonding wire is used as the series inductance that constitutes the circuit, and in order to simplify the configuration, multiple parallel capacitors in multiple stages are used. It is constructed using a single dielectric plate. When incorporating such a matching circuit into a package, the parallel capacitors differ depending on the characteristics specifications of the transistor, so if the thickness of the dielectric plate is constant, its area and therefore the dimensions of the package base block may differ. It was necessary to prepare. Also, if you try to respond to various specifications by changing the thickness of the dielectric plate while keeping the area constant, you will experience frizz.

ブチツブマウントの超高周波電界効果トランジスタ用パ
ッケージの場合、基体ブロックへ直接取り付ける電極と
当該誘電体板を介して取り付ける電極との関係で、誘電
体板の厚さが変化するとそれに応じて各釉のパッケージ
基体ブロックを準備する必要があった。In the case of a bump-mount ultra-high frequency field effect transistor package, the relationship between electrodes that are attached directly to the base block and electrodes that are attached through the dielectric plate changes.When the thickness of the dielectric plate changes, each glaze changes accordingly. It was necessary to prepare a package base block.

〔発明の概要〕[Summary of the invention]

この発明は以上のような点にｉみてなされたもので、パ
ッケージ基体ブロックは共通のものを用い、誘電体板と
基体ブロックとの間に金属薄板を挿入して用いることに
よって、誘電体板の厚さに応じて金属薄板の厚さを変化
させるのみで、種々の仕様に対して、同一のパッケージ
基体ブロックで対応できる超高周波トランジスタ装置の
構造を提供するものである。This invention was made in view of the above points, and by using a common package base block and inserting a thin metal plate between the dielectric plate and the base block, the dielectric plate The present invention provides a structure of an ultra-high frequency transistor device that can be used with the same package base block to meet various specifications by simply changing the thickness of the thin metal plate depending on the thickness.

〔発明の実施例〕[Embodiments of the invention]

図はこの発明の一実施例の構成を示す断面図で、外部引
出し端子（１）　、　（２＋およびこれらからそれぞれ
引出された金属リード線（”）　ｐ　（’ｓ）を備えた
アルミナ・セラミクスフレーム（５）が固着され無酸素
銅からなる基体ブロック（６）の中央部に形成された突
出部（７）にマイクロ波高出力電界効果トランジスタ（
８）のソース電極（９）を入力側誘電体板σＱ上の第１
のキャパシタ電極０υにゲート電極（２）を、出力側誘
電体板α砕土の第２のキャパシタ電極Ｑ４にドレイン電
極αＱを装着し、両誘電体板（１０、Ｑ、Ｉはそれぞれ
金属薄板ＱＱ　、αηを介して基体ブロック（６）Ｋ固
着されている。The figure is a sectional view showing the configuration of an embodiment of the present invention, which includes an alumina ceramic frame equipped with external lead terminals (1), (2+) and metal lead wires ('') p ('s) drawn out from these terminals. (5) is fixed to the protrusion (7) formed in the center of the base block (6) made of oxygen-free copper.
8) to the first source electrode (9) on the input side dielectric plate σQ.
A gate electrode (2) is attached to the capacitor electrode 0υ of the output side dielectric plate α, and a drain electrode αQ is attached to the second capacitor electrode Q4 of the output side dielectric plate α. The base block (6) K is fixed via αη.

入力側誘電体板曲の上には更に第３のキャパシタ間を導
体細線−で接続している。また、出力側誘電体板α１の
上には更に第４のキャパシタ電極Ｑ］）が形成され、第
２のキャパシタ電極Ｑ４１との間を導体細線に）で、出
力側外部引出し端子（２）との間を導体細線−で接続し
ている。このようにして、入力整合回路は第１および第
３のキャパシタ電極αυ、Ｄ１１Ｇが入力側誘電体板Ｑ
０を介して金属薄板θりとの間にそれぞれ形成する第１
および第３のキャパシタンスと導体細線α場、に）のイ
ンダクタンスとで構成され、出力整合回路は第２および
第４のキャパシタ電極（ロ）、Ｑｙが出力側誘電体板（
２）を介して金属薄板０７１との間にそれぞれ形成する
第２および第４のキャパシタンスと導体細線（４）、（
ホ）のインダクタンスとで構成される。A third capacitor is further connected to the input-side dielectric plate by a thin conductor wire. Furthermore, a fourth capacitor electrode Q]) is formed on the output side dielectric plate α1, and a thin conductive wire is connected between the output side external lead terminal (2) and the second capacitor electrode Q41. The two are connected by a thin conductor wire. In this way, the input matching circuit has the first and third capacitor electrodes αυ, D11G connected to the input side dielectric plate Q.
0, respectively formed between the thin metal plate θ and the
The output matching circuit consists of the second and fourth capacitor electrodes (b), and Qy is the output side dielectric plate (b).
2), the second and fourth capacitances formed respectively between the thin metal plate 071 and the thin conductor wire (4), (
It consists of the inductance (e).

従って、整合回路のキャパシタンスは両誘電体板（１０
、α→の厚さを変えるととＫよって調製でき、ゲート電
極（２）およびドレイン電極（ト）の装着面の高さは金
属薄板αす、Ｑηの厚さを変化させて一定に保持するこ
とができる。最後に１アルミナ・セラミックス板からな
るキャップ（ハ）によって気密に封止される。Therefore, the capacitance of the matching circuit is equal to both dielectric plates (10
The height of the mounting surface of the gate electrode (2) and drain electrode (G) can be adjusted by changing the thickness of the metal sheets α, α→ and K, and the height of the mounting surface of the gate electrode (2) and the drain electrode (G) can be kept constant by changing the thickness of the thin metal plates α, Qη. be able to. Finally, it is hermetically sealed with a cap (c) made of an alumina ceramic plate.

なお、この発明ではその超高周波トランジスタ、整合回
路の種類、形式、及び構造並びにパッケージのフレーム
およびキャップの素材、構造は上記実施例に限定される
ものではない。In the present invention, the types, formats, and structures of the ultra-high frequency transistor and matching circuit, as well as the materials and structures of the package frame and cap, are not limited to the above-mentioned embodiments.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明の超高周波トランジスタ
装置ではトランジスタ素子とともに容器内に装着される
整合回路を構成する誘電体板と基体ブロックとの間に金
属薄板を挿入し、整合回路の関係で誘電体板の厚さが変
化しても、これを金属薄板の厚さで補償することによっ
て、トランジスタ素子の接地電極を固着する基体ブロッ
クの中央突出部の高さを変える必要がなく、共通の基体
ブロックを用いることができ、容器の低価格化が達成で
きる。As explained above, in the ultra-high frequency transistor device of the present invention, a thin metal plate is inserted between the dielectric plate and the base block that constitute the matching circuit installed in the container together with the transistor element, and the dielectric Even if the thickness of the body plate changes, by compensating for this with the thickness of the thin metal plate, there is no need to change the height of the central protrusion of the base block to which the ground electrode of the transistor element is fixed, and a common base plate can be used. A block can be used, and the cost of the container can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

図はこの発明の一実施例の構成を示す断面図である。 図において、（１）は入力端子、（２）は出力端子、（
６）は基体ブロック、（７）は突出部、（８）は超高周
波トランジスタ素子、（９）は接地（ソース）電極、叫
は入力側誘電体板、α力はキャパシタ電極、（イ）は入
力（ゲート）電極、（２）は出力側誘電体板、ａＩＯは
キャパシタ電極、Ｑ！９は出力（ドレイン）電極、Ｑｌ
、α力は金属薄板、０す、翰は入力側引出導体（導体細
線）、（イ）、翰は出力側引出導体（導体細線）である
。The figure is a sectional view showing the configuration of an embodiment of the present invention. In the figure, (1) is an input terminal, (2) is an output terminal, (
6) is the base block, (7) is the protrusion, (8) is the ultra-high frequency transistor element, (9) is the ground (source) electrode, is the input side dielectric plate, α force is the capacitor electrode, (a) is Input (gate) electrode, (2) is output side dielectric plate, aIO is capacitor electrode, Q! 9 is the output (drain) electrode, Ql
, α force is a thin metal plate, 0 is a wire, an input side lead-out conductor (a thin conductor wire), (a), a wire is an output side lead-out conductor (a thin conductor wire).

Claims (1)

【特許請求の範囲】[Claims] （１）超高周波トランジスタ素子の接地電極を導体から
なる基体ブロックの上面中央部の突出部に直接固着し、
上記超高周波トランジスタ素子の入力および出力電極は
上記基体ブロックの上記突出部の両側の上面にそれぞれ
置かれた入力側および出力側誘電体板上のキャパシタ電
極に固着し、上記入力および出力電極からそれぞれ上記
入力側誘電体板で構成される入力側キャパシタと上記入
力電極からの引出導体のインダクタンスとからなる入力
整合回路および上記出力側誘電体板で構成される出力側
キャパシタと上記出力電極からの引出導体のインダクタ
ンスとからなる出力整合回路を介して入力端子および出
力端子を取り出したものにおいて、上記入力側および出
力側誘電体板と上記基体ブロックとの間にそれぞれ金属
薄板を設け、各上記誘電体板の厚さに応じて上記金属薄
板の厚さを変え、両者の和が一定になるようにしたこと
を特徴とする超高周波トランジスタ装置。(1) The ground electrode of the ultra-high frequency transistor element is directly fixed to the protrusion at the center of the upper surface of the base block made of a conductor,
The input and output electrodes of the ultra-high frequency transistor element are fixed to capacitor electrodes on the input and output side dielectric plates respectively placed on the upper surfaces of both sides of the protrusion of the base block, and are connected to the input and output electrodes respectively. An input matching circuit consisting of an input side capacitor constituted by the input side dielectric plate and an inductance of a lead-out conductor from the input electrode, and an output side capacitor constituted by the output side dielectric plate and a lead-out from the output electrode. An input terminal and an output terminal are taken out through an output matching circuit consisting of an inductance of a conductor, and thin metal plates are provided between the input side and output side dielectric plates and the base block, respectively, and each of the dielectric An ultra-high frequency transistor device characterized in that the thickness of the metal thin plate is changed according to the thickness of the plate so that the sum of both is constant.
JP59144726A 1984-07-10 1984-07-10 Ultrahigh-frequency transistor device Pending JPS6122655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59144726A JPS6122655A (en) 1984-07-10 1984-07-10 Ultrahigh-frequency transistor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59144726A JPS6122655A (en) 1984-07-10 1984-07-10 Ultrahigh-frequency transistor device

Publications (1)

Publication Number Publication Date
JPS6122655A true JPS6122655A (en) 1986-01-31

Family

ID=15368890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59144726A Pending JPS6122655A (en) 1984-07-10 1984-07-10 Ultrahigh-frequency transistor device

Country Status (1)

Country Link
JP (1) JPS6122655A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6009806A (en) * 1997-08-22 2000-01-04 Riso Kagaku Corporation Ink supply construction of printer having ink interrupting member
JP2009045945A (en) * 2008-12-05 2009-03-05 Tohoku Ricoh Co Ltd Stencil printing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6009806A (en) * 1997-08-22 2000-01-04 Riso Kagaku Corporation Ink supply construction of printer having ink interrupting member
JP2009045945A (en) * 2008-12-05 2009-03-05 Tohoku Ricoh Co Ltd Stencil printing device

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