JPH03217028A - Semiconductor device - Google Patents

Abstract

PURPOSE:To decrease a parasitic gate capacitance and to improve performance by arranging a low resistance gate wiring which is laid in parallel with the longitudinal direction of the gate electrode of a transistor and connects a gate electrode at a plurality of places on the upper part of the gate electrode. CONSTITUTION:A low-resistance gate wiring 34 which is connected to a gate pad 38 is laid in parallel with the longitudinal direction of a gate electrode 33. In this semiconductor device, the gate wiring 34 and the gate electrode 33 are connected at a plurality of places. The gate wiring 34 is arranged at the upper pat of the gate electrode 33. For example, a GaAs MES-FET is constituted as follows. The miniaturized gate electrode 33 is arranged in the gap between a drain electrode 31 and a source electrode 32. The gate wiring 34 using a low-resistance material is arranged at the upper part of the gate electrode 33. The gate electrode 33 and the gate wiring 34 are connected with a plurality of contact holes 35-37. A gate pad 38 for applying a gate voltage and the gate wiring 34 are connected with a piece of lead wire 39.

Description

[Detailed Description of the Invention] [Summary] In order to reduce the parasitic gate capacitance and improve the performance of semiconductor devices with miniaturized gate electrodes, a low-resistance gate wiring connected to the gate pad is connected to a transistor. A semiconductor device in which the gate wiring is laid parallel to the longitudinal direction of the gate electrode and the gate wiring and the gate electrode are connected at a plurality of points, the gate wiring being arranged above the gate electrode. Configure.

[Industrial application field]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which gate electrodes are miniaturized to achieve high-speed operation, and in particular to a semiconductor device intended to improve performance by reducing parasitic gate capacitance.

Compound semiconductor devices, e.g. GaAsMES-FET
The electron mobility (or hole mobility) of silicon (
Because it is considerably more expensive than Si), it is valued as a high-speed operation device.

However, in recent years, electronic devices tend to have higher processing speeds and higher signal frequencies, and even compound semiconductor devices are required to further improve their operating speeds.

[Conventional technology]

FIG. 5 is a diagram showing an example of a conventional semiconductor device.
It shows a cross section of the main part near the gate of the MES-FET. In this figure, 10 is a compound semiconductor substrate, 1l
is a source electrode, l2 is a drain electrode, and an extremely fine gate electrode l3 is formed on the substrate 10.

That is, the gate length L of the gate electrode 13 is made extremely short (for example, L=1/4 μm) to provide a short channel, thereby further improving the operating speed.

By the way, miniaturization of the gate electrode 13 causes a problem of increased gate resistance, so in the semiconductor device shown in FIG. 5, the cross-sectional shape of the gate electrode 13 is T-shaped (shape shown).
Alternatively, the cross-sectional area of the gate electrode 13 is increased by making it mushroom-shaped, thereby lowering the gate resistance.

However, in order to make the cross-sectional shape of the gate electrode l3 as described above, it is necessary to use, for example, a two-layer resist or to perform exposure twice, which complicates the manufacturing process and is disadvantageous in terms of cost. There is a problem.

FIG. 6 is a diagram showing another example of a conventional semiconductor device.
It represents a plan view of the main part near the gate of a AsMES-FET. In this figure, 2
0 is a drain electrode, 21 is a source electrode, and 22 is a gate electrode. The gate electrode 22 is connected to a low-resistance gate wiring 26 at three points via lead lines 23 to 25. Note that 27 is a gate pad for applying gate voltage, and 28 is a gate pad for applying gate voltage.
, 29 are power supply pads.

That is, a low resistance gate wiring 26 and three lead lines 23 to 2 are connected between the gate pad 27 and the gate electrode 22.
5, the combined line cross-sectional area can be increased, and the resistance from the gate pad 27 to the gate electrode 22 (
In other words, gate resistance) can be lowered.

[Problem to be solved by the invention]

However, in the conventional semiconductor device shown in FIG. Since the source electrode 21 and the gate wiring 26 and the source electrode 21 and the three lead lines 23 to 25 face each other over a large area, parasitic gate capacitance increases and the device There was a problem that performance deteriorated.

[Purpose of the invention]

The present invention was made in view of these problems, and
The aim is to improve performance by reducing parasitic gate capacitance by carefully arranging gate wiring.

[Means to solve the problem]

In order to achieve the above object, the present invention lays a low-resistance gate wiring connected to a pad parallel to the longitudinal direction of the gate electrode of a transistor, and connects the gate wiring and the gate electrode at multiple locations. The semiconductor device to be connected is characterized in that the gate wiring is arranged above the gate electrode.

[Effect]

In the present invention, the gate wiring is arranged avoiding the upper part of the source electrode. Therefore, the capacitance between the source electrode and the gate wiring, that is, the parasitic gate capacitance, is reduced, and the dehysing performance is improved.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 3 are diagrams showing a first embodiment of a semiconductor device according to the present invention, which is an example applied to a GaAs MES-FET.

In FIG. 1, the semiconductor device 30 of this embodiment has a miniaturized gate electrode 33 disposed in the gap between the drain electrode 31 and the source electrode 32, and above the gate electrode 33.
A gate wiring 34 using a low resistance material (for example, Ti/Pt/Au) is arranged, and these gate electrodes 33
and the gate wiring 34 are connected through a plurality of (three in the embodiment) contact holes 35 to 37, and one lead-out is connected between the gate pad 38 for gate voltage application and the gate wiring 34. It is configured by connecting with a line 39.

That is, a low-resistance gate wiring 34 connected to the gate pad 38 is laid parallel to the longitudinal direction of the gate electrode 33 of the transistor, and the gate wiring 34 and the gate electrode 33 are connected to each other.
are connected to each other at a plurality of locations through contact holes 35 to 37, and the gate wiring 34 is arranged above the gate electrode 33.

FIG. 2 is an enlarged view of the main part near one contact hole (for example, 37), where L is the gate length (for example, L+
= 1/4 μm), Lx is the gap between the drain electrode 31 and the source electrode 32 (for example, L2 = 2 μm), L3 is the width of the gate wiring 34 (for example, l. = 2 μm), and L4 is the length of one side of the contact hole 37. (For example, L4-1 μm).

As shown in FIG. 3, the semiconductor device 30 of this embodiment has a semi-insulating substrate 40 made of a compound semiconductor (e.g. GaAs), and an inter-element isolation 41 of, for example, an n-GaAs layer formed thereon. Ohmic electrodes (e.g. AuGe/Ni/A) as electrode 31 and source electrode 32
After the usual process of patterning the gate electrode 33 (e.g. Au), depositing the insulating film 42 (e.g. SiON), opening the contact holes 35 to 37, and depositing the gate electrode 33 (e.g. Au). Wiring metal as the wiring 34 (for example, T i / P t / A
It is manufactured by adding steps such as vapor deposition and patterning (u).

According to such a configuration, (1) the gate electrode 33 can be made finer and the operating speed can be improved;
In addition to the effect that gate resistance can be reduced by connecting 3 and gate pad 38 with low resistance,
(2) Since the gate wiring 34 and the lead line 39 are not located above the drain electrode 31 and the source electrode 32, unique effects such as parasitic gate capacitance can be reduced and device performance can be improved.

Note that in the above embodiment, the insulating film 42 is interposed between the substrate 40 and the gate wiring 34, but the invention is not limited to this.
For example, as shown in FIG. 4, which shows a second embodiment of the semiconductor device according to the present invention, a resist is applied instead of an insulating film, and after the gate wiring 34'' is formed, the resist is removed and the gate wiring 34'' is floated. (so-called air bridge wiring).

In this case, the gate wiring 34'' is supported by a contact pole 34a and a lead line (not shown) which are formed at the same time as the gate wiring 34''.

〔Effect of the invention〕

According to the present invention, since the gate wiring is arranged above the gate electrode, parasitic gate capacitance can be reduced and device performance can be improved.

[Brief explanation of drawings]

1 to 3 are diagrams showing a first embodiment of the semiconductor device according to the present invention, FIG. 1 is a plan view thereof, FIG. 2 is a plan view of the main part thereof, and FIG. ■A sectional view taken along the arrow 9. FIG. 4 is a sectional view of the essential parts of a second embodiment of the semiconductor device according to the present invention.9 FIG. 5 is a sectional view of the essential parts of an example of a conventional semiconductor device. FIG. 6 is a plan view showing another example of a conventional semiconductor device. 31...Drain electrode, 32...Source electrode, 33...Gate electrode, 34...Gate wiring, 34a...Contact ball, 35-37...
...Contact hole, 38...Gate pad, 39...Leader line, 40...Substrate, 41...Isolation between elements, 42... ...Insulating film. 10 Plan view of main parts of semiconductor device of first embodiment FIG. 2 FIG.

Claims (1)

[Claims] A semiconductor device in which a low-resistance gate wiring connected to a gate pad is laid parallel to the longitudinal direction of a gate electrode of a transistor, and the gate wiring and the gate electrode are connected at multiple points. A semiconductor device, characterized in that the gate wiring is arranged above a gate electrode.