JPS62296473A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62296473A JPS62296473A JP13951786A JP13951786A JPS62296473A JP S62296473 A JPS62296473 A JP S62296473A JP 13951786 A JP13951786 A JP 13951786A JP 13951786 A JP13951786 A JP 13951786A JP S62296473 A JPS62296473 A JP S62296473A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- oxide film
- glass layer
- phosphorus glass
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 11
- 239000012298 atmosphere Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 24
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims description 11
- 239000011574 phosphorus Substances 0.000 claims description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 abstract description 20
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 abstract description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract description 2
- 238000005111 flow chemistry technique Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 241000894007 species Species 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000282994 Cervidae Species 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000006200 vaporizer Substances 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
3、発明の詳細な説明
産業上の利用分野
本発明は半導体装置の製造方法に関し、特に金属−酸化
膜一半導体集積回路(以下MO3LSIと略す)を製造
するプロセスに関するものである。Detailed Description of the Invention 3. Detailed Description of the Invention Industrial Application Field The present invention relates to a method for manufacturing a semiconductor device, and particularly to a process for manufacturing a metal-oxide semiconductor integrated circuit (hereinafter abbreviated as MO3LSI). It is.
従来の技術
従来例を第2図に沿って説明する。例えばp型(100
)10〜15Ω・口のシリコン基板1上に選択酸化法等
を用いてフィールド酸化膜2を形成する。次にトランジ
スタの特性を決めるゲート酸化膜3、不純物ドープ多結
晶シリコン電極4を各々、電気炉、減圧化学気相堆積法
を用いて成長させると共に、写真蝕刻法により望みのゲ
ート電極パターン4を形成する。この多結晶シリコンに
セルフ7ライン法で、例えば砒素を加速電圧80 Ke
V程度で5〜e x 1015/ail程度イオン注入
を実施し、活性化する事によってソース5あるいはド、
レイン5を形成する。次に化学気相堆積法等で酸化硅素
膜6、及び燐やホウ素を各々個別に入れる場合は約7〜
10%、同時に入れる場合は各4〜6チ程度含ませた酸
化硅素膜8(以下ボロン・燐ガラス層と略す)を成長さ
せる。Prior Art A conventional example will be explained with reference to FIG. For example, p-type (100
) A field oxide film 2 is formed on a silicon substrate 1 of 10 to 15 Ω by using a selective oxidation method or the like. Next, a gate oxide film 3, which determines the characteristics of the transistor, and an impurity-doped polycrystalline silicon electrode 4 are grown using an electric furnace and low pressure chemical vapor deposition, and a desired gate electrode pattern 4 is formed using photolithography. do. For example, arsenic is applied to this polycrystalline silicon using the self-seven line method at an accelerating voltage of 80 Ke.
By performing ion implantation of about 5 to ex 1015/ail at about V and activating it, the source 5 or
Form rain 5. Next, if silicon oxide film 6 and phosphorus and boron are each added individually by chemical vapor deposition method, approximately 7~
A silicon oxide film 8 (hereinafter abbreviated as a boron/phosphorus glass layer) containing about 10% of the silicon oxide film 8 (hereinafter abbreviated as boron/phosphorus glass layer) is grown.
このプロセスで、酸化硅素膜6を成長させた理由は、下
地のソースあるいはドレイン5に上段のボロン燐ガラス
層8よりボロンもしくは燐が不純物として導入されるの
を防ぐ為である。本説明図はNチャネルMOSトランジ
スタの場合なので、燐が入っても良いが、例えばPチャ
ネルトランジスタの共存するCMOSプロセス等では必
らず必要である。さて、このように層8よシなる層間絶
縁膜を形成させた後、1000℃で20分程度、水蒸気
雰囲気中で加熱処理を行なう。すると、最上層のボロン
燐ガラス8が第2図fC)に示すように、固体であシな
がら流動性を示し、第2図(b)のようなほぼ垂直に近
い被覆形状から、かなりの傾斜角度を有する層8よりな
る層間絶縁膜が形成される。The reason why the silicon oxide film 6 is grown in this process is to prevent boron or phosphorus from being introduced as an impurity into the underlying source or drain 5 from the upper boron phosphorus glass layer 8. This explanatory diagram shows the case of an N-channel MOS transistor, so phosphorus may be included, but it is absolutely necessary, for example, in a CMOS process where a P-channel transistor coexists. After forming an interlayer insulating film such as layer 8 in this manner, heat treatment is performed at 1000° C. for about 20 minutes in a steam atmosphere. Then, as shown in Fig. 2 (fC), the top layer of boron phosphorus glass 8 exhibits fluidity even though it is solid, and changes from the almost vertical coating shape shown in Fig. 2 (b) to a considerable slope. An interlayer insulating film consisting of layers 8 having an angle is formed.
従って例えば多結晶シリコン4上の段差部が非常に平滑
になり、層間絶縁膜8上に形成される金属配線層(図示
せず)も下地の形状を反映して滑らかになる事が予測さ
れる。Therefore, for example, it is predicted that the stepped portion on the polycrystalline silicon 4 will become extremely smooth, and that the metal wiring layer (not shown) formed on the interlayer insulating film 8 will also become smooth, reflecting the shape of the underlying layer. .
これがいわゆる燐ガラスフローと称されるものであって
急激な段差の軽減の為、非常に広く用いられる。そして
平滑性が良いのは、水蒸気雰囲気中が最も良く、単なる
窒素雰囲気ではなかなかガラスの流動性が生じない。This is called phosphorous glass flow, and it is very widely used to reduce sudden steps. Smoothness is best in a water vapor atmosphere, and glass fluidity does not easily occur in a simple nitrogen atmosphere.
現在は燐ガラスを1000℃以上の高温で燐を含んだ雰
囲気中で処理する事が多く、よシ低温でもその流動性を
生かす為、前述のようにホウ素をも含んだボロン燐ガラ
ス層の利用が検討されつつある。Currently, phosphorus glass is often processed in an atmosphere containing phosphorus at high temperatures of over 1000°C, and in order to take advantage of its fluidity even at much lower temperatures, a layer of boron-phosphorus glass that also contains boron is used as mentioned above. is being considered.
発明が解決しようとする問題点
前述のようにリンガラス層、あるいはボロン燐ガラス層
に流動性を持たせる雰囲気としては水蒸気雰囲気が望ま
しいと述べたが、その熱処理時に第2図(C)に示すよ
うに、層間絶縁膜6,8を通して酸化種が下地基板にま
で到達し、ゲート多結晶シリコンのエッヂでの持ち上が
り部4Aや、ソースドレイン部の酸化部5Aの形成によ
るソースドレイン抵抗の増加といった2点の問題が生じ
ている。これらは素子寸法が大きい間は特に大きな問題
ではなかったが、微細化が進むにつれ、その制御性の困
難さや特性の劣化が顕著になりつつある。Problems to be Solved by the Invention As mentioned above, it was stated that a steam atmosphere is preferable as the atmosphere for imparting fluidity to the phosphorus glass layer or the boron phosphorus glass layer, but during heat treatment, the atmosphere shown in FIG. 2 (C) As shown in FIG. 2, oxidized species reach the underlying substrate through the interlayer insulating films 6 and 8, resulting in two problems such as an increase in source-drain resistance due to the formation of a raised part 4A at the edge of the gate polycrystalline silicon and an oxidized part 5A in the source-drain part. A problem has arisen. These problems were not a particularly big problem while the device size was large, but as the device size becomes smaller, the difficulty in controllability and the deterioration of characteristics are becoming more noticeable.
層間絶縁膜は通常6 、000〜1μmと非常に厚いが
堆積時の温度が約400℃と低く、水蒸気酸化種に対し
ては何らストップ効果を持たないようである。更に、ソ
ースドレイン層は高濃度の不純物層であり不純物の入ら
ない場合に比べ、酸化速度が非常に早くなる事は良く知
られており、又、特に水蒸気酸化の場合、特に、その相
対的な成長速度が早い為、上述のような問題点が生じる
ものと理解される。The interlayer insulating film is usually very thick, 6,000 to 1 μm, but the temperature during deposition is as low as about 400° C., and it does not seem to have any stopping effect on water vapor oxidation species. Furthermore, it is well known that the source/drain layer is a highly concentrated impurity layer, and the oxidation rate is much faster than in the case of no impurities. It is understood that the above-mentioned problems arise because the growth rate is fast.
問題点を解決するための手段
本発明の方法は、ゲート電極とソース及びドレイン構造
を有するMOS集積回路の製造するに際し、半導体基体
一主面上にゲート電極、ソース、ドレインを各々形成し
た後前記ゲート電極、ソース及びドレインと接続される
金属配線層との層間絶縁膜を形成し、酸化硅素膜を化学
気相堆積法で形成する工程と、この膜上に多結晶シリコ
ン膜を堆積する工程と、ボロン及びリンを個別もしくは
同時に含む酸化硅素膜を堆積する工程と、前記半導体基
体をsoo’c以上かつ水蒸気雰囲気中で熱処理する工
程とからなり、前記多結晶シリコン膜を全て酸化膜に変
えるものである。Means for Solving the Problems The method of the present invention, when manufacturing a MOS integrated circuit having a gate electrode, a source, and a drain structure, involves forming the gate electrode, source, and drain on one main surface of a semiconductor substrate, and then performing the steps described above. A step of forming an interlayer insulating film with a metal wiring layer connected to the gate electrode, source and drain, and forming a silicon oxide film by chemical vapor deposition, and a step of depositing a polycrystalline silicon film on this film. , a step of depositing a silicon oxide film containing boron and phosphorus individually or simultaneously, and a step of heat-treating the semiconductor substrate at a temperature above soo'c in a water vapor atmosphere, and converting the polycrystalline silicon film into an oxide film entirely. It is.
作 用
ボロン燐ガラス層の下に多結晶シリコン膜を敷いておく
事によって、酸化種は下地に到達する前に、先ずこの多
結晶シリコン層の酸化に費され、しかも、その結果、形
成される膜は酸化硅素膜である為、層間絶縁膜は全て、
同種の膜であシ、次工程のコンタクトホールのエツチン
グ等に何ら支障をきたさない。Function By placing a polycrystalline silicon film under the boron phosphorus glass layer, the oxidizing species are first spent oxidizing this polycrystalline silicon layer before reaching the underlying layer, and as a result, the oxidation species are formed. Since the film is a silicon oxide film, all interlayer insulation films are
Since the film is of the same type, it will not cause any problems in the next process such as etching of contact holes.
実施例 本発明の実施例を第1図に沿って説明する。Example An embodiment of the present invention will be described with reference to FIG.
MOS)ランジスタのソースドレインを形成するまでは
従来法と同様で良い。次にやはりボロン燐ガラス層から
の不純物汚染を防ぐ為に化学気相堆積法あるいは低重ド
ライ酸化法で、ソースドレイン部の抵抗値があがったシ
、多結晶シリコンゲートエッヂが持ち上がらない程度に
酸化硅素膜6を形成する。次に多結晶シリコン7を、後
述のボロン燐ガラス層の水蒸気によるフロー処理を行な
うのに必要な時間の間に多結晶シリコンが酸化される酸
化膜厚の半分より若干少な目の厚みに減圧化学気相堆積
法等で成長させる。例えば900℃。The method may be the same as the conventional method until the source/drain of the MOS transistor is formed. Next, in order to prevent impurity contamination from the boron phosphorus glass layer, chemical vapor deposition or low-intensity dry oxidation is used to oxidize the polycrystalline silicon to an extent that increases the resistance value of the source/drain region and does not lift the polycrystalline silicon gate edge. A silicon film 6 is formed. The polycrystalline silicon 7 is then heated in a vacuum chemical vaporizer to a thickness slightly less than half the oxide thickness that the polycrystalline silicon will be oxidized during the time required to carry out the water vapor flow treatment of the boron phosphorous glass layer described below. Grow by phase deposition method etc. For example, 900℃.
60分の水蒸気フロー処理を行なうなら、700人程鹿
の膜厚が望ましい。その後ボロン燐ガラス層8を500
0〜9000人程度の膜厚で堆積する。If a steam flow treatment is performed for 60 minutes, a film thickness of about 700 deer is desirable. After that, add 500% of boron phosphorus glass layer 8.
It is deposited with a film thickness of about 0 to 9000.
これを第2図(b)に示す。次に水蒸気雰囲気中で、8
00℃以上の高温たとえば8oO〜1ooO℃の温度で
、高温なら15〜30分、低温なら60〜180分熱処
理を行なう。すると表面のボロン燐ガラス層8が流動性
を示し、多結晶シリコン7は全て酸化膜となると同時に
第1図(C)に示すように表面が平滑になる。This is shown in FIG. 2(b). Next, in a steam atmosphere, 8
Heat treatment is carried out at a high temperature of 00° C. or higher, for example, 80° C. to 100° C., for 15 to 30 minutes at a high temperature and 60 to 180 minutes at a low temperature. Then, the boron phosphorus glass layer 8 on the surface exhibits fluidity, and the entire polycrystalline silicon 7 becomes an oxide film, and at the same time, the surface becomes smooth as shown in FIG. 1(C).
発明の効果
本発明の方法によれば、表面が平滑になると共に、下地
のソースドレイン領域が酸化される事なく、又、多結晶
シリコンエッヂの端部が持ち上がる事が生じない。後の
工程として、層間絶縁膜にコンタクトホールを形成し、
下地と接続する為の金属配線形成があるが、その際の段
差部での断線あるいは異方性エッチによる段差部でのエ
ツチング残りが見られない等の利点を持っている。Effects of the Invention According to the method of the present invention, the surface becomes smooth, the underlying source/drain regions are not oxidized, and the edges of the polycrystalline silicon edges are not lifted. As a later step, a contact hole is formed in the interlayer insulating film,
Metal wiring is formed to connect to the underlying layer, but it has the advantage that there is no disconnection at the stepped portion or etching residue at the stepped portion due to anisotropic etching.
第1図は本発明の一実施例における半導体装置の製造方
法を示す工程断面図、第2図は従来の製造方法を示す工
程断面図である。
6・・・・・・酸化硅素膜、7・・・・・・多結晶シリ
コン、8・・・・・・ボロン燐ガラス層。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名4・
−96晶シソコン1−不を
第 2 図FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process sectional view showing a conventional manufacturing method. 6...Silicon oxide film, 7...Polycrystalline silicon, 8...Boron phosphorus glass layer. Name of agent: Patent attorney Toshio Nakao and 1 other person 4.
-96 Crystal Sisocon 1-Fu Figure 2
Claims (1)
積回路の製造に際し、半導体基体一主面上にゲート電極
、ソース、ドレインを各々形成した後前記ゲート電極、
ソース及びドレインと接続される金属配線層との層間絶
縁膜を形成し、酸化硅素膜を化学気相堆積法で形成する
工程と、多結晶シリコン膜を堆積する工程と、ボロン及
びリンを個別もしくは同時に含む酸化硅素膜を堆積する
工程と、前記半導体基体を800℃以上かつ水蒸気雰囲
気中で熱処理する工程とからなり、前記多結晶シリコン
膜を全て酸化膜に変えるようにしてなる半導体装置の製
造方法。When manufacturing a MOS integrated circuit having a gate electrode, a source, and a drain structure, after each of the gate electrode, source, and drain is formed on one main surface of a semiconductor substrate, the gate electrode,
A step of forming an interlayer insulating film with a metal wiring layer connected to the source and drain, a step of forming a silicon oxide film by chemical vapor deposition, a step of depositing a polycrystalline silicon film, and a step of depositing boron and phosphorus separately or A method for manufacturing a semiconductor device, comprising simultaneously depositing a silicon oxide film and heat-treating the semiconductor substrate at a temperature of 800° C. or higher in a steam atmosphere, thereby converting all of the polycrystalline silicon film into an oxide film. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13951786A JPS62296473A (en) | 1986-06-16 | 1986-06-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13951786A JPS62296473A (en) | 1986-06-16 | 1986-06-16 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62296473A true JPS62296473A (en) | 1987-12-23 |
Family
ID=15247136
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13951786A Pending JPS62296473A (en) | 1986-06-16 | 1986-06-16 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62296473A (en) |
-
1986
- 1986-06-16 JP JP13951786A patent/JPS62296473A/en active Pending
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