JPS62165365A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent oxidation and improve electrical characteristics of a device and improve the reliability by levelling the wiring by a method wherein a layer insulating film has a triple-layer structure composed of a silicon oxide film, a silicon nitride film and an impurity doped silica glass film laminated in this order from the lower layer to the upper layer. CONSTITUTION:After a gate silicon oxide film 2 is made to grow on a P-type single crystal silicon substrate 1, a phosphorus doped polycrystalline silicon film 3 is made to grow on the film 2 and further a tungsten silicide film 4, as a high melting point metal silicide, is made to grow on the film 3. After that a gate electrode of a double-layer structure is formed by patterning. Then arsenic ions are implanted into the silicon substrate 1 as an N-type impurity to form source and drain regions 6 and 6. A silicon oxide film 7 is made to grow on the regions 6 and 6 and a silicon nitride film 8 is formed on the oxide film 7 and further a BPSG film 9 containing boron and phosphorus is formed on the film 8 to form a layer insulating film 10 of a triple-layer structure. the layer insulating film 10 is subjected to a heat treatment in a stream atmosphere and the BPSG film 9 which is the top layer is made to reflow to relieve its stepped parts.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having an insulated gate field effect transistor, and particularly to a semiconductor device having an improved interlayer insulating film.

[Conventional technology]

Generally, in a semiconductor device, an interlayer insulating film is provided to insulate between an element formed on a semiconductor substrate and an upper layer wiring formed on the second side. For example, in a semiconductor device having an insulated gate field effect transistor (hereinafter referred to as a Mis transistor) as an element, an interlayer insulating film is formed to cover the underlying gate electrode and source/drain regions, and on top of this an interlayer insulating film is formed. It is intended to be insulated from the two-layer wiring installed.

Conventionally, this type of interlayer insulating film has been made of silicon oxide film or phosphorous-containing silica glass (PS), which can be reflowed at relatively low temperatures.
G) or silica glass containing phosphorus and poron (B P
SG) is used, in which a silicon oxide film is deposited on the gate I/electrode and source/drain regions of the MIS transistor, and then a film such as PSG or BPSG is deposited. In this interlayer insulating film, after the film is formed, it is heated and reflowed to alleviate the step difference caused by the lower layer gate electrode and lower layer wiring, and prevent the upper layer wiring from being disconnected at the step part. .

Generally, these PSG and BF'SG can be reflowed at a low temperature, but they can be reflowed at a lower temperature in a steam atmosphere than in a non-oxidizing atmosphere such as nitrogen or argon. Therefore, in recent years, where shallow junctions in source and drain regions are required due to miniaturization of devices, glue flow is often performed in a steam atmosphere that allows processing at low temperatures.

[Problem that the invention seeks to solve]

In the conventional semiconductor device described above, a silicon oxide film and a PS
Since the interlayer insulating film made of G or BPSG is reflowed in a steam atmosphere, the gate electrode and source/drain regions under the interlayer insulating film, which have no oxidation resistance, are oxidized. Therefore, if the gate electrode or source/drain regions are excessively oxidized, the shape of the gate electrode may be deformed and the electrical characteristics may be deteriorated. Particularly, in the case of a fine M■S transistor whose gate length is shortened, deterioration of characteristics due to deformation of the gate electrode becomes remarkable.

In addition, if the gate electrode is made of a material containing a high-melting point metal or a high-melting point metal silicide, the high-melting point metal may be sublimated by oxidation, resulting in significant deformation of the shape, or the layer resistance of the high-melting point metal silicide may There is also the problem of an increase in

[Means for solving problems]

The semiconductor device of the present invention makes it possible to reflow only the interlayer insulating film in a steam atmosphere without oxidizing the gate electrode or source/drain region of the MIS transistor, thereby preventing deterioration of the characteristics of the device and preventing disconnection in the upper layer wiring. This effectively prevents

The semiconductor device of the present invention has an interlayer insulating film formed on the gate electrode and source/drain regions of the MIS transistor.
It has a three-layer structure in which a silicon oxide film, a silicon nitride film, and a silica glass film containing impurities are laminated in order from the bottom layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

The figure is a sectional view of one embodiment of the present invention, and here shows an example applied to an N-channel MIS+- transistor.

That is, a gate silicon oxide film 2 with a thickness of 300 nm is grown on a P-type crystal silicon substrate 1''2 by thermal oxidation.
On top of this, phosphorus-added polycrystalline silicon film 3 is deposited at 200°C.
Further, a tungsten silicide film 4, which is a refractory metal silicide, is grown on this film to a thickness of 2,000 nm by CVD or spacing. Thereafter, these are patterned into a desired shape using photolithography technology 7 to form a gate electrode 5 having a two-layer structure called polycide.

Then, by a self-alignment method using this gate electrode 5, arsenic, which is an N-type impurity, is ionized into the silicon substrate 1 to form a source/drain region 6.6.

On top of this, a silicon oxide film 7 is deposited by a normal CVD method.
A silicon nitride film 8 is deposited on top of the silicon nitride film to a thickness of 500 mm.
Then, a BPSG film 9 containing 4 weight percent of boron and phosphorous each is grown to a thickness of 1 μm to form an interlayer insulating film 10 having a three-layer structure. Then, heat treatment is performed on this interlayer insulating film 10 in a steam atmosphere at 900° C. for 20 minutes, and the uppermost layer B P S
The G film 9 is reflowed to soften the stepped portion.

Incidentally, after that, the MIS transistor is completed by opening contact holes and forming two-layer wiring, but these are omitted from illustration here.

According to this configuration, the B P S GI of the interlayer insulating film 10
Since the oxidation-resistant silicon nitride film 8 is interposed between the Ix 9 and the silicon oxide film 7, even if the BPSG film 9 is reflowed in a steam atmosphere, this silicon nitride film 8 functions as a barrier. Lower layer silicon oxide film7. The gate electrode 5 and source/drain regions 6 are not affected by oxidation.

For this reason, the tungsten silicide lI! that constitutes the gate electrode 5. It is possible to prevent oxidation of the polycrystalline silicon film 4, thereby preventing problems such as an increase in layer resistance and peeling off from the polycrystalline silicon film 3. This improves the electrical characteristics of the M I S +- transistor, and also improves the reliability of the upper layer wiring by flattening the interlayer insulating film.

Here, in the above embodiment, an N-channel MIS transistor was illustrated, but the present invention can be similarly applied to a P-channel MIS transistor. Furthermore, it is also possible to use a PSG film as the uppermost layer of the interlayer insulating film.

〔Effect of the invention〕

As explained above, the present invention has a three-layer structure in which the interlayer insulating film formed on the gate electrode and source/drain regions is laminated in order from the bottom: a silicon oxide film, a silicon nitride film, and a silica glass film containing impurities. Therefore, even if the interlayer insulating film is reflowed in a steam atmosphere, the oxidation resistance of the silicon nitride film will prevent the gate electrode, source and
The influence of oxidation on the drain region can be prevented, and by preventing such oxidation, it is possible to improve the electrical characteristics of the element and improve reliability by flattening the wiring. In addition, by realizing glue flow in a steam atmosphere, source
It is possible to form a shallow junction in the drain region, thereby making it possible to shorten the channel of the element and achieve high integration of the semiconductor device.

[Brief explanation of drawings]

The figure is a cross-sectional view of essential parts of an embodiment of the present invention. 1... Solicon base, 2... Gate oxide film, 3...
- Polycrystalline silicon film, 4... Tungsten silicide film, 5... Gate electrode, 6... Source/drain region, 7... Silicon oxide film, 8... Silicon nitride film, 9... BPSG film, 10... interlayer insulating film.

Claims (2)

[Claims] (1) In a semiconductor device including an insulated gate field effect transistor, an interlayer insulating film formed on the gate electrode and source/drain regions of the insulated gate field effect transistor is sequentially formed from a silicon oxide film, a silicon nitride film, and a silicon nitride film from the bottom. A semiconductor device characterized in that it has a three-layer structure in which silica glass films containing impurities are laminated. (2) The semiconductor device according to claim 1, wherein the gate electrode has a polycide structure consisting of two layers of a polycrystalline silicon film and a high melting point metal silicide film.