JP3104322B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MOS field effect transistor having a self-aligned silicide structure.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor devices, especially MOS
In a transistor, a shallow junction of a source / drain diffusion layer is required for a short channel. However, as the junction depth becomes shallower, the increase in layer resistance is a major factor limiting the performance of the device. As a method for solving this problem, titanium (Ti), cobalt (Co), and tantalum (T
Structures that form metal silicide (silicide) such as a) and thereby reduce the resistance of the diffusion layer have begun to be adopted.

This structure is, for example, as shown in FIG.
A polycrystalline silicon gate electrode 4 is formed on a P-type silicon substrate 1 in an active region separated by a field oxide film 2 with a gate oxide film 3 interposed therebetween. Are formed. N ^- layer 17
For example, a titanium silicide (TiSi ₂ ) layer 9 is formed on the source / drain constituted by the N ⁺ layer 18. At this time, a titanium silicide layer 9a is also formed on the surface of polycrystalline silicon 4 of the gate electrode. The method of forming the self-aligned silicide layer 9 is described in, for example, IEE, Transaction of Electron Devices, Vol.
985), M. Alperin, el.
al. , IEEE Transaction of E
Electron Devices, vol. ED-3
2, p 141, 1985). The layer resistance of the self-aligned silicide layer 9 described above shows a low layer resistance of several Ω / □, and it is possible to avoid an increase in diffusion layer resistance due to a shallow junction.

[0004]

By the way, miniaturization of metal wiring is also important for miniaturization of semiconductor devices. In order to realize high-density fine wiring, it is necessary to reduce unevenness on the surface of the substrate as much as possible and to prevent disconnection of wiring at a step portion, short-circuit between wirings, and the like. Conventionally, PSG is used as an interlayer insulating film between a gate electrode and a metal wiring.
Alternatively, a heat-meltable insulating film such as BPSG is used, and this film is heat-treated at a high temperature of 900 ° C. to 1000 ° C. and reflowed to planarize the substrate surface.
However, in the above-described structure in which the metal silicide layer is formed on the source / drain surfaces, in this high-temperature reflow step, boron (B), which is a dopant impurity of the source / drain diffusion layer, particularly the P ⁺ diffusion layer, is solidified in the silicide. Since the solubility is remarkably high, it re-diffuses from the silicon side into the silicide layer, and the boron concentration at the silicide / silicon interface decreases. For this reason, there arises a problem that the parasitic resistance at the silicide / silicon contact portion increases and the transistor characteristics deteriorate. In order to avoid the above problem, the heat treatment temperature after silicide formation may be lowered, but the reflow property of the interlayer film is reduced and the flatness is deteriorated.

[0005]

According to the present invention, there is provided a semiconductor device comprising:
CMOS transistors with self-aligned silicide layer is formed on the source and drain diffusion layer, and directly on the silicide layer of the P-channel MOS transistor B
An SG film is formed on the N-channel MOS transistor
The silicide layer is not directly covered with the BSG film .

Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor chip according to the related art of the present invention. A thick field oxide film 2 for element isolation is formed on an N-type silicon substrate 20 by a selective oxide film.
Formed to a thickness of 4 to 1.0 μm, and through a gate oxide film 3, polycrystalline silicon 4 and tungsten silicide (WSi
_X ) 5 are sequentially deposited in a thickness of about 100 to 200 nm, and a gate electrode is formed by patterning this two-layer film. On the side surface of the gate electrode, for example, a sidewall 6 of an oxide film is formed. Further, a P ⁻ layer 7 is formed in self-alignment with the gate electrode, and a P ⁺ layer 8 is formed in self alignment with the side wall. Further, the surface of the P ⁺ silicon layer forming the source and drain of the MOS transistor is formed. , A silicide layer 9 is formed. Then, the BSG film 12 is in contact with the silicide
nm and then a BPSG film 13 of 300-500
The BPSG film 13 is grown by about nm and reflowed by heat treatment.

FIG. 2 is a sectional view of a semiconductor chip showing one embodiment of the present invention. This embodiment shows a so-called complementary semiconductor device in which an N-type semiconductor layer (N-well) 10 is formed on a P-type silicon substrate 1 and MOS transistors are formed on both conductive semiconductor layers. . In the present embodiment, a gate electrode polycrystalline silicon 4 formed by patterning polycrystalline silicon through a gate oxide film 3 is formed.
An oxide film sidewall 6 is formed on the side wall of the gate electrode, and silicide layers 9a and 9 are simultaneously formed on the upper surface of the gate electrode and the surfaces of the source / drain diffusion layers. CVD on source / drain diffusion layer on N channel side
The BSG film 12 is grown via the SiO ₂ film 11, and the BSG film 12 is grown directly on the source / drain diffusion layer on the P channel side. BPSG film 13 on BSG film 12
Are deposited and reflowed.

Hereinafter, the manufacturing method of this embodiment will be described with reference to FIG. N-well region 10 on P-type silicon substrate 1
Is formed, and the field oxide film 2 for element isolation is set to 0.
A polycrystalline silicon film having a thickness of 4 to 1.0 μm is deposited via a gate oxide film 3 by a 100 to 400 nm CVD method, and this is patterned using ordinary photolithography and anisotropic etching to form a polycrystalline silicon film. Crystalline silicon 4
Is formed in the same manner as in the related art. Thereafter, as shown in FIG. 3 (a), respectively two conductive type semiconductor region by self-alignment with the gate electrode, the N-type forming region phosphorus, and boron ions are implanted in the P-forming region N ^- layer 1
7, a P ⁻ layer 7 is formed, and then a SiO ₂ film is grown on the entire surface of the substrate by a CVD method to a thickness of 100 to 300 nm. A sidewall 6 is formed on a side surface of the silicon 4.

Next, arsenic (As), boron fluoride (BF ₂ ) and the like are ion-implanted into the both conductivity type semiconductor regions to form an N ⁺ layer 18 and a P ⁺ layer 8, and then the semiconductor substrate is formed on the semiconductor substrate. Titanium (Ti) is deposited using 50 to 200 nm sputtering or the like, and is subjected to a heat treatment to cause a reaction with silicon exposed on both the source / drain diffusion layers and the polycrystalline silicon 4 to form titanium silicide (TiSi _2). ) Layer 9
a, 9 are formed. Then, unreacted Ti is selectively wet-etched to obtain the structure shown in FIG.

Next, a SiO ₂ film 1 is formed on the entire surface of the substrate by the CVD method.
3 is deposited to a thickness of 50 to 200 nm, and the N-tunnel side is masked using a photoresist 15 or the like as shown in FIG. Using this photoresist 15, the SiO ₂ film 11 on the P channel side is selectively etched. At this time, a P-type impurity such as boron (B) may be ion-implanted into the silicide layer 9 only on the P-channel side by using the photoresist 15 described above.

Next, after removing the photoresist 15,
As shown in FIG. 3D, a BSG film 12 is grown to a thickness of 100 to 300 nm over the entire surface of the substrate by a CVD method or the like. further,
A BPSG film is grown at 300 to 600 nm,
The structure shown in FIG. 2 is obtained by performing reflow at 00 ° C.

[0012]

As described above, according to the present invention, the source
In a semiconductor device having a structure in which a silicide layer is formed in a self-alignment manner on a drain diffusion layer, in a P-channel source / drain diffusion layer, BSG is directly formed on the silicide layer.
By forming a film and forming a thermally fusible interlayer insulating film on the film, B
Since boron is sufficiently supplied from the SG film to the silicide layer, redistribution of boron from the P ⁺ silicon layer is suppressed. Thereby, there is an effect that the interlayer insulating film can be flattened without deteriorating the performance of the P-channel MOS transistor.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip according to a related technique of the present invention.

FIG. 2 is a cross-sectional view of one embodiment of the present invention.

FIG. 3 is a sectional view of the manufacturing method according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 3 gate oxide film 4 polycrystalline silicon for gate electrode 7 P ⁻ layer 8 P ⁺ layer 9, 9a titanium silicide layer 12 BPSG film 20 P-type silicon substrate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/28 301 H01L 21/28 H01L 21/336

Claims (1)

(57) [Claims] An N-type semiconductor layer region and a P-type semiconductor layer are formed on a semiconductor substrate.
A semiconductor layer region; and a metal silicon layer on each of the semiconductor layer regions.
P-type source / drain diffusion with side layer formed on the surface
Semiconductor having respective N-type source / drain diffusion layers
In the semiconductor device, the metal silicide on the P-type source / drain diffusion layer
Boron silicate glass film is directly deposited on the
The metal silicide on the N-type source / drain diffusion layer.
The boron silicate glass film directly contacts the surface of the oxide layer.
A semiconductor device characterized in that it has a structure that does not.