JP3077146B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a p-type semiconductor region and an n-type semiconductor region are formed on a semiconductor substrate. It is preferable.

[Summary of the Invention]

The present invention provides an insulating device having a first opening and a second opening provided on a semiconductor substrate having a p-type semiconductor region and an n-type semiconductor region, respectively, corresponding to the p-type semiconductor region and the n-type semiconductor region. A method of manufacturing a semiconductor device, wherein a film is provided, and an aluminum-based wiring is contacted to a p-type semiconductor region in a first opening portion and an n-type semiconductor region in a second opening portion via a titanium film, respectively. ,
Forming an insulating film having a first opening and a second opening on the semiconductor substrate; and forming an n-type semiconductor region in the p-type semiconductor region and the n-type semiconductor region through the first opening and the second opening in the insulating film, respectively. A step of ion-implanting impurities at a first dose of 1 × 10 ¹² / cm ² or more and less than 1 × 10 ¹⁵ / cm ^2, and a step of implanting 1 × p-type impurities into the p-type semiconductor region through the first opening of the insulating film; 10 ¹⁴ / c
ion implantation at a second dose of at least m ^{2 and} less than 1 × 10 ¹⁷ / cm ² and at least one order of magnitude higher than the first dose, thereby providing a p-type semiconductor region through the Ti film. And n
In the case where an Al-based wiring is brought into contact with the type semiconductor region, it is possible to realize a good ohmic contact and prevent a junction leak in both the p-type semiconductor region and the n-type semiconductor region. .

[Conventional technology]

Conventionally, in a semiconductor device using aluminum (Al) -silicon (Si) wiring, in order to prevent the occurrence of defects due to so-called Al spikes, the diffusion layer at the contact portion of the Al-Si wiring has the same conductivity as this diffusion layer. A method is known in which the junction depth at this portion is increased by ion implantation of a type impurity. By the way, when the Al-Si wiring is brought into contact with Si, the height of the Schottky barrier at the interface between the Al-Si wiring and Si in this contact portion is Al-Si
The case where the Al-Si wiring is contacted with the n-type Si is higher than the case where the wiring is contacted with the p-type Si. Therefore, in order to achieve good ohmic contact,
The dose of ion implantation of impurities into the contact portion is p
It is necessary to make the n-type Si higher than the type Si. Also,
Since junction leakage is more likely to occur in n-type Si, it is necessary to increase the dose of ion implantation of impurities into the contact portion for n-type Si in order to prevent this junction leakage.

2A to 2C show a method of manufacturing a conventional CMOS LSI in which ions of impurities are implanted into a contact portion. According to this conventional manufacturing method, as shown in FIG. 2 A, initially for example n ^- after the n-well 102 and p-well 103 are formed respectively in the type Si substrate 101, the n ^- surface of the type Si substrate 101 Then, a field SiO ₂ film 104 is selectively formed to perform element isolation.
Then, after forming a gate SiO ₂ film 105 on the surface of the active region surrounded by the field SiO ₂ film 104, the gate SiO ₂
Gate electrodes 106 and 107 are formed on the film 105. Next, for example, a p-type impurity such as boron (B) is ion-implanted into the n-well 102 using the gate electrode 106 as a mask while the surface on the p-well 103 side is covered with a resist (not shown) or the like. Thus, for example, the p ⁺ type source region 108
And a train region 109 is formed in a self-aligned manner with respect to the gate electrode 106. Next, an n-type impurity such as arsenic (As) is ion-implanted into the p-well 103 using the gate electrode 107 as a mask while the surface on the n-well 102 side is covered with a resist (not shown) or the like. For example, an n ⁺ type source region 110 and a train region 111 are connected to the gate electrode 10.
7 is formed in a self-aligned manner. Next, after an interlayer insulating film 112 is formed on the entire surface, the interlayer insulating film 112 and the gate Si
A predetermined portion of the O ₂ film 105 is removed by etching to form contact holes C ₁ ′, C ₂ ′, C ₃ ′, and C ₄ ′.

Next, as shown in FIG. 2B, a p-type impurity such as B is ion-implanted over the entire surface at a dose of, for example, 10 ¹³ / cm ² . As a result, the contact holes C ₁ ′, C ₂ ′,
Through C ₃ ′ and C ₄ ′, the p ⁺ type source region 1 of the contact portion
A p-type impurity is ion-implanted into the substrate region 08, the train region 109, the n ⁺ -type source region 110, and the train region 111 (the implanted p-type impurities are indicated by white circles).

Next, as shown in FIG. 2C, after the surface on the n-well 102 side is covered with a resist pattern 113, an n-type impurity such as P is ion-implanted over the entire surface at a dose of, for example, 10 ¹⁵ / cm ^2. inject. As a result, the contact holes C ₃ ′,
An n-type impurity is ion-implanted into the n ⁺ -type source region 110 and the drain region 111 of the contact portion through C ₄ ′ (the implanted n-type impurity is indicated by a black circle). In this case, the p-type impurity previously ion-implanted is compensated by the n-type impurity thus ion-implanted. As a result, the ion-implanted n is implanted into the type ⁺ type source region 110 and the drain region 111 of the contact portion.
N in an amount corresponding to the difference in dose between the p-type impurity and the p-type impurity
The mold impurities are net doped.

Next, after removing the resist pattern 113 and performing annealing as necessary, a wiring or the like is formed to form a desired CM.
Complete OSLSI.

On the other hand, when Al-Si wiring is brought into contact with Si with the progress of miniaturization of elements, barrier metal is used because the increase in contact resistance due to the formation of so-called Si nodules at the contact part can not be ignored. Is now available. When this barrier metal is used, Si
Since it is difficult to achieve good ohmic contact between the silicon and the barrier metal, a titanium (Ti) film is often formed between Si and the barrier metal (for example, see Japanese Patent Application Laid-Open No. 61-25 / 1986).
No. 8452).

[Problems to be solved by the invention]

However, since Ti has a different work function from Al, when contacting Al-Si wiring with Si via a Ti film, p
The height of the Schottky barrier is higher when contacting with the type Si than when contacting with n-type Si. Also, junction leakage is more likely to occur when contact is made between Ti and p-type Si. For this reason, Al-
In the case where the Si wiring is brought into contact with Si, the p-type impurity is first ion-implanted at a low dose over the entire surface, and then the n-type impurity is ion-implanted only at the n-type Si at a high dose to perform compensation. With the method, p-type
There are problems such as a failure to make a good ohmic contact on the Si side and a tendency for junction leakage to occur.

Therefore, an object of the present invention is to provide a good ohmic contact for both a p-type semiconductor region and an n-type semiconductor region when an Al-based wiring is contacted to a p-type semiconductor region and an n-type semiconductor region via a Ti film. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of realizing the above and preventing a junction leak.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a semiconductor device comprising a p-type semiconductor region (8, 9) on a semiconductor substrate (1) having a p-type semiconductor region (8, 9) and an n-type semiconductor region (10, 11). An insulating film (12) having a _first opening (C ₁ , C ₂ ) and a second opening (C ₃ , C ₄ ) provided corresponding to the n-type semiconductor region (10, 11), respectively. provided, n-type semiconductor region in a portion of the p-type semiconductor region in the portion of the first opening _{(C 1, C 2) (} 8,9) and a second opening _{(C 3, C 4) (} 10,11) A method of manufacturing a semiconductor device in which an aluminum-based wiring is brought into contact with each other via a titanium film, wherein a first opening (C ₁ , C ₂ ) and a second opening (C ₃ , Forming an insulating film (12) having C ₄ ); and forming a p-type semiconductor region through the first opening (C ₁ , C ₂ ) and the second opening (C ₃ , C ₄ ) of the insulating film (12). (8,9) and n-type semiconductor region (10, 11) each n-type impurities and the 1 × 10 ¹² / cm ² or more 1 × 10 ¹⁵ / cm ² less than the first
Ion implantation at a dose amount of p, and p-type semiconductor regions (8, 9) through the _first openings (C ₁ , C ₂ ) of the insulating film (12).
Implanting a mold impurity at a ^second dose not less than 1 × 10 ¹⁴ / cm ^{2 and} less than 1 × 10 ¹⁷ / cm ² and at least one digit higher than the first dose.

Here, the dose of the ion implantation of the p-type impurity is preferably selected to be at least one order of magnitude larger than the dose of the ion implantation of the n-type impurity. Specifically, the dose of the ion implantation of the n-type impurity is selected, for example, in the range of 10 ¹² / cm ² to 10 ¹⁴ / cm ² . The dose of the ion implantation of the p-type impurity is selected, for example, in the range of 10 ¹⁴ / cm ² to 10 ¹⁶ / cm ² .

[Action]

According to the method for manufacturing a semiconductor device of the present invention configured as described above, low-concentration ion implantation of n-type impurities
N-type impurity is ion-implanted in the p-type semiconductor region (8, 9) and n-type semiconductor region (10, 11) through the opening of the insulating film _{(12) (C 1, C} 2, C 3, C 4) . Thereby, the impurity concentration of the n-type semiconductor regions (10, 11) in the contact portion increases. On the other hand, the n-type impurities implanted at low concentration into the p-type semiconductor regions (8, 9) are compensated by the p-type impurities implanted at high concentration. As a result, a sufficient amount of the p-type semiconductor region (8, 9) corresponding to the difference in dose between the p-type impurity implanted at a high concentration and the n-type impurity implanted at a low concentration is provided. The p-type impurity will be ion-implanted net. As a result, p
The impurity concentration of the type semiconductor regions (8, 9) becomes sufficiently high.

As described above, when the p-type semiconductor region (8, 9) and the n-type semiconductor region (10, 11) are brought into contact with the Al-based wiring through the Ti film, the p-type semiconductor region (8, 9) and the n-type Good ohmic contact with both the semiconductor regions (10, 11) and prevention of junction leakage can be achieved.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. This embodiment is an embodiment in which the present invention is applied to the manufacture of a CMOS LSI.

1A to 1C show a CMOS LS according to an embodiment of the present invention.
The manufacturing method of I is shown.

In the production method of CMOSLSI according to this embodiment, as shown in FIG. 1 A, first example n ^- after the n-well 2 and the p-well 3 were formed into a mold Si substrate 1, the n ^- type
By selectively thermally oxidizing the surface of the Si substrate 1, a field SiO ₂ film 4 is formed to perform element isolation. Next, a gate SiO ₂ film 5 is formed on the surface of the active region surrounded by the field SiO ₂ film 4 by a thermal oxidation method. Next, for example, CVD
A polycrystalline Si film is formed on the entire surface by a method, and an impurity such as P is doped into the polycrystalline Si film by ion implantation or the like to reduce the resistance, and then the polycrystalline Si film is formed into a predetermined shape by etching. The gate electrodes 6 and 7 are formed by patterning. As a material for the gate electrodes 6 and 7, a polycide film in which a refractory metal silicide film such as a tungsten silicide (WSi ₂ ) film is stacked on a polycrystalline Si film doped with an impurity may be used. it can.
When a polycide film is used as a material for the gate electrodes 6 and 7 as described above, a refractory metal silicide film is formed on an impurity-doped polycrystalline Si film, and then the refractory metal silicide film and the polycrystalline Si film are formed. Gate electrodes 6 and 7 are formed by patterning the film. Next, for example, a p-type impurity such as B is ion-implanted into the n-well 2 using the gate electrode 6 as a mask while the surface on the p-well 3 side is covered with a resist (not shown) or the like. After the p ⁺ -type source region 8 and the drain region 9 are formed in a self-aligned manner with respect to the gate electrode 6, the gate electrode 7 is formed while the surface on the n-well 2 side is covered with a resist or the like.
By ion-implanting an n-type impurity such as As into the p-well 3 using the mask as a mask, for example, an n ⁺ -type source region 10 and a drain region 11 are formed in a self-aligned manner with respect to the gate electrode 7. Next, after an interlayer insulating film 12 such as a phosphor silicate glass (PSG) film is formed on the entire surface by, eg, CVD, the interlayer insulating film 12 and the gate SiO _{2 are formed.}
A predetermined portion of the film 5 is removed by etching to form a contact hole.
Form C ₁ , C ₂ , C ₃ , C ₄ .

Next, as shown in FIG. 1B, ions are implanted into the entire surface with an n-type impurity such as P at a dose of, for example, 10 ¹³ / cm ² . As a result, the contact holes C ₁ , C ₂ , C ₃ , C ₄
Through the contact portion, the p ⁺ -type source region 8 and the drain region 9 and the n ⁺ -type source region 10 and the drain region
In FIG. 11, n-type impurities are ion-implanted at a low concentration (the implanted n-type impurities are indicated by black circles).

Next, as shown in FIG. 1C, after covering the surface on the p-well 3 side with a resist pattern 13, a p-type impurity such as B is injected at a higher dose than the ion implantation of the n-type impurity. For example, ion implantation is performed on the entire surface at about 10 ¹⁵ / cm ² . As a result, p ⁺ -type impurities are ion-implanted at a high concentration into the p ⁺ -type source region 8 and the drain region 9 of the contact portion through the contact holes C ₁ and C ₂ (the implanted p-type impurities are indicated by black circles). ). In this case, the p-type impurity thus ion-implanted causes
The mold impurities are compensated. As a result, the p ⁺ -type source region 8 and the drain region 9 of the contact portion correspond to the difference in dose between the p-type impurity implanted at a high concentration and the n-type impurity implanted at a low concentration. This means that a sufficient amount of p-type impurities has been doped net.

Next, after removing the resist pattern 13, annealing is performed as necessary. Next, for example, a Ti film, a titanium oxynitride (TiON) film, and an Al-Si film are sequentially formed on the entire surface by, for example, an evaporation method, and then these Al-Si films, TION
The film and Ti film are patterned by etching, and p ⁺
A wiring (not shown) is formed to contact the source region 8 and the drain region 9 of the n type and the source region 10 and the drain region 11 of the n ⁺ type. With this, the target CMOSLS
I is completed.

As described above, according to this embodiment, when ion implantation of impurities into the contact portion is performed, first, n-type impurities are ion-implanted at low concentration over the entire surface without using a mask.
Since a p-type impurity is ion-implanted at a high concentration only in the p-type ⁺ source region 8 and the drain region 9 using a mask, the n-type ⁺ source region 10 and the drain region 11 in the contact portion are, of course, The impurity concentration of the p-type ⁺ type source region 8 and the drain region 9 of the contact portion can also be sufficiently increased. Accordingly, when the Al-Si wiring is brought into contact with the p ⁺ -type source region 8 and the drain region 9 and the n-type ⁺ source region 10 and the drain region 11 via the Ti film, the p ⁺ -type source region Good ohmic contact and prevention of junction leak can be achieved for all of the drain region 8 and the drain region 9 and the n ⁺ -type source region 10 and the drain region 11. As a result, the reliability of the CMOS LSI can be improved.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible.

For example, in the above embodiment, the present invention
Although the description has been given of the case where the present invention is applied to the production of
For example, the present invention can be applied to the manufacture of a bipolar CMOS LSI or a bipolar LSI. More specifically, for example, in the case of a bipolar LSI, the conductivity type of the emitter region, the collector region, and the base region are different from each other. Therefore, the present invention is applied to the case where an Al-based wiring is contacted to these via a Ti film. It is possible to apply.

〔The invention's effect〕

Since the present invention is configured as described above, both the p-type semiconductor region and the n-type semiconductor region in the contact portion have a high impurity concentration, and therefore, the p-type semiconductor region and the n-type When an Al-based wiring is brought into contact with the semiconductor region, it is possible to achieve good ohmic contact and prevent junction leakage in both the p-type semiconductor region and the n-type semiconductor region.

[Brief description of the drawings]

1A to 1C show a CMOS LSI according to an embodiment of the present invention.
2A to 2C are cross-sectional views showing a method of manufacturing the semiconductor device in the order of steps.
Is a sectional view showing a conventional CMOS LSI manufacturing method in the order of process steps. Explanation of main symbols in the drawings 2: n well, 3: p well, 4: field SiO ₂ film, 6, 7: gate electrode, 8, 10: source region, 9, 11: drain region, 12: interlayer insulating film , C ₁ , C ₂ , C ₃ , C ₄ : contact holes.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/092 H01L 21/8238 H01L 21/28

Claims (1)

(57) [Claims] 1. A first opening and a second opening provided on a semiconductor substrate having a p-type semiconductor region and an n-type semiconductor region, respectively, corresponding to the p-type semiconductor region and the n-type semiconductor region. A semiconductor film provided with an insulating film having an aluminum-based wiring through a titanium film to the p-type semiconductor region in the first opening portion and the n-type semiconductor region in the second opening portion via a titanium film, respectively. A method of manufacturing the device, comprising: forming the insulating film having the first opening and the second opening on the semiconductor substrate; and forming the insulating film through the first opening and the second opening of the insulating film. Each of the p-type semiconductor region and the n-type semiconductor region has n
Implanting a p-type impurity at a first dose of 1 × 10 ¹² / cm ² or more and less than 1 × 10 ¹⁵ / cm ^2, and p-type impurities into the p-type semiconductor region through the first opening of the insulating film. Implanting impurities at a ^second dose of 1 × 10 ¹⁴ / cm ² or more and less than 1 × 10 ¹⁷ / cm ² and one digit or more higher than the first dose. Semiconductor device manufacturing method.