JPH02140927A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02140927A JPH02140927A JP29507888A JP29507888A JPH02140927A JP H02140927 A JPH02140927 A JP H02140927A JP 29507888 A JP29507888 A JP 29507888A JP 29507888 A JP29507888 A JP 29507888A JP H02140927 A JPH02140927 A JP H02140927A
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- insulating film
- peeling
- resist
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000001312 dry etching Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims 1
- 229920000642 polymer Polymers 0.000 abstract description 9
- 239000011229 interlayer Substances 0.000 abstract description 5
- 238000002161 passivation Methods 0.000 abstract description 5
- 238000011109 contamination Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 2
- 230000007774 longterm Effects 0.000 abstract description 2
- 230000000873 masking effect Effects 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000001947 vapour-phase growth Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野1
本発明は、半導体装置の製造方法に関し、特にドライエ
ツチングにより形成された金属配線上の絶縁膜成長に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a method for manufacturing a semiconductor device, and particularly to the growth of an insulating film on metal wiring formed by dry etching.
従来1例えば多層配線構造を持った半導体装置の製造方
法は、第2図の如<、トランジスタや抵抗等の半導体素
子が作り込まれた半導体基板21上の第1及び第2のフ
ィールド酸化1!22.23を介して、素子からの電極
取り出しの為にコンタクトホールを開孔した後、第1の
金属配線24となるAI2合金をスパッタリングし、フ
ォトレジスト25により所望形状にパターニングする(
第2図(a))、金属配線24は、微細化に伴いエレク
トロマイグレーション特性改@等の為、Ar1やAl1
−3tにCuを添加させている。次にフォトレジスト2
5をマスクにして、 (1!、やBcI2aのようなハ
ロゲン系ガスを用いて反応性イオンエツチャー(RI
E)や電子サイクロトロン共鳴型エツチャー(ECR)
によりドライエツチング後、変質したフォトレジストを
02プラズマによって剥離後、フォトレジストの残査や
ポリマーが残るのでフェノール系の剥m’t(12で処
理し水洗。Conventional method 1 For example, a method for manufacturing a semiconductor device having a multilayer wiring structure is as shown in FIG. After forming a contact hole through 22 and 23 to take out an electrode from the element, an AI2 alloy that will become the first metal wiring 24 is sputtered and patterned into a desired shape using a photoresist 25 (
In Fig. 2(a)), the metal wiring 24 is made of Ar1 or Al1 due to the electromigration characteristics changing due to miniaturization.
-3t is added with Cu. Next, photoresist 2
Using 5 as a mask, perform reactive ion etching (RI) using a halogen gas such as (1!, or BcI2a).
E) and electron cyclotron resonance etcher (ECR)
After dry etching and stripping the altered photoresist with 02 plasma, the photoresist residue and polymer remained, so it was treated with phenol-based stripper (12) and washed with water.
乾燥しているが、更にCl gによるCuのコロ−ジョ
ンを防ぐ為には0.プラズマ剥離後置−チャンバー、同
一装置内で02にCF、、CHF、の様なフレオン系の
ガスを混入しプラズマ中でポリマー26を故意に付着さ
せてやり、フェノール系のレジスト剥離液で処理して水
洗、乾燥するまでに大気中でコロ−ジョンを発生させな
いようにしている(第2図(b))、続いて層間絶縁膜
24として、450℃以下の低温でSiHイと02ある
いはN、Oガスを減圧化で気相反応させシリコン酸化膜
を形成する1次に第1の金属配線24の殺差部を平坦化
する為塗布ガラス膜28を被着し、アニール後フォトエ
ツチングによりスルホールを開孔し、第2の金属配線2
9となるAR金合金スパッタリングした後(第2図(C
))、第1の金属配線24と同様の方法により第2の金
属配線29をフォトエツチングしてから気相成長による
パシベーション膜を積層し、外部電極取り出し用のパッ
ド部を開孔している。It is dry, but in order to further prevent Cu corrosion due to Clg, 0. Plasma stripping post-chamber, Freon gas such as CF, CHF, etc. is mixed into 02 in the same apparatus, and polymer 26 is intentionally deposited in the plasma, and then treated with a phenolic resist stripper. The interlayer insulating film 24 is then coated with SiH, 02 or N, at a low temperature of 450°C or less, to prevent corrosion from occurring in the air before being washed and dried (Fig. 2 (b)). A silicon oxide film is formed by a gas phase reaction of O gas under reduced pressure.First, a coated glass film 28 is applied to flatten the dead-edge portion of the first metal wiring 24, and after annealing, through holes are formed by photo-etching. A hole is opened and the second metal wiring 2
After AR gold alloy sputtering to give 9 (Fig. 2 (C)
)) The second metal wiring 29 is photo-etched using the same method as the first metal wiring 24, and then a passivation film is deposited by vapor phase growth, and a pad portion for taking out an external electrode is opened.
〔発明が解決しようとする課題1
しかしながら従来技術では、金属配線24゜29のドラ
イエンチング後に残るポリマー26を、フェノール系の
レジスト剥1fif液で完全に除去するのは難しく、特
に段差側面や溝部には残査が多く残る。この上に形成さ
れる層間膜やパシベーション膜とする例えば、塗布膜や
気相成長シリコン酸化膜、シリコン窒化膜の密着が悪く
、成長直後や後工程のストレス等で剥離やクラックが発
生していた。またコンタミネーションに依る信頼性にも
悪影響を及ぼし、更にホール抵抗も高くなるなどの再現
性が悪かった。[Problem to be Solved by the Invention 1] However, with the prior art, it is difficult to completely remove the polymer 26 remaining after dry etching of the metal wiring 24°29 with a phenolic resist stripping solution, especially on the side surfaces of steps and grooves. leaves a lot of residue. The adhesion of interlayer films and passivation films formed on top of this, such as coating films, vapor-grown silicon oxide films, and silicon nitride films, was poor, and peeling and cracking occurred immediately after growth and due to stress during post-processing. . In addition, reliability was adversely affected due to contamination, and reproducibility was poor due to increased hole resistance.
しかるに本発明は、かかる間顕点を解決するもので、半
導体装置の特に配線形成時の汚染を除去し、微細多機
半導体装置の安定供給を図ると共に、信頼性に伴う品質
の向上を図ることを目的としたものである。However, the present invention solves this problem, and eliminates contamination in semiconductor devices, especially during wiring formation, and improves fine multi-functionality.
The purpose is to ensure a stable supply of semiconductor devices and to improve quality along with reliability.
[課題を解決するための手段]
本発明の半導体装置の製造方法は、少な(とも、金属配
線をドライエツチングによりパターニングする工程、マ
スク用レジストを剥離する工程、オゾンガスを含む雰囲
気中で熱処理する工程、電相成長もしくは塗布法により
絶縁膜を積層させる工程を有したことを特徴とする。[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention includes a step of patterning metal wiring by dry etching, a step of peeling off a mask resist, and a step of heat treatment in an atmosphere containing ozone gas. , it is characterized by having a step of laminating an insulating film by electrophase growth or coating method.
〔実 施 例1
以下本発明の一実施例を、第1図に基づいて詳細に説明
する。[Embodiment 1] An embodiment of the present invention will be described below in detail based on FIG. 1.
サブミクロンルールのAI2配線2層構造のSiゲート
CMO3半導体装置に適用した場合に於いて、トランジ
スタや抵抗等の半導体素子が形成された半導体基板ll
上に選択熱酸化や気相成長による第1、第2のフィール
ド酸化膜12.13を形成し電極取り出し用のコンタク
トホールを開孔してから、Cuを0.1〜0.5%程度
含むAI2合金を厚みが約0.1umでスパッタリング
し。When applied to a Si gate CMO3 semiconductor device with a submicron rule AI2 wiring two-layer structure, a semiconductor substrate on which semiconductor elements such as transistors and resistors are formed.
First and second field oxide films 12.13 are formed on the top by selective thermal oxidation or vapor phase growth, and a contact hole for taking out the electrode is formed. Sputtering AI2 alloy to a thickness of approximately 0.1 um.
フォトレジスト15をパターニングする(第1図(a)
)、次にCI2□ガスを含んだRIEでドライエツチン
グし、最小寸法が0.8〜1.21mでほぼ垂直に側面
が形成された第1の金属配線14を施し、連続して同一
チャンバー内で02プラズマによりレジストを剥離し、
更に続けて02に約4%のC日F3を添加してプラズマ
中でポリマー16を付着させた後(第1図(b))、約
90℃のフェノール系レジスト剥離液に浸漬させる。次
に並行平板のプラズマ気相成長装置内で、約380℃、
0□中約5〜6%のオゾンガスを混入させ80torr
の条件で60秒間処理しポリマー16を完全除去した後
に(第1図(C))、5iHa とN20を反応ガスと
して眉間絶縁11i 17となるシリコン酸化膜を2t
orrで約0.7Lt m成長させた。つぎに平坦化の
為、この上に塗布ガラス膜18を付着してからアニール
し、スルーホールを開孔後Cuを含むAI2.合金を約
1.0μmの厚みでスパッタリングし、第1の金属配線
14と同様な工程でフォトエツチング、レジスト剥離を
行ない、第2の金属配線19とした(第1図(d))、
その後平行平板のプラズマ気相成長装置内で、前工程と
同様なオゾン処理をした後にSiH4とNHIを反応ガ
スとしてプラズマによるシリコン窒化膜を1torrで
約1.011 m成長させパシベーション膜とし、外部
電極取り出し用のパッド部を開孔した。Patterning the photoresist 15 (Fig. 1(a)
), then dry etching is performed using RIE containing CI2□ gas to form a first metal wiring 14 with a minimum dimension of 0.8 to 1.21 m and almost vertical side surfaces, and then continuously etched in the same chamber. Remove the resist using 02 plasma,
Subsequently, about 4% C/F3 was added to 02 to adhere polymer 16 in plasma (FIG. 1(b)), and then immersed in a phenolic resist stripping solution at about 90°C. Next, at about 380°C in a parallel plate plasma vapor phase growth apparatus,
About 5-6% ozone gas is mixed in 0□ and heated to 80 torr.
After completely removing the polymer 16 by processing for 60 seconds under the conditions of
It was grown to about 0.7 Lt m at orr. Next, for planarization, a coated glass film 18 is attached on top of this and annealed, and after opening a through hole, an AI2 layer containing Cu is applied. The alloy was sputtered to a thickness of about 1.0 μm, and photoetching and resist peeling were performed in the same process as the first metal wiring 14 to form the second metal wiring 19 (FIG. 1(d)).
After that, in a parallel plate plasma vapor phase epitaxy apparatus, after ozone treatment similar to the previous step, a silicon nitride film was grown by plasma to about 1.011 m at 1 torr using SiH4 and NHI as reaction gases to form a passivation film, and an external electrode was formed. A hole was made in the pad section for removal.
このようにしてなる半導体装置は、金属配線をエツチン
グし、レジスト剥離した後に堆積したポリマーがオゾン
処理により完全除去された為、従来のように層間絶縁膜
やパシベーション膜の剥離やクラックが皆無となり、ま
た長期信頼性も向上させることが出来た。In the semiconductor device manufactured in this way, the polymer deposited after etching the metal wiring and peeling off the resist is completely removed by ozone treatment, so there is no peeling or cracking of the interlayer insulating film or passivation film as in the past. We were also able to improve long-term reliability.
このポリマーの除去効果は、オゾン濃度が2%程度から
ポリマーの除去効果が明確になり濃度が高い程除去速度
は大きくなる。又処理温度には敏感ではないが、200
℃程度以上から、金属配線やPN接合に影響を与λない
450℃程度までの温度が良い。又このオゾン処理は、
処理効率を考えて、高周波平行平板電極を持つ電相成長
装置の同一チャンバーで連続処理を行なったが、別の装
置で行なっても良く、特に絶縁膜を気相成長させる際、
金属配線のヒロックを押えるように、装置内に半導体基
板をセットしてから反応成長が始まるまでにかかる熱時
間を短くしたものほどその効果は顕著であり、よって枚
葉式の気相成長を行なう時には特に有効である。The polymer removal effect becomes clear from an ozone concentration of about 2%, and the higher the concentration, the higher the removal rate. Although it is not sensitive to processing temperature,
It is preferable to use a temperature of about 450° C. or higher, which does not affect the metal wiring or PN junction. Also, this ozone treatment
Considering processing efficiency, continuous processing was carried out in the same chamber of an electrophase growth apparatus equipped with high-frequency parallel plate electrodes, but it may also be carried out in different apparatuses, especially when vapor-phase growing an insulating film.
In order to suppress hillocks in metal wiring, the effect is more pronounced as the heat time required from setting the semiconductor substrate in the device to the start of reaction growth is reduced, and therefore single-wafer vapor phase growth is performed. sometimes especially useful.
更に気相成長膜は、5iHaとN、Oだけでなく S
i H,や有機シランにO宜やオゾンのプラズマ反応や
熱反応させたものでも良く、又これらの複合膜も活用出
来る。Furthermore, the vapor-phase grown film contains not only 5iHa, N, and O, but also S.
It may be made by subjecting iH, or organic silane to a plasma reaction or thermal reaction of ozone, or a composite film of these may also be used.
本発明は、多層配線構造に限らず、金属配線上に絶縁膜
を形成するMO3IC、バイポーラや0MO3及び(れ
らを組み合わせたICにも適用できる。更に金属配線と
しては、Aff合金に限られず、他金属、ケイ化物や半
導体物質でもよく、この他平坦化、コンタクトバリヤー
の為にTi、W、Co、Mo等の高融点金属あるいはそ
の窒化物、ケイ化物および合金膜を積層化したものにも
応用可能である。The present invention is applicable not only to multilayer wiring structures, but also to MO3ICs, bipolar, 0MO3, and (combined ICs) in which an insulating film is formed on metal wiring.Furthermore, the metal wiring is not limited to Aff alloy, Other metals, silicides, and semiconductor materials may be used. In addition, high-melting point metals such as Ti, W, Co, and Mo, or their nitrides, silicides, and alloy films may be laminated for flattening and contact barrier purposes. It is applicable.
[発明の効果]
以上の様に本発明によれば、MO3LSI等の金属配線
上の絶縁膜の形成前にオゾン処理を施してやることによ
り、汚染生成物を除去し絶縁膜自身の品質に関わる特性
を改善し4m頼性の向上がなされるもので、より微細化
、多(化能化された半導体装置の供給に寄与出来るもの
である。[Effects of the Invention] As described above, according to the present invention, by performing ozone treatment before forming an insulating film on metal wiring such as MO3LSI, contamination products are removed and characteristics related to the quality of the insulating film itself are improved. This improves the reliability by 4 m and contributes to the supply of more miniaturized and more sophisticated semiconductor devices.
第1図(a)〜(b)は1本発明による半導体装置の実
施15!1を示す概略断面図である。
第2図(a)〜(c)は、従来の半導体装置に係わる概
略断面図である。
11 、21
12、22
13、23
14、24
15、25
16、26
17.27
18.28
19、29
・半導体基板
・第1のフィールド酸化膜
・第2のフィールド酸化膜
・第1の金属配線
・フォトレジスト
・ポリマー
・層間絶縁膜
・塗布ガラス嗅
・第2の金属配線
jl!1図(1
:i!1図
(b〕
!II図
((,1
以上FIGS. 1A and 1B are schematic cross-sectional views showing an embodiment 15!1 of a semiconductor device according to the present invention. FIGS. 2(a) to 2(c) are schematic cross-sectional views of conventional semiconductor devices. 11, 21 12, 22 13, 23 14, 24 15, 25 16, 26 17.27 18.28 19, 29 - Semiconductor substrate - First field oxide film - Second field oxide film - First metal wiring・Photoresist ・Polymer ・Interlayer insulation film ・Coated glass ・Second metal wiring jl! Figure 1 (1: i! Figure 1 (b)! Figure II ((, 1 or more
Claims (1)
ニングする工程、マスク用レジストを剥離する工程、オ
ゾンガスを含む雰囲気中で熱処理する工程、気相成長も
しくは塗布法による絶縁膜を積層させる工程を有したこ
とを特徴とする半導体装置の製造方法。It is characterized by having at least the steps of patterning the metal wiring by dry etching, peeling off the mask resist, heat treatment in an atmosphere containing ozone gas, and laminating an insulating film by vapor deposition or coating. A method for manufacturing a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29507888A JPH02140927A (en) | 1988-11-22 | 1988-11-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29507888A JPH02140927A (en) | 1988-11-22 | 1988-11-22 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02140927A true JPH02140927A (en) | 1990-05-30 |
Family
ID=17816033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29507888A Pending JPH02140927A (en) | 1988-11-22 | 1988-11-22 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02140927A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04291923A (en) * | 1991-03-20 | 1992-10-16 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1988
- 1988-11-22 JP JP29507888A patent/JPH02140927A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04291923A (en) * | 1991-03-20 | 1992-10-16 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
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