JPH02140926A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To remove a contamination product and to improve a characteristic relating to quality of an interlayer insulating film itself for improving reliability by flattening of an interlayer insulating film through plasma-and sputter-etching followed by giving ozone treatment. CONSTITUTION:After forming a first metal wiring 13, a first interlayer insulating film 14 is laminated. After performing dry etching of the prescribed film thickness of this interlayer insulating film 14, a second interlayer insulating is coated by vapor growth or an application method through a process of heat treatment in an atmosphere containing ozone gas. Next, a second metal wiring 17 is formed by making a throughhole. Accordingly, contamination accompanying flattening treatment of a semiconductor device having multilayer wirings is removed so that coming-off of an application film and a crack are excluded. Thereby, qualitative long reliability can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure for multi-function and integration.

[Conventional technology] Conventionally, a method for manufacturing a semiconductor device having a multilayer wiring structure is as follows.
For example, as shown in FIG. 2, field oxidation 1 on a semiconductor substrate 21 in which semiconductor elements such as transistors and resistors are built.
After drilling a contact hole to take out the electrode from the element through 1422, an A of 0.5 to 0.8L1m was opened.
After sputtering the first alloy, it is photoetched into a desired shape and the first metal pattern is formed! 123
After forming the first interlayer insulating film, a silicon oxide film of approximately 1.0 μm is formed by reacting SiH4 or organic silane with O*, N*O, or ozone in a gas phase under reduced pressure at a low temperature of 450°C or lower. (FIG. 2(a)), and then CF, CHFI, C*Fs gas, etc. were used to flatten the first interlayer insulating film 24 covering the stepped portion of the first metal wiring 23. Etch back with a dry etcher to form side walls and smooth, or perform spack etching with Ar, etc. (Fig. 2(b)), and then apply coated glass pus 26 and anneal, or directly coat the interlayer insulating film of the cylinder 2. After the growth, a through hole is made by photoetching and the diameter is approximately 1.0.
After sputtering an A1 alloy of um, photoetching is performed to form the second metal wiring 27 (FIG. 2(c)), a passivation film is laminated, and a pad portion for taking out an external electrode is opened.

[Problem to be Solved by the Invention 1] However, in the prior art, during dry etching or sputter etching for planarizing the first interlayer insulating film 24, the polymer 25 is generated due to a reaction between the silicon oxide film and the gas. In particular, a large amount adheres to the side surfaces of steps and grooves. The adhesion of the coating film 26 and the second interlayer insulating film formed thereon was poor, and peeling and cracking occurred immediately after growth and due to stress in post-processes. Moreover, these contaminants have had a negative effect on reliability. As a post-treatment after etching back the silicon oxide film, polymer removal using 0□ plasma has also been attempted, but
There is not much effect, and H, SO2 and H at about 90℃
Although the first metal wiring 23 is removed by immersion in the mixed solution of No. 02, the first metal wiring 23 is etched from the periphery of the wafer and from the pinholes, making it impossible to apply the process after the metal wiring is formed.

However, the present invention solves these problems, and eliminates contamination associated with planarization of semiconductor devices having multilayer interconnections, thereby stably supplying microscopic multifunctional semiconductor devices.
The purpose is to improve quality associated with reliability.

[Means for Solving the Problems 1] The method for manufacturing a semiconductor device of the present invention includes at least the step of laminating a first interlayer insulating film after forming a first metal wiring, and forming a predetermined thickness of the interlayer insulating film. After a dry etching step and a heat treatment step in an atmosphere containing ozone gas, a second interlayer insulating film is deposited by vapor phase growth or coating, and a second metal wiring formation step is performed by forming through holes. It is characterized by having the following.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to FIG.

Si gate C with submicron rule AI wiring two-layer structure
When applied to an MO5 semiconductor device, a silicon substrate on which semiconductor elements such as transistors and resistors are formed
A field oxide film 1 is formed on top by selective thermal oxidation or vapor phase growth.
2 is formed, a contact hole is opened for taking out the electrode, and AI containing about 0.5% Cu is sputtered to a thickness of about 0.7 μm. After photolithography, dry etching is performed with C1 gas, and J'! First, a 0-order first interlayer insulating film with a first metal wiring 13 having a small dimension of 0.8 to 1.2 μm and a substantially vertical side surface is formed using a parallel plate plasma vapor deposition apparatus. TE01<S i (QC
. It was etched back by 0.4 μm to flatten it. At this time, the polymer 15 adheres to the surface. (Figure 1(b))
. Subsequently, while heating the wafer to 300°C in a chamber, it was heated to 6 oz without flowing gas, containing 5 to 6% ozone.
orr for 60 seconds to remove 15% of the polymer (FIG. 1(c)'), a coated glass film 16 was formed thereon and annealed at 400°C. Subsequently, after forming through-holes, A1 alloy was sputtered and patterned to a thickness of about 1.0 am to form the second metal wiring 17.

Thereafter, a layer of plasma silicon nitride was applied, and a hole was made in the butt part for taking out the external electrode.

In the semiconductor device thus formed, since the deposited polymer is removed by ozone treatment after the first interlayer insulating film is etched back, there is no peeling or cracking of the coating film 16 as in the conventional case, and the quality is improved. The long-term reliability of the system has also been improved.

The removal effect of this polymer becomes clear from about 2% ozone at 1 degree, and the higher the concentration, the faster the removal rate becomes. Although it is not sensitive to processing temperature,
Does not affect metal wiring or PN junctions at temperatures above ℃45
A temperature of up to about 0°C is suitable. In addition, the growth process, etchback, and ozone treatment of this first interlayer insulating film were performed in the same chamber equipped with high-frequency parallel plate electrodes at a processing temperature of 36°C.
Continuous processing was also carried out while maintaining the temperature at 0 to 400°C, and it was possible to not only remove the polymer but also eliminate the problems of contamination and particles caused by transportation.

Etch back not only CF, and He but also CzF,,CH
It was also effective in removing polymers generated during sputter etching of F, 0□, and Ar.

In addition, the gas phase film used for the interlayer insulating film may be formed not only by the reaction of TEOS and 02, but also by a plasma reaction or thermal reaction using SiH4 and N20, 0□, TEOS and ozone,
Composite membranes of these can also be used. Furthermore, as for the second interlayer insulating film structure.

It can be applied not only to a single layer of a coated glass film or a vapor-grown film, but also to a composite film or an etched back structure of these films.

The present invention is applicable not only to MO5ICs but also to bipolar, 0MO3, and ICs that combine these, and can also be applied to the formation of interlayer insulating films between polycrystalline Si or polycrystalline Si and A1 alloy wiring. . Furthermore, the metal wiring is not limited to A1 alloy, but may also be other metals, silicides, or semiconductor materials.In addition, high-melting point metals such as Ti, W, Co, and Mo, or their nitrides may be used for planarization and contact barriers. It can also be applied to laminated films of materials, silicides, and alloy films.

[Effect of the invention 1 As described above, according to the present invention, the interlayer insulating film of MO5LSI etc. is flattened by plasma or sputter etching, and then ozone treatment is performed to remove contamination products and flatten the interlayer insulating film. This improves reliability by improving characteristics related to its own quality, and can contribute to the supply of more integrated and multi-functional semiconductor devices.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) are schematic cross-sectional views showing embodiments of a semiconductor device according to the present invention. FIGS. 2(a) to 2(C) are schematic cross-sectional views of conventional semiconductor devices. - Semiconductor substrate - Field oxide film - First metal wiring - First interlayer insulating film - Polymer - Coated glass film - Second metal wiring Figure 1 (α) Figure 1 cb+ Applicant Agent for Seiko Epson Corporation Person Patent Attorney Masaharu Kamiyanagi (and 1 other person) Figure 1 (C
) Figure 1rd)

Claims (1)

[Claims] At least, after forming the first metal wiring, a step of laminating a first interlayer insulating film, a step of dry etching a predetermined thickness of the interlayer insulating film, a step of heat treatment in an atmosphere containing ozone gas, and then a vapor phase A method for manufacturing a semiconductor device, comprising the steps of depositing a second interlayer insulating film by growth or coating, and forming a second metal wiring by forming a through hole.