JPH08111474A - Formation of wiring layer - Google Patents

Abstract

PURPOSE: To prevent the major part of a wiring layer, i.e., a metal layer, from being exposed to the outer surface by depositing a second fine metal particle film on the entire surface including the metal layer and then removing first and second resist films simultaneously with first and second fine metal films except the part covering the metal layer thereby forming a wiring layer. CONSTITUTION: Fine particles of Ti are deposited on the upper surface of a resist film 13 of a semiconductor substrate 11 to form a Ti film. Subsequently, fine particles of Pd are deposited on the Ti film to form a laminate of Ti/Pd. A resist film 24 is formed thereon and an opening 25 corresponding to a predetermined wiring pattern is made therein such that the laminate of Ti/Pd 15 is exposed. A Cu layer 26 is then formed on the Pd film in the laminate of Ti/Pd 15 exposed in the resist opening 25 by electrolytic plating using the resist 24 as a mask and the laminate of Ti/Pd 15 as a cathode. Consequently, the Cu layer 26 in a wiring layer 28 is covered by the laminate of Ti/Pd 15 and an Ni layer 27 and prevented from being exposed to the outer surface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a wiring layer used for manufacturing a wiring board such as a multilayer wiring board of a multichip module.

[0002]

2. Description of the Related Art A conventional method of forming a wiring layer of a wiring board for a multi-chip module by plating will be described with reference to FIGS. 9 to 12 are cross-sectional views showing the steps of forming a wiring layer in the order of steps.

First, in a first step shown in FIG. 9, about 0.1 μm of Ti is deposited on the SiO ₂ insulating layer 2 formed on the upper surface of the substrate 1 by a commonly used sputtering method.
To a thickness of 0.1 μm.
The Ti / Cu layer 3 is formed by continuous deposition to have a film thickness of. Subsequently, a resist film 4 having a thickness of 10 μm is formed on the Ti / Cu layer 3, and a resist opening portion 5 corresponding to a predetermined wiring pattern is formed on the Ti / C layer by photolithography.
It is formed so that the u layer 3 is exposed.

Next, in the second step shown in FIG.
Electrolytic Cu plating using the resist film 4 as a mask and the Ti / Cu layer 3 as a cathode, for example, when CuSO ₄ is used, is performed at room temperature with a pH of 0.1 and a current density of 10 mA / cm ^2. Then, a 10 μm thick Cu layer 6 is formed on the Cu film of the Ti / Cu layer 3 exposed in the resist opening 5. After that, the resist film 4 is removed with an ethylene glycol-based solution.

Next, in the third step shown in FIG.
A resist film 7 is formed on the Ti / Cu layer 3 and the Cu layer 6. Then, using the photolithography technique again, Cu
The resist film 7 in the other portion is removed so that it is left in the region including the layer 6 and its vicinity. Using the resist film 7 covering the remaining Cu layer 6 as a mask, an ammonium persulfate aqueous solution (20
wt%) to remove the Cu film of the Ti / Cu layer 3 by etching, followed by EDTA (ethylenediaminetetraacetic acid),
The Ti film remaining on the Ti / Cu layer 3 is removed by etching with NH ₄ OH and H ₂ O ₂ .

Finally, in the fourth step shown in FIG.
The resist film 7 is removed to form the wiring layer 8 composed of the Cu layer 6 and the Ti / Cu layer 3. After that, an interlayer insulating film made of polyimide, SiO ₂ or the like is deposited on the entire surface to form a wiring board.

When forming a multi-layer wiring board,
After the fourth step shown in FIG. 12 above, although not shown, polyimide or SiO having a required thickness is formed on the entire surface of the substrate including the wiring layer 8.
An interlayer insulating film such as ₂ is deposited, the upper and lower wiring layers are formed so as to contact each other at predetermined portions, and the above steps are repeated to form a multilayer wiring board having the required number of layers.

According to such a method for forming the wiring layer of the wiring board for the multi-chip module, the interlayer insulating film is directly formed on the outer surface of the wiring layer 8 with the outer surface thereof exposed. Therefore, at the interface between the polyimide film or the SiO ₂ film of the interlayer insulating film which is in contact with the surface of the wiring layer 8, the Cu of the wiring layer 8 and the polyimide film or the SiO ₂ film are mutually diffused or other impurities are diffused into Cu. An increase in wiring resistance due to diffusion, deterioration of adhesion due to deterioration of the surface of the wiring layer 8 in which the Cu surface is oxidized by residual water in the interlayer insulating film, and the like, and improvement in reliability of the wiring board itself cannot be expected. .

When the wiring layer 8 is formed, it is necessary to form the resist layer 7 over the entire surface, form the photolithography technique, and etch after forming the Cu layer 6 in the second step. The mask required for the photolithography technique at this time requires a mask having a different width in addition to the mask for forming the resist opening 5 in the resist film 4 to form one wiring pattern. Two
The use of two masks would increase the manufacturing cost.

[0010]

As described above, in the conventional structure, the interlayer insulating film is formed directly on the outer surface of the wiring layer, and the interdiffusion and the wiring layer are formed at the interface between the wiring layer and the interlayer insulating film. It is difficult to improve the reliability of the wiring board due to the increase of wiring resistance due to surface deterioration or the deterioration of adhesion between the two.
Further, two masks having different widths are required to form one wiring pattern. The present invention has been made in view of such circumstances, and an object thereof is to provide a method for forming a wiring layer that can improve the reliability of the wiring board and reduce the manufacturing cost. is there.

[0011]

According to a method of forming a wiring layer of the present invention, a first opening corresponding to a desired wiring pattern is formed in a first resist film on a substrate by lithography using a predetermined mask. And a step of forming a first metal fine particle film on the first opening and the surface of the first resist film, and a second resist film on the surface of the first metal fine particle film.
Forming a second opening in the resist film by lithography using the mask, forming a metal layer in the second opening by a plating method, and forming a metal layer and a second resist film surface in the second opening. 2 step of forming a metal fine particle film, and the first metal fine particle film and the second metal fine particle film in a portion other than the portion for removing the first resist film and the second resist film and simultaneously covering the metal layer And a step of removing the metal fine particles produced by the in-gas evaporation method together with the inert gas, and sprayed by the first metal fine particle film and the second metal fine particle film. It is characterized in that it is deposited in this way. Furthermore, the plating method for forming a metal layer is the first method.
Electroplating using the metal fine particle film of
Characterized in that it is electroless plating using the metal fine particle film as an underlayer, and the second metal fine particle film is at least one of Ni, Pd, Pt, Au and Ag.
The invention is characterized in that a film is formed by using a kind of metal or an alloy mainly containing these metals.
Is a laminated film, and at least one layer is N
The film is formed of one kind of metal selected from i, Pd, Pt, Au, and Ag or an alloy mainly containing these metals, and the other layer mainly contains at least one metal of Ti and Cr or these metals. It is characterized in that it is formed of an alloy, and the metal layer is at least C
It is characterized by being layered by one kind of metal among u, Ag and Au or an alloy mainly composed of these metals.

[0012]

The method of forming the wiring layer configured as described above is
After forming a first opening corresponding to a desired wiring pattern by lithography on a first resist film on the substrate using a predetermined mask, a first metal fine particle film is formed on the entire surface including the first opening. A second opening is formed on the second resist film formed thereon by lithography using the same mask as the mask, and a metal layer is formed on the second opening by plating. Further, after forming the second metal fine particle film on the entire surface including the metal layer, the first and second resist films are removed, and at the same time, the first and second metal fine particle films on the portion other than the portion for covering the metal layer are formed. The metal layer, which is the main part of the wiring layer, is firstly removed.
And the second metal fine particle film does not expose the outer surface. For this reason, even if an interlayer insulating film is deposited around the wiring layer, the metal layer does not directly contact the interlayer insulating film, and the wiring resistance increases or the surface quality of the wiring layer deteriorates due to mutual diffusion between the wiring layer and the interlayer insulating film. The adhesiveness is not deteriorated due to, the reliability of the wiring board is significantly improved, and the same mask can be used for the two lithography processes, so that the manufacturing cost can be reduced. .

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. 1 to 5 are cross-sectional views showing respective steps of forming a wiring layer in the order of steps, FIG. 6 is a schematic configuration diagram shown for explaining a gas deposition method, and FIGS. 7 and 8 are multilayer wirings, respectively. It is sectional drawing of the process at the time of forming a board | substrate.

First, in the first step shown in FIG. 1, a positive resist having a viscosity of about 500 cp is dropped on the SiO ₂ insulating layer 12 formed on the upper surface of a substantially circular semiconductor substrate 11. Then, the semiconductor substrate 11 is first spin-spun at a rotation speed of 400 rpm for 60 seconds so that the film thickness is uniform in the central portion and the peripheral portion on the insulating layer 12, and then 30 times.
The rotation speed is 00 rpm for 20 seconds. As a result, a resist film 13 having a film thickness of about 12 μm is formed on the insulating layer 12.

Thereafter, a resist opening 14 corresponding to a predetermined wiring pattern having a width of 10 to 20 μm is formed by photolithography so that the insulating layer 12 is exposed.

Next, in a second step shown in FIG. 2, Ti fine particles and Pd fine particles are formed on the entire upper surface of the resist film 13 on the semiconductor substrate 11 in which the resist openings 14 are formed by using a gas deposition method. Film formation is performed to form a Ti / Pd laminated film 15 which is a first metal fine particle film made of a Ti film and a Pd film having a film thickness of 0.5 μm.

This gas deposition method is carried out by a processing apparatus having a first chamber 16 and a second chamber 17, as shown in the schematic diagram of FIG. The processing apparatus is provided with a gas introduction pipe 18 for introducing He gas into the first chamber 16 and is connected to the first and second chambers 16 and 17 by a transfer pipe 19.

The pressure in the first chamber 16 is set to 1a
tm, and the pressure in the second chamber 17 is 0.3 Tor.
The He gas can flow from the first chamber 16 to the second chamber 17 due to the pressure difference by keeping the vacuum at about r, and the He gas can flow from the nozzle 20 at the tip of the transfer pipe 19 into the second chamber 17. It is pouring in.

Film formation of Ti fine particles on the resist film 13 of the semiconductor substrate 11 by such an apparatus is as follows. That is, Ti is put in the pyrolytic graphite crucible 21 housed in the first chamber 16 as the vaporized metal source 22. Then, Ti is heated to about 2000 ° C. by the induction heating coil 23 provided so as to surround the crucible 21.
To generate Ti metal vapor. Occurred T
The metal vapor of i is introduced into the first chamber 16 through the gas introduction pipe 18.
Cooled with He gas introduced inside, the particle size is about 0.02μm
To produce Ti fine particles.

The generated Ti fine particles are sucked into the carrier pipe 19 having an end opening above the crucible 21 together with the flow of He gas, and the semiconductor substrate is housed below the nozzle 20 in the second chamber 17. It is sent to the upper surface of the resist film 13 of No. 11. The delivered Ti particles are the semiconductor substrate 11
A Ti film can be formed by depositing on the upper surface of the resist film 13 of FIG.

Similarly, Pd is put in the crucible 21 as the metal vapor source 22 and heated to about 2000.degree.
Of the metal vapor is generated and further cooled with He gas to produce Pd fine particles having a particle size of about 0.02 μm. And Ti
Pd fine particles are continuously deposited on the film to form a Pd film to form a Ti / Pd laminated film 15.

Next, in the third step shown in FIG.
A resist film 24 having a thickness of about 2 μm is formed on the i / Pd laminated film 15. Then, the resist opening 25 corresponding to the predetermined wiring pattern is formed in Ti by the photolithography technique using the same mask as that used in the first step.
The / Pd laminated film 15 is formed so as to be exposed.

Then, an electrolytic plating method using the resist film 24 having the resist opening 25 formed as a mask and the Ti / Pd laminated film 15 as a cathode, for example, when CuSO ₄ is used, the pH is set to about 0.1. The film thickness is about 10 μm by performing it at room temperature with a current density of 10 mA / cm ^2.
The Cu layer 26 of T is exposed in the resist opening 25.
It is formed on the Pd film of the i / Pd laminated film 15. Although the Cu layer 26 is formed by electrolytic plating here,
It may be formed by an electroless plating method using O or Cu (OH) ₂ .

Next, in the fourth step shown in FIG. 4, the crucible 2 is used by using the gas deposition method in the second step.
The evaporation metal source 22 in 1 is Ni, and this is heated to Ni.
The metal vapor is generated and further cooled with He gas to generate Ni fine particles having a particle size of about 0.02 μm. And Cu formed in the resist film 24 and the resist opening 25
A film of Ni fine particles is formed on the entire upper surface of the layer 26 to form a Ni film 27 which is a second metal fine particle film having a thickness of 0.5 μm.

Next, in a fifth step shown in FIG. 5, the resist films 13, 24 are removed with a stripping solution such as an ethylene glycol-based solution or MMP (methyl-3-methoxypropinate).
And removing the Ti / Pd laminated film 15 and the Ni film 27 in a portion other than the portion covering the Cu layer 26,
A wiring layer 28 composed of the Cu layer 26, the Ti / Pd laminated film 15 and the Ni film 27 covering the Cu layer 26 is formed. After that, an interlayer insulating film made of polyimide, SiO ₂ or the like is deposited on the entire surface to form a wiring board.

When forming a multilayer wiring board,
This is required by forming a thin interlayer insulating film on the semiconductor substrate 11 having the wiring layer 28 after the fifth step shown in FIG. 5 or forming a thick interlayer insulating film and then repeating the above steps. A multilayer wiring board having the number of layers is formed.

For example, a case of forming a thin interlayer insulating film will be described with reference to FIG. 7. On the semiconductor substrate 11 on which the wiring layer 28 is formed, the wiring layer 28 is thinly covered with polyimide or SiO. Interlayer insulation film 2 consisting of ₂ etc.
9 is deposited. Then, the entire upper surface 29a of the interlayer insulating film 29
Is removed by etch back to expose the upper surface of the wiring layer 28. And again, the upper wiring layer and the wiring layer 2 not shown
An insulating layer is provided so as to make contact with a predetermined portion, and an upper wiring layer is formed by repeating the above steps.

A case of forming a thick interlayer insulating film will be described with reference to FIG. 8. The semiconductor substrate 11 having the wiring layer 28 formed thereon is covered with polyimide, SiO ₂ or the like so that the wiring layer 28 is thickly covered. The inter-layer insulation film 30 is deposited. Then, a contact hole 31 is formed at a predetermined portion of the interlayer insulating film 30 so that the wiring layer 28 is exposed at the inner bottom portion thereof. Then, although not shown, the contact hole 31 is filled with a conductive material, and the upper wiring layer is formed again by repeating the above steps.

With the above-mentioned structure, the wiring layer 2
In FIG. 8, the Cu layer 26 is the Ti / Pd laminated film 15 and the Ni film 27.
Covered Cu layer 26 is not exposed to the outer surface, an interlayer insulating film and the Cu polyimide film or SiO ₂ film is formed after this
There is no direct contact with the layer 26. Therefore, the wiring layer 2
8 at the interface between the interlayer insulating film 8 and the interlayer insulating film, deterioration of adhesion due to deterioration of the surface of the wiring layer 28 due to residual water in the interlayer insulating film, mutual diffusion between the Cu layer 26 and the interlayer insulating film, or Cu layer of other impurities. The wiring resistance does not increase due to diffusion into the wiring 26, and the reliability of the wiring board itself is significantly improved.

Further, when the wiring layer 28 is formed, formation of the resist films 13 and 24, photolithography technique, etching, etc. are performed. At this time, only one mask is required for two photolithography techniques. Good.

On the other hand, when a metal film of Ti or Ni is to be formed on the organic film such as the resist films 13 and 24, in the sputtering method used in the usual LSI manufacturing process,
The organic film itself is exposed to plasma, the inner wall of the sputtering chamber and the sputtering target are contaminated with the organic material, and it is extremely difficult to form a metal film without impurities.

However, in forming the Ti film of the Ti / Pd laminated film 15 and the metal fine particle film of the Ni film 27 using the gas deposition method as described above, the metal vapor source 22 and the metal fine particles are generated. First chamber 16 and semiconductor substrate 11
Since the second chamber 17 for depositing the metal fine particle film is provided separately, it is not necessary to consider contamination by the organic film on the semiconductor substrate 11, and the wiring layer 28 having excellent characteristics can be obtained.

Moreover, the processing apparatus of the gas deposition method is cheaper than the sputtering apparatus, and the number of masks used in the photolithography technique is reduced, so that the manufacturing cost can be reduced.

In the above embodiment, the Ni film 27 made of Ni fine particles was formed on the upper surface of the Cu layer 26.
Instead of 7, the film may be formed of Pd, Pt, Au, Ag, or an alloy mainly containing these. Further Cu layer 26
The Ti / Pd laminated film 15 was formed before forming T.
Instead of the Ti film of the i / Pd laminated film 15, Cr or an alloy mainly containing Cr may be formed, and instead of the Pd film, Ni, Pt, Au, Ag or an alloy mainly containing these may be formed. You may film. Furthermore, the wiring layer 28
May be formed of Ag, Au, or an alloy mainly containing these instead of the Cu layer 26.

[0035]

As is apparent from the above description, according to the present invention, the reliability of the wiring board can be improved and the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step in one embodiment of the present invention.

FIG. 2 is a sectional view showing a second step in one embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a third step in one embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a fourth step in one embodiment of the present invention.

FIG. 5 is a sectional view showing a fifth step in one embodiment of the present invention.

FIG. 6 is a schematic configuration diagram shown for explaining a gas deposition method according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view shown for explaining a step of forming a multilayer wiring board by providing a thin interlayer insulating film according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view shown for explaining a step of forming a multilayer wiring board by providing a thick interlayer insulating film according to an embodiment of the present invention.

FIG. 9 is a sectional view showing a first step in a conventional example.

FIG. 10 is a cross-sectional view showing a second step in the conventional example.

FIG. 11 is a cross-sectional view showing a third step in the conventional example.

FIG. 12 is a cross-sectional view showing a fourth step in the conventional example.

[Explanation of symbols]

 11 ... Semiconductor substrate 12 ... Insulating layer 13, 24 ... Resist film 14, 25 ... Resist opening 15 ... Ti / Pd laminated film 26 ... Cu layer 27 ... Ni film 28 ... Wiring layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H05K 3/18 B 7511-4E 3/24 A 7511-4E // H01L 23/522

Claims (6)

[Claims] 1. A step of forming a first opening corresponding to a desired wiring pattern by lithography in a first resist film on a substrate by using a predetermined mask, the first opening and the first opening. Forming a first metal fine particle film on the resist film surface, and forming a second resist film on the first metal fine particle film surface by lithography using a second mask using the mask. A step of forming an opening,
Forming a metal layer on the second opening by a plating method; forming a second metal fine particle film on the metal layer and the second resist film surface; the first resist film and the A step of removing the second resist film and at the same time removing the first metal fine particle film and the second metal fine particle film in a portion other than the portion covering the metal layer. Forming method. 2. The first metal fine particle film and the second metal fine particle film are formed by transporting and spraying metal fine particles generated by an in-gas evaporation method together with an inert gas. The method of forming a wiring layer according to claim 1, wherein the wiring layer is formed. 3. The plating method for forming a metal layer is electrolytic plating using a first metal fine particle film as a cathode, or the first metal fine particle film as a cathode.
2. The method for forming a wiring layer according to claim 1, wherein the metal fine particle film is used as an underlayer for electroless plating. 4. The second metal fine particle film comprises at least N 2.
The method of forming a wiring layer according to claim 1 or 2, wherein the film is formed of one kind of metal selected from i, Pd, Pt, Au, and Ag or an alloy mainly containing these metals. 5. The first metal fine particle film is a multilayer film,
One layer is formed of at least one metal selected from Ni, Pd, Pt, Au, and Ag or an alloy mainly composed of these metals, and the other layer is formed of at least one metal of Ti or Cr or these metals. The method for forming a wiring layer according to claim 1, wherein the film is formed of an alloy as a main component. 6. The metal layer comprises at least Cu, Ag, Au.
4. The method for forming a wiring layer according to claim 1, wherein the wiring layer is formed of one of the metals described above or an alloy containing these metals as a main component.