JP3243381B2 - Method of forming wiring layer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring layer used for manufacturing a wiring board such as a multilayer wiring board of a multi-chip module.

[0002]

2. Description of the Related Art A conventional method for forming a wiring layer of a wiring board for a multichip module by a plating method will be described with reference to FIGS. 9 to 12 are cross-sectional views showing steps of forming a wiring layer in the order of steps.

First, in a first step shown in FIG. 9, Ti is applied to a thickness of about 0.1 μm on a SiO ₂ insulating layer 2 formed on the upper surface of a substrate 1 by a commonly used sputtering method.
Is deposited so as to have a thickness of about 0.1 μm.
To form a Ti / Cu layer 3. Subsequently, a resist film 4 having a thickness of 10 μm is formed on the Ti / Cu layer 3 and a resist opening 5 corresponding to a predetermined wiring pattern is formed by photolithography using Ti / C.
It is formed so that the u layer 3 is exposed.

Next, in a second step shown in FIG.
When electrolytic Cu plating using the Ti / Cu layer 3 as a cathode with the resist film 4 as a mask, for example, CuSO ₄ is used, the pH is set to 0.1 and the current density is set to 10 mA / cm ² at room temperature. Then, a Cu layer 6 having a thickness of 10 μm is formed on the Cu film of the Ti / Cu layer 3 exposed in the resist opening 5. Thereafter, the resist film 4 is removed with an ethylene glycol solution.

Next, in a third step shown in FIG.
A resist film 7 is formed on the Ti / Cu layer 3 and the Cu layer 6. Then, again using photolithography technology, Cu
Other portions of the resist film 7 are removed so as to remain in the region including the layer 6 and the vicinity thereof. Using the resist film 7 covering the remaining Cu layer 6 as a mask, an aqueous solution of ammonium persulfate (20
wt%), the Cu film of the Ti / Cu layer 3 is removed by etching, followed by EDTA (ethylenediaminetetraacetic acid),
The remaining Ti film of the Ti / Cu layer 3 is removed by etching with NH ₄ OH and H ₂ O ₂ .

Finally, in a fourth step shown in FIG.
By removing the resist film 7, a wiring layer 8 composed of the Cu layer 6 and the Ti / Cu layer 3 is formed. Thereafter, an interlayer insulating film made of polyimide, SiO ₂ or the like is deposited on the entire surface to form a wiring board.

In the case of forming a multilayer wiring board,
After the fourth step shown in FIG. 12, although not shown, the required thickness of polyimide or SiO
An interlayer insulating film such as ₂ is deposited, and upper and lower wiring layers are formed so as to be in contact with each other at a predetermined portion, and the above-described steps are repeated to form a multilayer wiring board of a required number of layers.

According to such a method for forming a wiring layer of a wiring board for a multichip module, an interlayer insulating film is formed directly on the wiring layer 8 with the outer surface exposed. For this reason, at the interface between the polyimide film and the SiO ₂ film of the interlayer insulating film in contact with the surface of the wiring layer 8, the interdiffusion between the Cu of the wiring layer 8 and the polyimide film or the SiO ₂ film or the diffusion of other impurities into the Cu An increase in wiring resistance due to diffusion, deterioration of adhesion due to deterioration of the surface of the wiring layer 8 where the Cu surface is oxidized due to residual moisture in the interlayer insulating film, etc., occur, and it is not possible to expect improvement of the reliability of the wiring substrate itself. .

When the wiring layer 8 is formed, it is necessary to form a resist film 7 over the entire surface, photolithography, etching, etc. after forming the Cu layer 6 in the second step. The mask required for the photolithography technique at this time requires a mask having a different width in addition to the mask for forming the resist opening 5 in the resist film 4 in order to form one wiring pattern. 2
One mask must be used, which increases the manufacturing cost.

[0010]

As described above, in the conventional structure, the interlayer insulating film is formed directly on the outer surface of the wiring layer, and the interdiffusion or the wiring layer is formed at the interface between the wiring layer and the interlayer insulating film. It is difficult to improve the reliability of the wiring board due to the increase in wiring resistance due to surface deterioration, or the deterioration of adhesion between the two,
Further, two masks having different widths are required to form one wiring pattern. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a method for forming a wiring layer that can improve the reliability of a wiring board and reduce manufacturing costs. is there.

[0011]

According to a method of forming a wiring layer of the present invention, a first opening corresponding to a desired wiring pattern is formed in a first resist film on a substrate by lithography using a predetermined mask. Forming a first metal fine particle film on the first opening and the first resist film surface, forming a second resist film on the first metal fine particle film surface,
Forming a second opening in the resist film by lithography using the mask, forming a metal layer in the second opening by plating, and forming a second layer on the surface of the metal layer and the second resist film. Forming the second metal fine particle film, removing the first resist film and the second resist film, and simultaneously forming the first metal fine particle film and the second metal fine particle film at a portion other than the portion covering the metal layer. Wherein the first metal fine particle film and the second metal fine particle film transport and blow the metal fine particles generated by the in-gas evaporation method together with the inert gas. The plating method for forming a metal layer is characterized by the following:
Electrolytic plating using the metal fine particle film of
Wherein the second metal fine particle film is formed of at least one of Ni, Pd, Pt, Au, and Ag.
Characterized in that the film is formed by a kind of metal or an alloy mainly composed of these metals.
Is a laminated film, one of which is at least N
The film is formed by one kind of metal among i, Pd, Pt, Au, and Ag or an alloy mainly composed of these metals, and the other layer is mainly composed of at least one of Ti, Cr or these metals. Characterized in that the metal layer is formed of an alloy.
It is characterized by being layered by one kind of metal among u, Ag and Au or an alloy mainly containing these metals.

[0012]

The method of forming the wiring layer configured as described above is as follows.
After forming a first opening corresponding to a desired wiring pattern on a first resist film on a substrate by lithography using a predetermined mask, a first metal fine particle film is formed on the entire surface including the first opening. A second opening is formed in the second resist film formed thereon by lithography using the same mask as the mask, and a metal layer is formed in the second opening by a plating method; Further, after forming the second metal fine particle film on the entire surface including the metal layer, the first and second resist films are removed, and at the same time, the first and second metal fine particle films in portions other than the portion covering the metal layer are removed. The wiring layer is formed by removing the first metal layer.
And it is covered with the second metal fine particle film and is not exposed to the outer surface. For this reason, even if an interlayer insulating film is deposited around the wiring layer, the metal layer does not directly contact the interlayer insulating film, and the wiring resistance increases due to mutual diffusion between the wiring layer and the interlayer insulating film and the surface of the wiring layer deteriorates. The reliability of the wiring substrate is greatly improved without causing the deterioration of the adhesion due to the lithography, and the same mask can be used for the mask used in the two lithography, so that the manufacturing cost can be reduced. .

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. 1 to 5 are cross-sectional views showing the steps of forming a wiring layer in the order of steps, FIG. 6 is a schematic configuration diagram for explaining a gas deposition method, and FIGS. It is sectional drawing of the process at the time of forming a board | substrate.

First, in a first step shown in FIG. 1, a positive resist having a viscosity of about 500 cp is dropped on an SiO ₂ insulating layer 12 formed on the upper surface of a substantially circular semiconductor substrate 11. Then, spin rotation of the semiconductor substrate 11 is first performed at a rotation speed of 400 rpm for 60 seconds so that the film thickness at the center portion and the peripheral portion on the insulating layer 12 becomes uniform, and then 30 minutes.
This is performed for 20 seconds at a rotation speed of 00 rpm. Thus, a resist film 13 having a thickness of about 12 μm is formed on the insulating layer 12.

Thereafter, a resist opening 14 corresponding to a predetermined wiring pattern having a width of 10 to 20 μm is formed by photolithography so that the insulating layer 12 is exposed.

Next, in a second step shown in FIG. 2, Ti fine particles and Pd fine particles are formed on the entire upper surface of the resist film 13 on the semiconductor substrate 11 in which the resist openings 14 are formed by using a gas deposition method. A Ti / Pd laminated film 15 which is a first metal fine particle film made of a Ti film and a Pd film each having a thickness of 0.5 μm is formed.

This gas deposition method is performed by a processing apparatus having a first chamber 16 and a second chamber 17 as shown in FIG. The processing apparatus is provided with a gas introduction pipe 18 for introducing He gas into the first chamber 16, and is connected to the first and second chambers 16 and 17 by a transfer pipe 19.

Then, the pressure in the first chamber 16 is set to 1a
tm, and the pressure in the second chamber 17 is 0.3 Torr.
By setting the vacuum at about r, the He gas flows from the first chamber 16 to the second chamber 17 due to the pressure difference, and the He gas flows from the nozzle 20 at the tip of the transfer pipe 19 into the second chamber 17. It is flowing.

The formation of Ti fine particles on the resist film 13 of the semiconductor substrate 11 by such an apparatus is as follows. That is, Ti is put into the pyrolytic graphite crucible 21 accommodated in the first chamber 16 as the evaporated metal source 22. Then, Ti is heated to about 2000 ° C. by an induction heating coil 23 provided so as to surround the crucible 21.
To generate metal vapor of Ti. T that occurred
i is supplied to the first chamber 16 through the gas introduction pipe 18.
Cooled by He gas introduced inside, the particle size is about 0.02 μm
To generate Ti fine particles.

The generated Ti fine particles are sucked together with the flow of He gas into a transfer pipe 19 having an end opening above the crucible 21, and the semiconductor substrate housed below the nozzle 20 in the second chamber 17. 11 is sent to the upper surface of the resist film 13. The transmitted Ti fine particles are applied to the semiconductor substrate 11.
Is deposited on the upper surface of the resist film 13 to form a Ti film.

Similarly, Pd is placed in the crucible 21 as the evaporated metal source 22 and heated to about 2000 ° C.
Is generated, and further cooled with He gas to generate Pd fine particles having a particle size of about 0.02 μm. And Ti
Pd fine particles are continuously deposited on the film, and a Pd film is formed to form a Ti / Pd laminated film 15.

Next, in a third step shown in FIG.
A resist film 24 having a thickness of about 2 μm is formed on the i / Pd laminated film 15. Then, by photolithography using the same mask as that used in the first step, the resist opening 25 corresponding to the predetermined wiring pattern is
/ Pd laminated film 15 is formed to be exposed.

Subsequently, in the case of using an electrolytic plating method using the Ti / Pd laminated film 15 as a cathode with the resist film 24 in which the resist opening 25 is formed as a mask, for example, when CuSO ₄ is used, the pH is set to 0.1, By performing the treatment under the condition of room temperature with a current density of 10 mA / cm ² , the film thickness is about 10 μm
Exposing the Cu layer 26 in the resist opening 25
It is formed on the Pd film of the i / Pd laminated film 15. Here, the Cu layer 26 was formed by the electrolytic plating method.
It may be formed by an electroless plating method using O or Cu (OH) ₂ .

Next, in a fourth step shown in FIG. 4, the gas deposition method in the second step is used to
1 is Ni, and this is heated to Ni.
And then cooled with He gas to produce Ni fine particles having a particle size of about 0.02 μm. Then, the Cu formed in the resist film 24 and the resist opening 25 is formed.
A film of Ni fine particles is formed on the entire upper surface of the layer 26 to form a Ni film 27 as a second metal fine particle film having a thickness of 0.5 μm.

Next, in a fifth step shown in FIG. 5, the resist films 13, 24 are removed with a stripping solution such as an ethylene glycol solution or MMP (methyl-3-methoxypropionate).
And the Ti / Pd laminated film 15 and the Ni film 27 in portions other than the portion covering the Cu layer 26 are removed,
A wiring layer 28 composed of a Cu layer 26 and a Ti / Pd laminated film 15 and a Ni film 27 covering the Cu layer 26 is formed. Thereafter, an interlayer insulating film made of polyimide, SiO ₂ or the like is deposited on the entire surface to form a wiring board.

In the case of forming a multilayer wiring board,
After the fifth step shown in FIG. 5, a thin interlayer insulating film is formed on the semiconductor substrate 11 having the wiring layer 28, or the above-described steps are repeated after forming a thick interlayer insulating film. A multilayer wiring board having the number of layers is formed.

For example, the case where a thin interlayer insulating film is formed will be described with reference to FIG. 7. On the semiconductor substrate 11 on which the wiring layer 28 is formed, polyimide or SiO is formed to a thickness such that the wiring layer 28 is thinly covered. Interlayer insulating film 2 composed of ₂ etc.
9 is deposited. Subsequently, the entire upper surface 29a of the interlayer insulating film 29
Is removed by etch back to expose the upper surface of the wiring layer 28. Then, an upper wiring layer and a wiring layer 2 (not shown)
An upper wiring layer is formed by repeating the above-described steps, for example, by providing an insulating layer so as to make contact with a predetermined portion.

The case where a thick interlayer insulating film is formed will be described with reference to FIG. 8. The semiconductor substrate 11 on which the wiring layer 28 is formed is covered with polyimide or SiO ₂ so that the wiring layer 28 is thickly covered. An interlayer insulating film 30 is deposited. Subsequently, a contact hole 31 is formed at a predetermined portion of the interlayer insulating film 30 so that the wiring layer 28 is exposed at an inner bottom thereof. Then, although not shown, the contact hole 31 is filled with a conductive material, and an upper wiring layer is formed again by repeating the above steps.

With the above configuration, the wiring layer 2
Numeral 8 indicates that the Cu layer 26 is composed of the Ti / Pd laminated film 15 and the Ni film 27.
The Cu layer 26 is not exposed on the outer surface and is covered with Cu and an interlayer insulating film such as a polyimide film or SiO ₂ film.
There is no direct contact with the layer 26. Therefore, the wiring layer 2
At the interface between the insulating layer 8 and the interlayer insulating film, the adhesion of the wiring layer 28 deteriorates due to the deterioration of the surface due to residual moisture in the interlayer insulating film, the mutual diffusion between the Cu layer 26 and the interlayer insulating film, or the Cu layer of other impurities. There is no increase in wiring resistance due to the diffusion to 26, and the reliability of the wiring board itself is greatly improved.

When the wiring layer 28 is formed, the formation of the resist films 13 and 24, photolithography, etching, and the like are performed. At this time, only one mask is required for the two photolithography techniques. Is fine.

On the other hand, when a metal film such as Ti or Ni is to be formed on an organic film such as the resist films 13 and 24, the sputtering method used in a normal LSI manufacturing process is as follows.
The organic film itself is exposed to the plasma, and the inner wall of the sputter chamber and the sputter target are contaminated with the organic material, so that it is extremely difficult to form a metal film without impurities.

However, as described above, in the formation of the Ti film of the Ti / Pd laminated film 15 and the fine metal film of the Ni film 27 using the gas deposition method, the evaporated metal source 22 and the fine metal particles are generated. First chamber 16 and semiconductor substrate 11
Since the second chamber 17 for forming a metal fine particle film is separately provided, there is no need to consider the contamination by the organic film on the semiconductor substrate 11, and the wiring layer 28 having excellent characteristics can be obtained.

Moreover, the processing apparatus of the gas deposition method is less expensive than the sputtering apparatus, and the manufacturing cost can be reduced because the number of masks used in the photolithography technique is reduced.

In the above embodiment, the Ni film 27 made of Ni fine particles is formed on the upper surface of the Cu layer 26.
Alternatively, the film may be formed of Pd, Pt, Au, Ag, or an alloy mainly composed of these. Further, the Cu layer 26
The Ti / Pd laminated film 15 was formed before the formation of
The i / Pd laminated film 15 may be formed of Cr or an alloy mainly composed of Cr instead of the Ti film, or may be composed of Ni, Pt, Au, Ag or an alloy mainly composed of these instead of the Pd film. It may be a film. Further, the wiring layer 28
May be formed of Ag, Au, or an alloy mainly containing them, instead of the Cu layer 26.

[0035]

As is clear from the above description, according to the present invention, the reliability of the wiring board can be improved, and the production cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first step in one embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a second step in one embodiment of the present invention.

FIG. 3 is a sectional view showing a third step in one embodiment of the present invention.

FIG. 4 is a sectional view showing a fourth step in one embodiment of the present invention.

FIG. 5 is a sectional view showing a fifth step in one embodiment of the present invention.

FIG. 6 is a schematic configuration diagram for explaining a gas deposition method according to one embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a step of forming a multilayer wiring board by providing a thin interlayer insulating film according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining a step of forming a multilayer wiring board by providing a thick interlayer insulating film according to one embodiment of the present invention.

FIG. 9 is a sectional view showing a first step in a conventional example.

FIG. 10 is a sectional view showing a second step in the conventional example.

FIG. 11 is a sectional view showing a third step in the conventional example.

FIG. 12 is a sectional view showing a fourth step in the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate 12 ... Insulating layer 13, 24 ... Resist film 14, 25 ... Resist opening 15 ... Ti / Pd laminated film 26 ... Cu layer 27 ... Ni film 28 ... Wiring layer

────────────────────────────────────────────────── ─── Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 23/12 H05K 3/24 H05K 3/46 JICST file (JOIS)

Claims (6)

(57) [Claims] A step of forming a first opening corresponding to a desired wiring pattern in a first resist film on a substrate by lithography using a predetermined mask; and forming the first opening and the first opening in the first resist film on the substrate. Forming a first metal fine particle film on the surface of the resist film, forming a second resist film on the first metal fine particle film surface, and forming a second resist film on the second resist film by lithography using the mask. Forming an opening;
A step of forming a metal layer in the second opening by a plating method, a step of forming a second metal fine particle film on the surface of the metal layer and the second resist film, and forming the first resist film and Removing the second resist film and simultaneously removing the first metal fine particle film and the second metal fine particle film at portions other than the portion covering the metal layer. Forming method. 2. The method according to claim 1, wherein the first metal fine particle film and the second metal fine particle film are formed by transporting and blowing metal fine particles generated by an in-gas evaporation method together with an inert gas. 2. The method for forming a wiring layer according to claim 1, wherein: 3. A plating method for forming a metal layer, comprising: electroplating using the first metal fine particle film as a cathode;
2. The method for forming a wiring layer according to claim 1, wherein the method is electroless plating using the metal fine particle film as an underlayer. 4. The method according to claim 1, wherein the second metal fine particle film has at least N
3. The method for forming a wiring layer according to claim 1, wherein the film is formed of one of i, Pd, Pt, Au, and Ag or an alloy mainly composed of these metals. 5. The method according to claim 1, wherein the first metal fine particle film is a multilayer film,
One layer is formed of at least one of Ni, Pd, Pt, Au, and Ag or an alloy mainly composed of these metals, and the other layer is formed of at least one of Ti, Cr or any of these metals. 4. The method for forming a wiring layer according to claim 1, wherein the film is formed of an alloy as a main component. 6. The metal layer is made of at least Cu, Ag, Au.
4. The method for forming a wiring layer according to claim 1, wherein the wiring layer is formed of one of the above metals or an alloy mainly composed of these metals.