KR20000044861A - Method for forming copper metal wire of semiconductor device - Google Patents
Method for forming copper metal wire of semiconductor device Download PDFInfo
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- KR20000044861A KR20000044861A KR1019980061364A KR19980061364A KR20000044861A KR 20000044861 A KR20000044861 A KR 20000044861A KR 1019980061364 A KR1019980061364 A KR 1019980061364A KR 19980061364 A KR19980061364 A KR 19980061364A KR 20000044861 A KR20000044861 A KR 20000044861A
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- Prior art keywords
- hard mask
- copper
- layer
- mask layer
- forming
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 55
- 239000002184 metal Substances 0.000 title claims abstract description 55
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000010949 copper Substances 0.000 title claims description 55
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims description 54
- 229910052802 copper Inorganic materials 0.000 title claims description 54
- 238000001312 dry etching Methods 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 claims description 9
- 229910003902 SiCl 4 Inorganic materials 0.000 claims description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 239000007789 gas Substances 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 45
- 239000011229 interlayer Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000006227 byproduct Substances 0.000 description 4
- 229910021591 Copper(I) chloride Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- OXBLHERUFWYNTN-UHFFFAOYSA-M copper(I) chloride Chemical compound [Cu]Cl OXBLHERUFWYNTN-UHFFFAOYSA-M 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 230000027756 respiratory electron transport chain Effects 0.000 description 2
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
Description
본 발명은 반도체 소자의 구리(Cu) 금속 배선 형성 방법에 관한 것으로, 특히 구리 배선 형성을 위한 건식 식각 공정을 용이하게 하여 양호한 형상(profile)의 구리 배선을 얻을 수 있는 반도체 소자의 구리 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming copper (Cu) metal wiring of a semiconductor device, and particularly to forming a copper metal wiring of a semiconductor device which facilitates a dry etching process for forming copper wiring and thus obtains a good profile copper wiring It is about a method.
일반적으로, 반도체 소자의 집적도 증가에 따른 금속 배선 선폭의 감소는 금속 배선을 통해 흐르는 전류 밀도를 증가시키기 때문에 기존의 알루미늄계(Al) 합금으로 제작하는 금속 배선의 경우 높은 전류 밀도에서의 열악한 전자이동(electromigration; EM) 특성으로 인해 소자의 신뢰성에 문제점을 갖고 있다. 이러한 알루미늄계 합금의 문제점을 해결하기 위해 최근에는 구리를 이용한 금속 배선 제작이 연구중이다. 구리는 알루미늄계 합금의 3 내지 4 μΩ/cm2정도의 비저항 값과 비교하여 1.6 μΩ/cm2의 낮은 비저항 값을 갖기 때문에 반도체 소자의 정보 처리 속도 측면에서 유리할 뿐만 아니라, 기존의 알루미늄 보다 원자량 및 용융점(melting point)이 높은 특성에 기인하여 높은 전류 밀도에서도 전자이동에 대한 저항성이 높은 장점을 갖는다. 그러나, 현재까지는 구리를 이용한 배선 제작시 건식 식각(dry etch)을 이용한 이방성 식각(anisotropic etch) 기술이 실제 소자 제작에 적용되기에는 그 개발 정도가 미흡하다.In general, the decrease in the metal wiring line width due to the increase in the integration density of the semiconductor device increases the current density flowing through the metal wiring, so that in the case of the metal wiring made of a conventional aluminum-based (Al) alloy, poor electron transfer at a high current density (electromigration; EM) has a problem in the reliability of the device. In order to solve the problem of the aluminum-based alloy, the manufacture of metal wiring using copper has recently been studied. Since copper has a low resistivity value of 1.6 μΩ / cm 2 compared to the resistivity value of about 3 to 4 μΩ / cm 2 of aluminum-based alloys, copper is not only advantageous in terms of information processing speed of semiconductor devices, but also lower in atomic weight and higher than conventional aluminum. Due to the high melting point (melting point) has the advantage of high resistance to electron transfer even at high current density. However, until now, anisotropic etching technology using dry etching when manufacturing wires using copper is insufficient in actual device manufacturing.
현재까지 개발된 구리의 이방성 식각 기술로는 플라즈마(plasma)를 이용한 건식 식각, 반응성 이온 식각(Reactive Ion Etching; RIE), 레이저(laser)를 이용한 건식 식각 등의 기술이 있고, 이러한 구리의 이방성 식각 기술은 CCl4, SiCl4/N2, Cl2/NH3/SiCl4/N2와 같이 Cl 을 포함하고 있는 식각계(etchant)를 사용하고 있다. Cl 계 식각계를 사용하는 구리의 건식 식각 경우, 식각 후 발생하는 반응 부산물은 CuClX계의 부산물이며, 이러한 CuClX계의 식각 부산물은 알루미늄의 건식 식각시 발생하는 식각 부산물과 비교하여 증기압(vapor pressure)이 낮은 특성을 갖는다. CuClX계의 증기압 특성을 높여 실제로 적용 가능한 구리의 건식 식각 속도를 얻기 위해서는 약 200 ℃ 이상의 고온 식각 공정이 요구된다. 그러나, 현재 금속 배선 형성 공정에서 사용하고 있는 포토레지스트(photoresist; PR)는 유기계 물질이기 때문에 이러한 200 ℃ 이상의 고온이 요구되는 구리의 건식 식각 공정에서는 적용이 불가능하여 궁극적으로는 구리를 이용한 반도체 소자의 금속 배선 제작 자체가 불가능한 문제점을 갖고 있다.Copper anisotropic etching techniques developed to date include dry etching using plasma, reactive ion etching (RIE), and dry etching using laser, and the like. The technique uses an etchant containing Cl, such as CCl 4 , SiCl 4 / N 2 , Cl 2 / NH 3 / SiCl 4 / N 2 . When Cl-based expression dry etching of the copper used for various fields, and the reaction by-products generated after the etching is a by-product of CuCl X type, this etch by-product of CuCl X system is a vapor pressure (vapor compared to the etch by-products generated during dry etching of an aluminum low pressure). The high temperature etching process of about 200 ° C. or more is required in order to increase the vapor pressure characteristic of CuCl X system to obtain a practical dry etching rate of copper. However, since photoresist (PR), which is currently used in the metal wiring forming process, is an organic material, it is not applicable to the dry etching process of copper requiring a high temperature of 200 ° C. or more, and ultimately, a semiconductor device using copper Metal wiring fabrication itself has a problem that is impossible.
구리에 관련된 참고 문헌으로 'S.L.Cohen, M.Lieher, and S.Kasi Appl. Phys. Lett., 60(1), pp. 50 (1992)' 및 'A.Jain, K.M.Chi, T.T.Kodas, and M.J.Hampden-Smith, K. Electrochem. Soc., 140(5), pp. 1435 (1993)'이 있다.References related to copper include S. L. Cohen, M. Lieher, and S. Kasi Appl. Phys. Lett., 60 (1), pp. 50 (1992) and A. Jain, K. M. Chi, T. T. Kodas, and M. J. Hamden-Smith, K. Electrochem. Soc., 140 (5), pp. 1435 (1993) '.
따라서, 본 발명은 구리 배선 형성을 위한 건식 식각 공정을 고온에서 양호한 형상의 구리 배선을 제작할 수 있게 하여, 소자의 동작 특성 개선과 더불어 소자의 신뢰성을 높일 수 있는 반도체 소자의 구리 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention provides a method for forming a copper metal wiring of a semiconductor device, which enables a dry etching process for forming copper wiring to produce a copper wiring having a good shape at a high temperature, thereby improving the operation characteristics of the device and increasing the reliability of the device. The purpose is to provide.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 구리 금속 배선 형성 방법은 비아 콘택홀이 형성된 반도체 기판이 제공되는 단계; 상기 비아 콘택홀을 포함한 전체 구조상에 배리어 금속층 및 구리층을 순차적으로 형성하는 단계; 상기 구리층 상에 하드 마스크층을 형성하는 단계; 상기 하드 마스크층 상에 포토레지스트 패턴을 형성한 후, 포토레지스트 패턴을 이용하여 상기 하드 마스크층을 식각하고, 이로 인하여 하드 마스크층 패턴이 형성되는 단계; 상기 포토레지스트 패턴을 제거한 후, 상기 하드 마스크층 패턴을 식각 마스크로 한 건식 식각 공정으로 상기 구리층 및 배리어 금속층을 순차적으로 식각하고, 이로 인하여 구리 금속 배선이 형성되는 단계; 및 상기 하드 마스크층 패턴을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, a method of forming a copper metal wiring of a semiconductor device according to the present invention includes providing a semiconductor substrate having a via contact hole; Sequentially forming a barrier metal layer and a copper layer on the entire structure including the via contact hole; Forming a hard mask layer on the copper layer; Forming a photoresist pattern on the hard mask layer, and then etching the hard mask layer using the photoresist pattern, thereby forming a hard mask layer pattern; Removing the photoresist pattern and sequentially etching the copper layer and the barrier metal layer by a dry etching process using the hard mask layer pattern as an etching mask, thereby forming a copper metal wiring; And removing the hard mask layer pattern.
도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 구리 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1F are cross-sectional views of a device for explaining a method of forming a copper metal wire in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 반도체 기판 12: 층간 절연막11: semiconductor substrate 12: interlayer insulating film
13: 하부 금속 배선 14: 금속 층간 절연막13: lower metal wiring 14: metal interlayer insulating film
15: 비아 콘택홀 16: 배리어 금속층15: via contact hole 16: barrier metal layer
17: 구리층 18: 하드 마스크층17: copper layer 18: hard mask layer
18A: 하드 마스크층 패턴 19: 포토레지스트 패턴18A: Hard Mask Layer Pattern 19: Photoresist Pattern
170: 구리 금속 배선170: copper metal wiring
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 구리 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1F are cross-sectional views of devices for explaining a method of forming a copper metal wire in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(11)상에 층간 절연막(12)을 형성하고, 층간 절연막(12)상에 하부 금속 배선(13)을 형성한다. 하부 금속 배선(13)을 포함한 층간 절연막(12)상에 금속 층간 절연막(14)을 형성하고, 금속 배선 콘택 마스크를 사용한 식각 공정으로 금속 층간 절연막(14)의 일부분을 식각 하여 하부 금속 배선(13)의 표면이 노출되는 비아 콘택홀(15)을 형성한다.Referring to FIG. 1A, an interlayer insulating layer 12 is formed on a semiconductor substrate 11 on which various elements for forming a semiconductor element are formed, and a lower metal wiring 13 is formed on the interlayer insulating layer 12. A metal interlayer insulating film 14 is formed on the interlayer insulating film 12 including the lower metal wiring 13, and a portion of the metal interlayer insulating film 14 is etched by an etching process using a metal wiring contact mask to etch the lower metal wiring 13. The via contact hole 15 is formed to expose the surface.
도 1b를 참조하면, 비아 콘택홀(15)을 포함한 금속 층간 절연막(14)상에 배리어 금속층(barrier metal layer; 16) 및 배선용 구리층(17)을 순차적으로 형성한다.Referring to FIG. 1B, a barrier metal layer 16 and a wiring copper layer 17 are sequentially formed on the metal interlayer insulating layer 14 including the via contact hole 15.
상기에서, 배리어 금속층(16)은 구리층(17)으로부터 구리 이온이 금속 층간 절연막(14)으로 확산되는 것을 방지하면서, 구리층(17)의 금속 층간 절연막(14)에 대한 접착력을 향상시키기는 역할을 하며, 물리기상증착(PVD) 스퍼터링 공정이나 화학기상증착(CVD) 공정으로 타이타늄나이트라이드(TiN)나 탄탈륨나이트라이드(TaN)를 100 내지 1000Å의 두께로 증착하여 형성한다. 구리층(17)은 비아 콘택홀(15)을 충분히 매립할 수 있도록 콘택에 대한 매립 특성이 우수한 공정을 적용하여 구리를 6000 내지 12000Å의 두께로 형성하되, 그 증착 공정은 금속-유기계 전구체(metal-organic precursor)를 이용한 화학기상증착(MOCVD) 공정이나, 전기도금(electroplating) 공정이 사용될 수 있다.In the above, the barrier metal layer 16 prevents the diffusion of copper ions from the copper layer 17 into the metal interlayer insulating film 14, while improving the adhesion to the metal interlayer insulating film 14 of the copper layer 17. It is formed by depositing a titanium nitride (TiN) or tantalum nitride (TaN) to a thickness of 100 to 1000 으로 by physical vapor deposition (PVD) sputtering process or chemical vapor deposition (CVD) process. The copper layer 17 is formed to have a thickness of 6000 to 12000 kPa by applying a process having excellent buried characteristics to the contact so as to fully fill the via contact hole 15, the deposition process is a metal-organic precursor (metal) chemical vapor deposition (MOCVD) process using an organic precursor or an electroplating process may be used.
도 1c를 참조하면, 구리층(17)상에 하드 마스크층(hard mask layer; 18)을 형성한다.Referring to FIG. 1C, a hard mask layer 18 is formed on the copper layer 17.
상기에서, 하드 마스크층(18)은 플라즈마 증가형 화학기상증착(PECVD) 방식으로 실리콘나이트라이드(Si3N4)를 2000 내지 6000Å의 두께로 전면 증착하여 형성된다. 하드 마스크층(18)으로 실리콘나이트라이드를 증착할 때, 일반적인 화학기상증착법으로 증착할 수 있으나, 본 발명에서는 가능한 낮은 온도 범위에서 증착 공정이 진행되도록 플라즈마 증가형 화학기상증착법을 적용한다. 실리콘나이트라이드 하드 마스크층(18)은 후에 구리층을 식각할 때 사용되는 Cl 계 식각계와의 식각 선택비(etch selectivity)를 고려하여 적절한 두께 범위로 선택하여 증착할 수 있다.In the above, the hard mask layer 18 is formed by depositing silicon nitride (Si 3 N 4 ) in a total thickness of 2000 to 6000 kPa by a plasma enhanced chemical vapor deposition (PECVD) method. When depositing the silicon nitride with the hard mask layer 18, it can be deposited by a general chemical vapor deposition method, the present invention applies a plasma enhanced chemical vapor deposition method to proceed the deposition process in the lowest temperature range possible. The silicon nitride hard mask layer 18 may be selected and deposited in an appropriate thickness range in consideration of an etch selectivity with a Cl-based etching system used when etching the copper layer later.
도 1d를 참조하면, 하드 마스크층(18) 상에 포토레지스트를 전면 코팅한 후, 금속 배선 레티클(reticle)을 사용한 노광 공정을 실시하고, 현상 공정을 통해 포토레지스트 패턴(19)을 형성한다. 포토레지스트 패턴(19)을 식각 마스크로 한 건식 식각 공정을 실시하여 하드 마스크층(18)을 식각하고, 이로 인하여 하드 마스크층 패턴(18A)이 구리층(17) 상에 형성된다. 실리콘나이트라이드 하드 마스크층(18)의 건식 식각 공정은 플루오린(fluorine)계 식각계인 NF3, SF6또는 CF4의 식각 가스를 사용한다.Referring to FIG. 1D, after the photoresist is completely coated on the hard mask layer 18, an exposure process using a metal wiring reticle is performed, and a photoresist pattern 19 is formed through a developing process. The dry etching process using the photoresist pattern 19 as an etching mask is performed to etch the hard mask layer 18, whereby the hard mask layer pattern 18A is formed on the copper layer 17. The dry etching process of the silicon nitride hard mask layer 18 uses an etching gas of NF 3 , SF 6, or CF 4 , which is a fluorine-based etching system.
도 1e를 참조하면, 포토레지스트 패턴(19)을 제거한 후, 하드 마스크층 패턴(18A)을 식각 마스크로 한 건식 식각 공정으로 구리층(17) 및 배리어 금속층(16)을 순차적으로 식각하고, 이로 인하여 구리 금속 배선(170)이 형성된다. 구리층(17)의 건식 식각 공정은 CCl4, SiCl4/N2, Cl2/NH3/SiCl4/N2와 같이 Cl 을 포함하고 있는 식각계(etchant)를 사용한다.Referring to FIG. 1E, after the photoresist pattern 19 is removed, the copper layer 17 and the barrier metal layer 16 are sequentially etched by a dry etching process using the hard mask layer pattern 18A as an etching mask. Due to this, the copper metal wiring 170 is formed. The dry etching process of the copper layer 17 uses an etchant containing Cl, such as CCl 4 , SiCl 4 / N 2 , Cl 2 / NH 3 / SiCl 4 / N 2 .
도 1f를 참조하면, 하드 마스크층 패턴(18A)을 제거하여 구리 금속 배선 제작 공정을 완료한다. 실리콘나이트라이드 하드 마스크층 패턴(18)의 제거 공정은 플루오린계 식각계를 사용한 건식 식각이나 H3PO4용액을 이용한 습식 식각 방식으로 진행한다.Referring to FIG. 1F, the hard mask layer pattern 18A is removed to complete a copper metal wiring fabrication process. The silicon nitride hard mask layer pattern 18 may be removed by a dry etching method using a fluorine-based etching system or a wet etching method using a H 3 PO 4 solution.
상기한 본 발명은 기판 전면에 증착된 구리층 위로 기존의 금속 배선 형성을 위해 사용하던 유기계 포토레지스트 코팅 공정에 앞서 플라즈마 증가형 화학기상증착 공정으로 실리콘나이트라이드막을 증착하고, 이 실리콘나이트라이드막 위에 포토레지스트 패턴을 형성하고, 포토레지스트 패턴을 이용하여 실리콘나이트라이드막을 식각하고, 실리콘나이트라이드막 패턴을 하드 마스크층으로 한 고온 건식 식각 공정으로 구리층을 식각 하여 구리 금속 배선을 제작한다.The present invention described above deposits a silicon nitride film by a plasma enhanced chemical vapor deposition process prior to the organic photoresist coating process used to form a conventional metal wiring on the copper layer deposited on the entire surface of the substrate, and on the silicon nitride film A photoresist pattern is formed, the silicon nitride film is etched using the photoresist pattern, and the copper layer is etched by a high temperature dry etching process using the silicon nitride film pattern as a hard mask layer to produce a copper metal wiring.
상술한 바와 같이, 본 발명은 256M DRAM 이상의 고집적 소자 제작에 있어서 기존의 구리 금속 배선 제작시 문제가 되고 있는 고온에서의 건식 식각 문제를 해결하므로써, 실제 소자 제작시에 구리 금속 배선을 용이하게 형성할 수 있어, 2층 이상의 다층 금속 배선 구조를 갖는 소자에서 금속 배선의 비저항이 낮아 정보 처리 속도가 우수하고, 집적도 증가에 따른 배선 선폭의 감소와 더불어 문제시되는 높은 전류 밀도에 대해 기존의 알루미늄계 합금의 금속 배선이 갖는 열악한 전기이동 특성을 개선할 수 있으므로 소자의 동작 특성 개선과 더불어 소자의 신뢰성을 높일 수 있다.As described above, the present invention solves the problem of dry etching at high temperature, which is a problem in manufacturing a conventional copper metal wiring in fabricating a highly integrated device of 256M DRAM or more, thereby easily forming copper metal wiring in actual device fabrication. It is possible to improve the information processing speed due to the low resistivity of the metal wiring in devices having a multi-layered metal wiring structure of two or more layers, and to reduce the wiring line width due to the increase in the density, and to solve the problem of high current density. Since the poor electrophoretic characteristics of the metal wiring can be improved, the operation characteristics of the device and the reliability of the device can be improved.
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| KR100586067B1 (en) * | 1999-06-23 | 2006-06-07 | 매그나칩 반도체 유한회사 | Method For Forming The CU Metal Line Using Electroplating |
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| KR102030797B1 (en) | 2012-03-30 | 2019-11-11 | 삼성디스플레이 주식회사 | Manufacturing method for thin film transistor array panel |
| KR102081614B1 (en) | 2018-03-29 | 2020-02-26 | 인하대학교 산학협력단 | Method for Dry Etching of Copper Thin Films |
| KR102030548B1 (en) | 2018-11-15 | 2019-10-10 | 인하대학교 산학협력단 | Method for Dry Etching of Copper Thin Films |
| KR101977132B1 (en) | 2018-12-28 | 2019-05-10 | 인하대학교 산학협력단 | Method for Dry Etching of Copper Thin Films |
| KR102073050B1 (en) | 2019-09-19 | 2020-02-04 | 인하대학교 산학협력단 | Method for Dry Etching of Copper Thin Films |
| KR102562321B1 (en) | 2020-11-13 | 2023-08-01 | 인하대학교 산학협력단 | Method for Dry Etching of Copper Thin Films |
| KR102428640B1 (en) | 2021-02-22 | 2022-08-02 | 인하대학교 산학협력단 | Method for Dry Etching of Copper Thin Films |
| KR102574751B1 (en) | 2021-12-07 | 2023-09-06 | 인하대학교 산학협력단 | Method for Dry Etching of Copper Thin Films |
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| JPH01308028A (en) * | 1988-06-07 | 1989-12-12 | Fujitsu Ltd | Formation of copper or copper alloy electrode wiring |
| JPH02123740A (en) * | 1988-11-02 | 1990-05-11 | Mitsubishi Electric Corp | Semiconductor device |
| JPH05102152A (en) * | 1991-10-11 | 1993-04-23 | Sony Corp | Semiconductor device |
| JPH0729908A (en) * | 1993-07-15 | 1995-01-31 | Nec Corp | Formation of copper fine wiring |
| KR0148325B1 (en) * | 1995-03-04 | 1998-12-01 | 김주용 | Formation method of metal layer in semiconductor device |
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