TW502335B - Method for controlling the line width of polysilicon gate by an etching process of a hard mask layer - Google Patents

Abstract

The present invention discloses a method for producing a semiconductor device, which comprises providing a semiconductor substrate formed thereon a gate dielectric layer; forming a polysilicon layer on the gate dielectric layer; forming a dielectric layer having a first thickness on the polysilicon layer; forming and defining a photoresist layer on the dielectric layer; using the photoresist layer as an etching mask and an etchant consisting of a mixture of at least a C2F6 and a CH2F2 to etch the dielectric layer and overetch the polysilicon layer to a second thickness to form a hard masking layer having a trapezoidal profile, in which the second thickness is about half the first thickness; removing the photoresist layer; and using a hard mask layer as an etching mask to etch the polysilicon layer to form a polysilicon gate.

Description

502335 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for forming a polycrystalline silicon gate, and more particularly to a method for controlling the critical size of a polycrystalline silicon gate by etching a hard mask layer. 5-2 Background of the Invention: As the density of integrated circuits continues to increase, the only way to keep the chip area (ch ip) the same or even to reduce the unit cost of the circuit is to continuously reduce the circuit design specifications (Designru 1 e) ^ in line with the future development trend of the southern technology industry. With the development of semiconductor technology, the size of integrated circuit components has been reduced to the sub-micron range. When the semiconductor is continuously reduced to the deep sub-micron range, some problems in the process shrinkage arise. Advances in integrated circuits have involved the downsizing of component geometries. In sub-micron semiconductor technology, smaller and smaller critical dimensions of polycrystalline silicon gates are required. In order to expand the lithography process window, it is necessary to reduce the thickness of the photoresist layer to form a thinner photoresist layer. Therefore, in the polysilicon gate integration process, the demand for a hard mask layer is more important. Since the choice between oxide and polycrystalline silicon is relatively high, traditionally, an oxide etching reaction chamber is used for the hard mask etching process. However, this approach often results in critical dimensions in the wafer

502335 V. Description of the invention (2) The consistency of the inch is not good. In addition, in order to control the remaining contour in the #etching process, a hard mask etching process such as C 2F 6 is usually performed using a reactive gas having a carbon-to-fluorine ratio (C / F). Because the reaction gas with a carbon-to-fluorine ratio (C / F) is not good in the selection ratio between the hard mask layer and the polycrystalline silicon, the surface consistency of the polycrystalline silicon layer is also not good, and the surface difference is about 1700 Angstroms to Between 2000 angstroms, that is, the surface uniformity is greater than 2000, which will increase the difficulty of subsequent etching processes. In addition, during the hard mask etching process, a polycrystalline silicon layer that is about half the thickness of the hard mask layer will be over-etched. At this time, the polycrystalline silicon layer under the hard mask layer will consume too much, as shown in the first figure. . In addition, the insect mask is usually in the same substrate specifications as the main substrate layer, oxidizes the foot, and electrically shields the hard cover of the small homogeneous phase. Therefore, during the manufacturing process, (the thickness of the design layer is offset from the subsequent, the layer has the same size but the width of the polar line. Because of the endpoint of the crystalline silicon layer, the upper gate oxide layer is controlled) Ion implantation reduces the fixed critical scale in the rest of the time. Therefore, the smaller the thickness of the oxide layer on the surface, the smaller the thickness of the oxide layer. The smaller the shape of the vertical wheel polycrystalline silicon, the larger the uniformity of the transfer process. During the manufacturing process, a large amount of damage control by the I-worm through the extremely thin engraving process is equivalent, which is formed. In the case of brakes, there is significant reproducibility. Profile. Although after layering, the crystals are larger than the dense polycrystals, the gate oxygen is lost by the end of the etching. Locally important oxidant oxidation affects the other side on the mask circle. The gate hard shield layer is difficult to determine the depth of the layer to be removed, especially the thickness of the layer, the thickness, or the surface. The crystalline silicon gate process in the line isolation area on the worm is regarded as a break. The semi-conductive crystal crushed rice is set to a thinner multipolar wire that does not cause a widening after the engraving.

502335 V. Description of the invention (3) Not only the manufacturing process is complex and it is difficult to control the thickness of the oxide layer, nor can it be reworked, which will increase the huge manufacturing cost. In view of the above reasons, we need a new etching process for the hard masking layer of the polycrystalline silicon gate, in order to improve the yield and yield of the subsequent processes. 5-3 Purpose and summary of the invention: In view of the above background of the invention, The traditional polycrystalline silicon gate hard mask etching process has many disadvantages. The present invention provides a method to overcome the problems of the traditional process. The main object of the present invention is to provide an etching process for a hard mask layer of a polycrystalline silicon gate. The invention uses an air mixture as a new etchant to perform the etching process of the hard masking layer of the polycrystalline silicon gate to increase the #etch selection ratio between the polycrystalline silicon layer and the hard masking layer. In addition, better surface uniformity of the polycrystalline silicon layer can be obtained after #etching the polycrystalline silicon layer, so that the etching endpoint between the subsequent polycrystalline silicon layer and the gate oxide layer can be accurately measured, and at the same time, the polycrystalline silicon layer can be reduced. loss. Therefore, the present invention can reduce the cost of the traditional process to meet economic benefits. Another object of the present invention is to provide an etching process for a polycrystalline silicon gate.

502335 V. Description of the invention (4). The method can use a CH 2F and C 2F 妁 gas mixture as an etchant to perform a hard mask etching process to form a hard mask having a trapezoidal profile. In addition, the present invention can also control the trapezoidal contour size of the hard cover layer by the amount of CH 2F fishing content, thereby controlling the critical size of the polycrystalline silicon gate, so that the polycrystalline silicon gate line width can be freely shifted in the isolated region and the dense region. . Therefore, this method can be applied to deep sub-micron technology of semiconductor elements. According to the above-mentioned object, the present invention discloses a new method for manufacturing a semiconductor device. First, a semiconductor substrate is provided with a gate dielectric layer thereon. Then, a polycrystalline silicon layer is formed on the gate dielectric layer. Next, a dielectric layer having a first thickness is formed on the polycrystalline silicon layer. Thereafter, a photoresist layer is formed and defined on the dielectric layer. The photoresist layer is used as an etch mask and a mixed gas containing at least one C 2F and a CH 2F A is used as a post-etching agent I and a poly-etched dielectric layer is over-etched to consume a second thickness. To form a hard mask layer with a trapezoidal profile, the second thickness is about half of the first thickness. Subsequently, the photoresist layer is removed. Then, the hard mask layer is used as a touch-engraved mask I to etch the polycrystalline stone layer to form a polycrystalline stone gate. 5-4 Detailed Description of the Invention: The present invention is directed to a method for manufacturing a residual polymer. In order to thoroughly understand the present invention, detailed descriptions will be provided in the following description.

502335 V. Description of the invention (5) Exhaustive steps and components. Obviously, the practice of the present invention is not limited to the specific details familiar to those skilled in semiconductor devices. On the other hand, well-known process steps and components have not been described in detail to avoid unnecessary limitations of the present invention. The preferred embodiments of the present invention will be described in detail as follows. However, in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, which is subject to the scope of subsequent patents. . Referring to FIGS. 2A to 2D, in a first embodiment of the present invention, a semiconductor substrate 200 is first provided. The semiconductor substrate 200 has a first dielectric layer 210 and a polycrystalline silicon layer 22 thereon. 0A, wherein the first dielectric layer 210 includes at least an oxide layer. Then, a second dielectric layer 230 is formed on the polycrystalline silicon layer 220A. The second dielectric layer 230 includes at least an oxide layer. Next, a photoresist layer 240 is formed and defined on the second dielectric layer 230. The photoresist layer 2 40 is used as an etching mask and an etchant to perform an etching process to etch the second dielectric layer 2 3 0 until the polycrystalline silicon layer 2 2 0 A is over-etched to a predetermined thickness to form a layer having A trapezoid-shaped hard mask layer 250, wherein the insecticide I includes at least a reaction gas having a carbon-to-fluorine ratio, for example, C 2F 6 and a reaction gas having a hydrocarbon-to-fluorine ratio, for example, CH 2F 2. The width of the trapezoidal profile of the mask layer 2 50 is determined by the content of the reaction gas having a hydrocarbon-to-fluorine ratio. When the content of the reaction gas of the fluorocarbon ratio is higher, the width of the trapezoidal contour of the hard mask layer 250 is larger. Subsequently, the photoresist layer 240 is removed. Next, the polycrystalline silicon layer 2 2 0 A is etched with the hard mask layer 2 50 as an etching mask to form a poly silicon region 2 2 0 B. Finally, the hard mask layer 250 is removed to form a polycrystalline silicon gate.

502335 V. Description of the invention (6) 2 2 0C. Referring to FIG. 3A and FIG. 3B, in a second embodiment of the present invention, a semiconductor substrate 300 is first provided. The semiconductor substrate 300 has a gate oxide layer 3 1 0 thereon. Then, a polycrystalline silicon layer 3 2 0 is formed on the gate oxide layer 3 1 0. Then, an oxide layer 3 3 0 having a first thickness is formed on the polycrystalline silicon layer 3 2 0. Next, a plurality of first photoresist layers 3408 and a plurality of second photoresist layers 3 4 0 B are formed and defined on the oxide layer 3 3 0, where the positions of the plurality of first photoresist layers 340 A are The isolation region is 300A, and the location of the plurality of second photoresist layers 340B is the dense region 300B. An etching process is performed by using the plurality of first photoresist layers 340A and the plurality of second photoresist layers 340B as a plurality of etching masks and a combined gas as an etchant to etch the oxide layer 3 3 0 until passing. The polycrystalline silicon layer 32 is etched until a second thickness of the polycrystalline silicon layer 3 2 0 is removed, and a plurality of first hard masks I 3 5 0A and a plurality of second hard masks 35 having a trapezoidal profile are formed. 〇B, where the mixed gas contains at least two, a CJ good reaction gas and a dF A reaction gas, and a trapezoidal contour field with a double-shielding layer 35A and a plurality of second hard-shielding layers 350B; 2 series of measures With CH2F & gas content determination, when the gas content of CHJ is higher, the width of the trapezoidal contours of the plurality of first hard shielding layers 35 OA and the plurality of second hard shielding layers 3 is larger, thereby controlling the polycrystalline silicon gate Outside the second line, there are multiple first hard masking layers 3500 recorded in the isolated area 3 0A ”Several second hard masking layers 3 5 0 Β are located in the dense area 3 0 0 Β, and complex — The sound is reduced by half. On the other hand, a plurality of first hard cover layers 35〇A ′ and a younger one hard cover layer 3 5 0 Β can also be used by additional Optical lithography

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502335 V. Description of the invention (7) Form trapezoidal contours with different offsets. Referring to FIGS. 3C and 3D, in the second embodiment of the present invention, the plurality of first photoresist layers 3 4 0 A and the plurality of second photoresist layers 3 4 0 B are removed. Next, an etching process is performed by using the plurality of first hard mask layers 3 5 0 A and the plurality of second hard mask layers 3 5 0 B as a plurality of etching masks to etch the polycrystalline silicon layer 3 2 0 and form a plurality of first A polycrystalline silicon region 3 2 0 A and a plurality of second polycrystalline silicon regions 3 2 0 B, wherein the plurality of first polycrystalline silicon regions 3 2 0 A are located in the isolated region 3 0 0 A and a plurality of first polycrystalline silicon regions 3 2 0 A. The second polycrystalline silicon region 3 2 0 B is located in the dense region 3 0 B. Finally, the plurality of first hard mask layers 3 5 0 A and the plurality of second hard mask layers 3 5 0 B are removed to form a plurality of first polycrystalline silicon gates 3 6 0 A in the isolation region 3 0 0 A The upper and plural second polysilicon gates 3 6 0 B are connected to the dense area 3 0 0 B. As described above, in the embodiment of the present invention, the present invention uses a gas mixture as a new etchant to perform the etching process of the hard masking layer of the polycrystalline silicon gate to increase the etching choice between the polycrystalline silicon layer and the hard masking layer. In particular, the etching selection ratio of the traditional process is less than about 1.5. In contrast, the method can increase the etching selection ratio to more than about 5. In addition, better surface uniformity of the polycrystalline silicon layer can be obtained after over-etching the polycrystalline silicon layer, so that the end point of the etching between the subsequent polycrystalline silicon layer and the gate oxide layer can be accurately measured to prevent the gate oxide layer from being eroded, and at the same time The loss of the polycrystalline silicon layer can be reduced. The surface uniformity of the traditional process is greater than about 200. In contrast, the method can reduce the surface uniformity to less than about 50. Therefore, the present invention can reduce the cost of the traditional process to meet the economic benefits. Furthermore, this method can be combined with a CH 2F and

Page 10 502335 V. Description of the invention (8) The C 2F 妁 gas mixture is used as an etchant to perform a hard mask etching process to form a hard mask having a trapezoidal profile. In addition, the present invention can also control the trapezoidal profile size of the hard cover layer by the amount of CH 2F fishing content, thereby controlling the critical size of the polycrystalline silicon gate, so that the polycrystalline silicon gate line width in the isolated area and the dense area can be freely Offset. Therefore, the control window for the critical dimension shift is more extensive. Therefore, this method can be applied to deep sub-micron technology of semiconductor elements. Of course, the present invention may be applied to an etching process of a hard masking layer of a polycrystalline silicon layer, and may also be applied to an etching process of any semiconductor. Moreover, the present invention uses the CH 2F A content of the reactive gas to control the critical size of the polycrystalline silicon gate, and has not yet been developed for use in the #engraving process of the polycrystalline stone layer. For deep sub-micron processes, this method is a better and feasible polycrystalline silicon gate process. Obviously, according to the description in the above embodiments, the present invention may have many modifications and differences. Therefore, it needs to be understood within the scope of the appended claims. In addition to the above detailed description, the present invention can be widely implemented in other embodiments. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following application patents Within range

The 502335 diagram on page 11 simply illustrates that the first diagram is a cross-sectional view of a conventional polycrystalline silicon layer etching process; the second diagram A to the second D diagram are the first preferred embodiment according to the present invention. A cross-sectional view of the process of forming a hard mask layer by an etchant; and Figures A through D through D are the second preferred embodiment according to the present invention. Process cross-sectional view of the critical dimensions of the spar xi gate. Representative symbols of main parts: 200 semiconductor substrate 210 first dielectric layer 2 2 0A polycrystalline silicon layer 2 2 0B polycrystalline silicon region 2 2 0C polycrystalline silicon gate 230 second dielectric layer 240 photoresist layer 250 hard mask layer 300 semiconductor substrate 3 0 0A Isolation area 3 0 0B Dense area 310 Gate oxide layer 320 Evening silicon layer 3 2 0 A First polycrystalline silicon area

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Claims (1)

502335 VI. Application Patent Scope 1. A method for etching a hard mask layer, the etching method includes at least the following steps to provide a semiconductor substrate, the semiconductor substrate having a polycrystalline silicon layer thereon; forming a dielectric layer on the polycrystal On the Shi Xi layer, a photoresist layer is formed on the dielectric layer; a mixed gas having a HC ratio is used as a #etching agent; and the photoresist layer is used as a #etching mask and the # 刻 剂 Touches the dielectric layer and forms a hard mask layer with a trapezoidal profile. 2. The method for etching a hard mask layer as described in item 1 of the scope of patent application, wherein the dielectric layer includes at least an oxide layer. 3. The method for etching a hard mask layer as described in item 1 of the scope of the patent application, wherein the gas having a hydrocarbon-to-hydrogen ratio described above contains at least one CH2F2. 4. The method for etching a hard mask layer as described in item 1 of the scope of the patent application, wherein the width of the trapezoidal contour of the hard mask layer is determined by the gas content having a hydrocarbon ratio. 5. A method for etching a polycrystalline silicon layer, the method including at least the following steps: providing a semiconductor substrate having a first dielectric layer on the semiconductor substrate; Page 14 502335 6. The scope of the patent application forms a polycrystalline silicon layer on the first dielectric layer; forms a second dielectric layer on the polycrystalline silicon layer; forms a photoresist layer on the second dielectric layer Providing a mixed gas having a fluorocarbon ratio and a fluorocarbon ratio as an etchant; using the photoresist layer as an etching mask and the etchant to etch the second dielectric layer until the polycrystalline silicon layer is over-etched Up to a predetermined thickness and forming a hard mask layer with a trapezoidal profile; removing the photoresist layer; and etching the polycrystalline silicon layer by using the hard mask layer as an etching mask to form a polycrystalline silicon region in the On the first dielectric layer. 6. The method of engraving a polycrystalline stone layer as described in item 5 of the scope of patent application, wherein the first dielectric layer includes at least an oxide layer. 7. The method as claimed in item 5 of the scope of patent application, wherein the second dielectric layer includes at least an oxide layer. 8. The method for etching a polycrystalline silicon layer as described in item 5 of the scope of the patent application, wherein the above-mentioned gas having a carbon-to-fluorine ratio includes at least one C 2F 6. 9. The method for etching a polycrystalline silicon layer as described in item 5 of the scope of the patent application, wherein the gas having a hydrocarbon-to-hydrogen ratio mentioned above contains at least one CH2F2. Page 15 502335 6. Application scope of patent 10. The method for etching a polycrystalline silicon layer as described in item 5 of the scope of application for patent, wherein the width of the trapezoidal profile of the hard mask layer is determined by the gas content having a hydrocarbon ratio. Decide. 11. A method for controlling the line width of a plurality of polycrystalline silicon gates, the method for controlling the line width includes at least the following steps: providing a semiconductor substrate having a gate oxide layer on the semiconductor substrate; forming a polycrystalline stone Layer on the gate oxide layer; forming a dielectric layer having a first thickness on the polycrystalline silicon layer; forming a plurality of photoresist layers on the dielectric layer; providing a CH 2F & mixed gas as a Etchant; using the plurality of photoresist layers as a plurality of #etching masks and the #etching agent I etch the dielectric layer until I etch the polycrystalline stone layer to remove a portion of a second thickness Up to the polycrystalline silicon layer, and form a plurality of hard mask layers having a trapezoidal profile on the polycrystalline silicon layer, wherein the width of the trapezoidal profile of the plurality of hard masking layers controls the line width of the plurality of polycrystalline silicon gates; removing the plurality of polysilicon gates; A photoresist layer; etching the polycrystalline silicon layer by using the plurality of hard mask layers as a plurality of etching masks to form a plurality of polycrystalline silicon regions; and removing the plurality of hard mask layers to form the plurality of polycrystalline silicon gates. 1 2. The method for controlling the line width of a plurality of polysilicon gates as described in item 11 of the scope of the patent application, wherein the dielectric layer includes at least an oxide layer. Page 16 502335 6. Scope of patent application 1 3. The method for controlling the line width of a plurality of polysilicon gates as described in item 11 of the scope of patent application, wherein the second thickness is about half of the first thickness. 14. The method for controlling the line width of a plurality of polysilicon gates as described in item 11 of the scope of the patent application, wherein the width of the trapezoidal contour of the plurality of hard shielding layers is determined by the CH2F2 content. 1 5. —A method for controlling the line width of a plurality of polycrystalline silicon gates. The method for controlling the line width of a plurality of polycrystalline silicon gates includes at least the following steps: Provide a semiconductor substrate having a gate oxide on the semiconductor substrate. Forming a polycrystalline broken layer on the gate oxide layer; forming an oxide layer having a first thickness on the polycrystalline silicon layer; forming a plurality of first photoresist layers and a plurality of second photoresist layers on the On the oxide layer, the location of the plurality of first photoresist layers is defined as a lone region, and the location of the plurality of second photoresist layers is a dense region; a C 2F and a CH 2F are provided. The mixed gas is used as an etchant, and the first photoresist layer and the second photoresist layer are used as a plurality of engraved masks and the remaining etching agent to etch the oxide layer until the polycrystalline silicon layer is removed. Except for a portion of the polycrystalline silicon layer having a second thickness, a plurality of first hard mask layers having a trapezoidal profile are formed in the lone region and the plurality of first Page 17 502335 VI. The number of patent applications includes the body and the air layer ^ Shield β i Η Hard c-The first and second borrowing numbers are used to restore the width and the layer of the wheel on the corridor. The second layer of the second hard layer is light-shielded by the second layer of the hard layer. The silicon and crystal layers are multi-blocked. The first number of the digital control is divided by the number. Determine the silicon when the crystal layer is more hidden, the second number is a complex number, and it is harder than the layer of the broken crystal, the first etched number is covered by the screen, and the moment is borrowed by the number. In the first episode of the region, the dense number is in the digital complex system, and the crystals are broken in the region. In the multi-region second crystal, the majority is in the second complex number. Second, the first and second areas are separated from the solitary layer and the layer at the shield electrode. The multi-density number of the first crystal set of the silicon region on the hard gate is the complex divisor. The silicon is shifted to the extreme divisor, and the crystal is formed into an extreme gate thickness of one of the width and half lines. The thickness of the degree is described in item 5 of the two institutes. The first paragraph is described in the upper circle of Fan Qili. Page 18