TW388068B - A new process for preventing the spacer of polysilicon gate and the surface of active area from etching damage - Google Patents

Abstract

When the line width of a CMOS device evolves into 0.18 <mu> m or smaller, a SiON layer is generally used as a bottom anti-reflection coating to increase the process window of the photolithography process for defining the poly sillcon gate. However, when the SiON layer is removed subsequently by etching, it is likely to damage the gate oxide layer. Alternatively, if the SiON layer is removed by hot phosphoric acid solution, the spacer of the polysilicon gate and the surface of the active area may be damaged. The characteristic of product is thus negatively influenced. The present invention provides an improved process, which carries out a wet chemical oxidation reaction process after defining the patterns of the gate oxide layer and polysilicon gate layer by etching, so as to form a thin protection layer on the surface of the spacer and substrate. When the hot phosphoric acid solution is used to etch off the SiON layer subsequently, the etching solution can be effectively isolated, such that the spacer of polysilicon gate and the surface of active area are protected from etching damage.

Description

V. Description of the invention (1) The present invention relates to the manufacture of semiconductor integrated circuits, and in particular, the complementary metal-oxygen half element improvement using the oxynitride phase 10N) layer as the bottom anti-reflection layer, # βΐ. JL &gt; ^ T also creates a protective layer to prevent the silicon gate sidewall and active area surface from being damaged by etching. Preventing the production of semiconductor integrated circuits (1C) is an extremely complicated process. The purpose is to reduce the production of various electronic components and circuits required for specific circuits on a small-area substrate. In today's semiconductor integrated circuit manufacturing process, photolithography is a very critical step. Whether it can accurately transfer the designed circuit pattern to the semiconductor substrate is an important factor that determines the quality of the product. Generally speaking, lithography procedures include: coating photoresist, exposure, development, and removal of photoresist. Among them, the required solution of the component is first made on a photomask, and then an exposure program is used to make a photochemical reaction in the area of the photoresist that is not covered by the photomask pattern, and change this part of the light. The development of the photoresist is followed by a developing process, taking a positive photoresist as an example, 'it uses a suitable solution to dissolve the exposed part of the photoresist', leaving the same photoresist pattern as the photomask pattern. As for the negative photoresist, In the case, a photoresist pattern complementary to the mask pattern is left. With the development of integrated circuit components that are increasingly denser and smaller, the effects of optical refraction and reflection that were easily overlooked in the exposure procedures of larger-sized components in the past have gradually become important factors affecting product yield, so there are many Improved technologies have been proposed to overcome these problems. Among them, a method of forming an anti-reflection coating (ARC) on the bottom or / and the top of the photoresist layer has been widely used in practical production lines.

C: \ Program Files \ Patent \ 0503-3785-E.ptd Page 4 V. Description of the invention (2) 'For example, when the gate line width of the complementary metal oxide semiconductor (CM0s) element enters 〇18 or even finer At the time of size, a silicon nitride oxide (SiON) layer is often used as the bottom anti-reflection layer (BARC) to improve the operational tolerance of the lithography imaging program that defines the polysilicon gate pattern (pr wind windc). . However, when this silicon oxynitride layer is removed by subsequent etching, it is easy to damage the gate oxide layer under the polycrystalline silicon gate; if it is removed by using hot phosphoric acid (H3P04) solution, it will cause the polycrystalline silicon gate. Damage to the polar sidewalls and active area surfaces forms rugged surface structures that affect the properties of product components. In order to further understand, the following describes the manufacturing process with reference to the first to the first (Figures. First, as shown in Figure VIII, a semiconductor substrate 10, such as a silicon wafer is provided. Formed on the substrate 10 There is a field oxide layer 12 to define the active area (acUve), and since a complementary metal-oxide half-element is to be produced, specific electrical impurities are implanted in the active area to form P-types. Well area (11) 11 and 8-type (N-Wel 1) 11B. Secondly, a gate oxide layer 13, a polycrystalline stone gate layer 14, and -nitrogen are sequentially formed on the surface of the substrate 10. The oxygen cut layer 15 is formed by, for example, a thermal oxidation process or a chemical vapor deposition process to form a gate oxide layer 13 covering the surface of the substrate 10, and then a chemical vapor deposition (CVD) process to form a polycrystalline silicon gate. The layer 14 is then deposited on the surface of the gate oxide layer 13-on the surface of the gas crystal dream closed layer. Next, a photoresist layer is coated on the surface of the gasification layer 15 and the silicon nitride layer 15 is used. Perform the lithography imaging procedure as the bottom anti-reflection layer to define the pattern of the photoresist layer 16, covering the desire Into the gate electrode region configuration.

V. Description of the invention (3) Please refer to Fig. 1B, in order to engrav the parts of the oxynitride layer 15 and the polycrystalite layer 13 which are not covered by the photoresist layer 16, so as to form the = button engraving procedure The photoresist layer 16 is removed, that is, the gate electrode shown in the figure is left. The nitrogen and oxygen 2 silicon layer 15 used as the bottom anti-reflection layer must be removed before the subsequent processes, such as forming a contact window. : The second step is to carry out a wet-type post-etching process. However, in order to ensure the complete removal of the nitrogenous silicon layer 16, the etching time is usually slightly longer than the actual need, and it often makes the polycrystals exposed to the etching solution. The surface of the active region of the silicon gate electrode 4, the gate oxide layer 1 3, and the substrate 10 is also etched and eroded. Among them, the removal of the oxynitride layer 16 will not damage the side wall of the complex crystal: gate 14, but it will erode the gate oxide layer i 3 below it, forming as shown in Figure 1C! Depression as shown. If the hot-dip acid solution is used to remove the gas 2 silicon layer 16, although the problem of erosion of the gate oxide layer 13 can be improved, according to the results of the inventor's experiments, it was found that the polycrystalline silicon gate electrode 14 g exposed to the hot phosphoric acid solution The sidewall, or even the active area surface of the substrate 10, will be etched and damaged to form a rugged surface structure. Since the technology of using silicon oxynitride as the bottom anti-reflection layer is necessary for a process with a width of less than a quarter micron, in order to be able to continue to apply this technology, it is necessary to seek for the above problems. In view of this, an object of the present invention is to provide an improved process for a semiconductor integrated circuit, which uses a silicon oxynitride layer as a bottom anti-reflection

V. Description of the invention (4) 卢 r Lur to improve the operation of the lithography imaging program that defines the complex crystal pole pattern. The purpose of improving ΓΓι is to provide a nitrogen oxide of semiconductor integrated circuit Γ1 ΐ #Filling with acid solution, except for 矣 &amp;# 石 η, which is the bottom anti-reflection layer, and prevent the polycrystalline silicon gate The side walls and the surface of the active area of the substrate are damaged by the etching during this etching process. fSinj For the above purpose, the present invention proposes a complementary metal-oxide-semiconductor (CMOS) device using silicon oxynitride as the bottom anti-reflection layer. After etching, the pattern of the polycrystalline silicon gate and oxide layers is defined. A wet chemical oxidation reaction (wet chewed 0 2 ur) sequence is added to form a thin-wall on the sidewall and the surface of the substrate, so when the subsequent use of hot phosphoric acid solution to remove silicon oxynitride, it can effectively isolate the etching Liquid, thereby preventing the polysilicon gate sidewall and the active area surface from being damaged by etching. In detail, the present invention provides a process for preventing damage to the side walls of the polysilicon gate and the surface of the active area, including the following steps: providing a half guide base j, and a field oxide layer is formed on the base to define the active area, N-type and p-type well regions are formed by implanting impurities; a gate oxide layer, a polycrystalline silicon gate layer, and a silicon nitride oxide (SiON) layer are sequentially formed on the surface of the semiconductor substrate; The photoresist layer is on the surface of the oxynitride layer and uses this-oxynitride as a bottom anti-reflection layer (BARC) to perform a lithography imaging program to define the photoresist layer pattern; the silicon oxynitride is sequentially etched Layer of the polycrystalline silicon gate layer and the gated layer are not covered by the photoresist layer pattern to form the gate structure on the active area of the semiconductor substrate; after removing the photoresist layer,

CAProgramFiles \ Patent \ 0503-3785-E.ptd page 7 V. Description of the invention (5) ---------- J Crystal stone on the side wall of the pole layer and the semiconductor substrate: two "etched gas Gasification plutonium, &quot; protection by protective layer = said that the side wall and active area surface of the silicon gate are damaged by etching. According to a preferred embodiment of the present invention, the thick sound of the gate oxide layer 2 = ° 0Λ, the thickness of the above-mentioned polycrystalline stone closed-electrode layer is about 300 Å, and the thickness of the above-mentioned lice siliconized layer is about 300 Angstroms. Oxidation growth procedure, such as: 疋 immerse the semiconductor substrate in a solution at a temperature of about 70 SPM) for about 5 to 10 minutes to form a thin oxide layer as a protective layer, the thickness of which is between 15 and 20 angstroms After that, a hot phosphoric acid (IPO4) solution is used to etch and remove the silicon oxynitride layer, and the etching time is about 10 minutes. In order to make the above and other objects, features, and advantages of the present invention more obvious and easier Only 'the following exemplifies a preferred embodiment' and the accompanying drawings are described in detail as follows: Explain the cross-sectional views of 1A to 1C 圊, which are used to show the manufacturing process of generally using a silicon nitride layer as the bottom anti-reflection layer (BARC); and the cross-sectional views of 2A to 2C 圊, which are used to show according to the present invention Manufacturing process of a preferred embodiment of the improved method. EXAMPLES A preferred embodiment of the improved method according to the present invention will be described below with reference to FIGS. 2A to 2C. First, as shown in FIG. 2A, a semiconductor substrate 20 is provided. 'For example, a &lt; 6th wafer. A field oxide layer is formed on the substrate 20

C: \ ProgramFiles \ Patent \ 0503-3785-E.ptd page 8

(field 0xide) 22 to define the active area, and since complementary metal-oxide-semiconductor (CMOS) devices are to be fabricated, specific electrical impurities are implanted in the active area to form p-type well areas. (1 &gt; ^ 11) 21 people and ^^-type region (N-Well) 21B 〇 Second, a gate oxide layer 23, a polycrystalline silicon gate layer 24, and a silicon oxynitride layer are sequentially formed on the surface of the substrate 20 The layer 25, for example, first uses a thermal oxidation process or a chemical vapor deposition process to form a gate oxide layer 23 covering the surface of the substrate 20, and the thickness is between 50 and 200 angstroms; A deposition (CVD) process forms a polycrystalline silicon gate layer 24 on the gate oxide layer 23 with a thickness of about 2,000 angstroms; then a silicon nitride layer 25 is deposited on the surface of the polycrystalline silicon gate layer 24 ' Its thickness is about 300 Angstroms. Next, the same as the conventional shoemaking, apply a photoresist layer (not shown) on the surface of the silicon nitride layer 25, and use this silicon nitride layer 25 as the bottom anti-reflection layer to perform a lithography imaging The program defines the pattern of the photoresist layer 26 to cover the area where the gate structure is to be formed. Then, portions of the silicon oxynitride layer 25, the polycrystalline silicon gate layer 24, and the gate oxide layer 23 that are not covered by the photoresist layer are sequentially etched to form a gate structure on the active area of the substrate 20. After removal, the photoresist layer is removed with a suitable solution or an oxygen plasma etching process, leaving a gate structure as shown in the figure. For the order of siliconized silicon, please refer to Section 2B. Unlike the conventional process of direct etching to remove the silicon oxynitride layer 25, the present invention first forms a thin protective layer holder covering the complex gate layer 25 and the gate oxide layer 24. Side wall i, and the surface of the substrate 20 active area "In this embodiment, a wet chemical oxidation growth process is performed, for example, the semiconductor substrate is immersed in a temperature of about 70. Its chemical training * &quot; /

V. Description of the invention (7) &quot; M (SPM) as the protective layer 2 6 Please note that the growing process is chemical or chemical. Familiar with the problems of vapor deposition caused by nitrogen oxide etching and nitrogen removal process. About 5 to 10 minutes in the solution 'its thickness is between 15 and 20' The protective layer 26 formed by the improved process of the present invention. The vapor deposition process is well known to those skilled in the art, regardless of the process is a high temperature process. The structure of the silicon layer 25 is more difficult to oxidize the broken layer at a low temperature of about 70 ° C to form a thin oxide layer to act as an angstrom. The intention is to use wet chemical oxidation instead of ordinary thermal oxidation growth processes to measure its low-temperature operating conditions, especially the thermal oxidation growth process or sequence, which also densifies the oxide layer at the same time, which will make it follow-up. The opposite 'wet chemical oxidation is performed, so it does not cause the above. Next, a wet etching process is performed, for example, using a hot phosphoric acid solution for about 10 minutes to remove the silicon oxynitride layer 25 and expose the compound below it. The gate gate layer 24 is shown in FIG. 2C. Obviously, the isolation of the protective layer 26 prevents the sidewalls of the polycrystalline silicon gate 24 and the surface of the active area of the substrate 20 from being exposed to a hot phosphoric acid solution. Therefore, even to ensure that the silicon oxynitride layer can be completely removed 25, and prolonging the etching treatment time can still effectively prevent the sidewall of the polycrystalline silicon gate layer 25 and the surface of the active area of the substrate 20 from being damaged by the etching process. Therefore, the improved process of the present invention can maintain smooth surface properties after etching to remove the silicon oxynitride layer 25 without forming a rugged surface structure as indicated by reference numeral Π in FIG. 1C. In this way, not only can the properties of product components be improved, but also the implementation of subsequent processes. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit of the present invention WMMBn C: \ ProgramFiles \ Patent \ 0503-3785-Lptd Page 5 'Description of the invention (8) and scope, there may be some changes and retouching, so the scope of protection of the present invention should be determined by the scope of the attached patent application.

C: \ Program Files \ Patent \ 0503-3785-E.ptd page 11

A process for preventing the surface of the active region from being damaged by etching, including the following steps: providing a semiconductor substrate Wang Qin region, and forming an N-type and a p-type well house by sequentially implanting impurities to form a gate oxide Layer 'a polycrystalline silicon: a silicon (SiON) layer is coated on the surface of the semiconductor substrate; a θ-layer is used to define i, and a photoresist layer is coated with an oxynitride layer on the silicon oxynitride layer as the bottom An anti-reflection layer (BARC) is used to define a photoresist layer pattern; on the surface, a lithography imaging program is performed using the nitrogen and oxygen to transform the half: sequentially etching the silicon oxynitride &amp;, the polycrystalline silicon gate layer And the gate oxygen = a portion not covered by the photoresist layer pattern to form a gate structure on the active area of the semiconductor substrate; after removing the photoresist layer, on the sidewall of the polycrystalline silicon gate layer Forming a protective layer on the surface of the conductor substrate; and removing the silicon oxynitride layer by etching, wherein the protective layer is used to prevent the sidewall of the polycrystalline gate and the surface of the active region from being damaged by etching. 2. A process for preventing etching damage to the side wall of the polycrystalline silicon gate and the surface of the active region according to item 1 of the scope of the patent application, wherein the thickness of the gate oxide layer is between 50 and 200 angstroms. 3. A process for preventing etching damage to the side wall of the polycrystalline silicon gate and the surface of the active region according to item 1 of the scope of the patent application, wherein the thickness of the polycrystalline silicon gate layer is about 2000 Angstroms. 4. A process for preventing etching damage to the side wall of the polycrystalline silicon gate and the surface of the active region as described in item 1 of the scope of patent application, wherein the silicon oxynitride layer

C: \ ProgramFiles \ Patent \ 0503-3785-E.ptd page 12 VI. Application scope Patent thickness is about 300 Angstroms. 5. A process for preventing etching damage to the side wall of the polycrystalline silicon gate and the surface of the active region as described in item 1 of the scope of the patent application, wherein the size of the gate structure is approximately 0.18 mm. 6 · A process for preventing etching damage to the side walls of the polysilicon gate and the surface of the active area as described in the first item of the patent application scope, wherein a wet chemical oxidation growth process is performed to form a thin oxide layer as the protection Floor. 7. A process for preventing etching damage to the polysilicon gate side | wall and active area surface as described in item 6 of the scope of the patent application, wherein the semiconductor substrate is immersed in a temperature of 112504/112 at a temperature of about 70 t 〇2 / 112〇 (3 ~ 10 solution in about 5 to 10 minutes to perform the wet chemical oxidation process. 8. As described in the scope of the patent application No. 6 a kind of prevention of polycrystalline silicon gate sidewall and active area surface A process that is damaged by etching, in which the thickness of the thin oxide layer formed by the wet chemical oxidation process is between 15 and 20 angstroms. 9. A method for preventing the side wall of a polycrystalline silicon gate as described in item 丨 of the patent application scope And the process of etching the surface of the active region by etching, wherein the silicon oxynitride layer is removed by etching with a hot phosphoric acid (H3P04) solution. 10. A method for preventing the side wall of the polycrystalline silicon gate and the surface of the active region as described in item 9 of the scope of patent application. In the process of being damaged by etching, the hot phosphoric acid solution is etched for about 10 minutes.

HHHI C: \ Program Files \ Patent \ 0503-3785-E.ptd page 13