CN106298504A - The method of thinning grid oxic horizon and the manufacture method of MOS device - Google Patents

Abstract

The application provides a method for thinning a gate oxide layer and a method for manufacturing a MOS device. The method includes: S101, depositing a protection layer on the gate oxide layer and the gate structure, where the protection layer includes a gate oxide protection layer, a gate sidewall protection layer and a gate top protection layer; S102, adopting dry etching Etching and removing the gate oxide protection layer and the gate top protection layer; S103, using the gate sidewall protection layer as a mask, etching and thinning the above gate oxide layer by using a wet etching process; and S104, removing The above gate sidewall protection layer. The gate oxide layer of the semiconductor device obtained by etching according to the above method has a uniform thickness, which overcomes the technical disadvantages caused by the existing etching process.

Description

Method for thinning gate oxide layer and method for manufacturing MOS device

technical field

The present application relates to a manufacturing process of a semiconductor integrated circuit, in particular to a method for thinning a gate oxide layer and a manufacturing method of a MOS device.

Background technique

At present, with the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, chips are developing towards the direction of high component density and high integration. Among them, gates of semiconductor devices are becoming thinner and shorter than before, and oxide layers of gates are becoming thinner and thinner.

In semiconductor products, both high-voltage devices and low-voltage devices are usually involved. In general, the thickness of the gate oxide layer in high-voltage devices is larger than that in low-voltage devices. Therefore, in the production process, it is necessary to etch and thin the gate oxide layer to balance the thickness of the oxide layer in the high and low voltage regions and increase the window size of the subsequent process. At present, the etching methods of the gate oxide layer mainly include photoresist masking combined with dry etching method, direct wet etching method and photoresist masking combined wet etching method.

The process steps of photoresist masking combined with dry etching method are: first deposit an oxide layer and a gate layer in sequence on the substrate, then coat a layer of photoresist on the middle part of the gate, and finally etch the gate layer by dry method As well as the oxide layer, the preparation of the gate and the thinning of the oxide layer are completed. Although this method can reduce the thickness of the oxide layer, it will cause damage to the substrate.

The process steps of the direct wet etching method are: immerse the wafer in the HF etching solution, let the HF etching solution react with the gate oxide layer for a period of time, and then gradually peel off the gate oxide layer to realize the reduction of the oxide layer. Thin. Since wet etching is isotropic, direct wet etching will cause lateral etching of the gate, so that a lateral groove appears at the bottom of the gate, thereby affecting the performance of the device.

The process steps of photoresist masking combined with wet etching method are as follows: a layer of photoresist is coated on the surface of the oxide layer and the surface of the gate as a photomask, and then the oxide layer is etched with hydrofluoric acid, and then ashed and processed. Cleaning step to remove photoresist. Although this method can achieve the balance of the thickness of the oxide layer in the high pressure and low pressure areas, it needs to add a layer of photomask and multiple corresponding procedures.

In the Chinese patent application publication number CN200310122904, a method for eliminating gate etching lateral grooves is disclosed. In this method, the over-etching step is divided into two steps of variable pressure. The first step is over-etching with high pressure. This high pressure can easily cause high molecular polymers to be generated in the plasma, and passivation can be formed on the side wall and bottom of the gate. For the protective layer, the second step is a general conventional over-etching, and its pressure is slightly lower than that of the first step, which is used to remove the unetched silicon residue and adjust the verticality of the sidewall of the gate. Although this application avoids lateral grooves, it cannot deal with the problem of oxide layer thickness balance because it is too selective for silicon/silicon oxide and it is difficult to remove silicon oxide in thick oxygen regions.

Contents of the invention

In order to solve the problems existing in the gate etching method of the existing semiconductor device, the present application provides a method for thinning the gate oxide layer and a manufacturing method of the MOS device. This method can not only achieve the balance of the thickness of the oxide layer in the high and low voltage area, but also will not cause damage to the substrate, avoiding the lateral etching caused by wet etching on the bottom of the gate, and the gate oxidation of the semiconductor device obtained The uniform layer thickness increases the window size for subsequent processes.

One aspect of the present application provides a method for thinning a gate oxide layer, the method comprising: S101, depositing a protective layer on the gate oxide layer and the gate structure, the protective layer includes a gate oxide protective layer, a gate side wall protection layer and gate top protection layer; S102, using dry etching to remove the gate oxide layer protection layer and gate top protection layer; S103, using the gate side wall protection layer as a mask, wet Etching and thinning the gate oxide layer by a method etching process; and S104, removing the gate sidewall protection layer.

Preferably, in step S103, the gate oxide layer partially covered by the gate sidewall protection layer is etched and thinned.

Preferably, in step S103, the etching ratio between the gate sidewall protection layer and the gate oxide layer is less than 1:50.

Preferably, the above wet etching process uses HF solution as the etching solution, more preferably, the volume ratio of water to HF in the above HF solution is 20-100:1.

Preferably, in step S102, the above dry etching is anisotropic etching. Preferably, the pressure of dry etching is 10-100 mTorr, the temperature is 0-60° C., and the power is 100-800 W.

Preferably, step S104 includes: immersing the semiconductor device obtained in step S103 into a protective layer dissolving agent, heating and dissolving the protective layer; more preferably, the protective layer dissolving agent is 85% phosphoric acid, and the reaction temperature is 160°C. The reaction time is 600 seconds.

Preferably, the protective layer is made of one or more materials selected from silicon nitride, titanium nitride, and silicon dioxide, and the thickness of the protective layer is 10-50 nanometers. More preferably, the ratio of the thickness of the protection layer to the etching thickness of the gate oxide layer is in the range of 1.5-1.1:1.

Another aspect of the present application is to provide a manufacturing method of a MOS device, the manufacturing method comprising: providing a semiconductor substrate, preparing a source, a drain, a gate oxide layer and a gate on the substrate; oxidizing the gate The layer is thinned, wherein the gate oxide layer is thinned by the method for thinning the gate oxide layer provided in this application; a P region or an N region is formed under the source and drain by deep ion implantation.

The manufacturing method described in the present application further includes: contact hole preparation, metallization wiring, deposition of passivation layer and subsequent lead connection and packaging process. The thickness of the semiconductor device obtained according to the manufacturing method is uniform, thereby overcoming the technical disadvantages caused by the existing etching process.

It can be seen from the above technical solution that the present application utilizes the gate sidewall protective layer formed on the gate sidewall, combined with dry etching and wet etching processes, to realize the adjustment of the thickness of the oxide layer in the high-voltage and low-voltage regions. etch thinning. This technical solution can not only balance the thickness of the oxide layer in the high-voltage and low-voltage regions according to the production requirements, but also avoid the lateral damage to the bottom of the gate during the process of etching and thinning. By using the etching method provided by this application, not only can the balance of the thickness of the oxide layer in the high and low voltage regions be achieved, but also the substrate will not be damaged, and the lateral etching caused by wet etching on the bottom of the gate can be avoided. , the thickness of the gate oxide layer of the obtained semiconductor device is uniform, and the window size of the subsequent process is increased.

In addition to the objects, features and advantages described above, the present application has other objects, features and advantages. The present application will be described in further detail below with reference to the drawings.

Description of drawings

The accompanying drawings constitute a part of this specification and are used for further understanding of the application. The accompanying drawings illustrate preferred embodiments of the application and are used together with the description to explain the principle of the application. In the picture:

FIG. 1 shows a schematic flow chart of a method for thinning a gate oxide layer provided by the present application;

Fig. 2 shows a schematic diagram of the cross-sectional structure of the base after the protective layer covers the gate oxide layer and the gate structure on the semiconductor substrate according to the method for thinning the gate oxide layer provided by the present application;

FIG. 3 shows a schematic cross-sectional structure diagram of the substrate after the gate oxide protection layer and the gate top protection layer shown in FIG. 2 are removed by dry etching;

FIG. 4 shows a schematic cross-sectional structure diagram of a substrate in which the gate oxide layer shown in FIG. 3 is etched and thinned by a wet etching process;

FIG. 5 shows a schematic cross-sectional structure diagram of the substrate after removing the gate sidewall protection layer shown in FIG. 4;

FIG. 6 shows a schematic flow chart of the method for manufacturing a MOS device provided by the present application;

FIG. 7 shows a scanning electron microscope image of a gate of a MOS device provided by a specific embodiment of the present application; and

FIG. 8 shows a scanning electron microscope image of a gate of a MOS device provided in another specific embodiment of the present application.

detailed description

The technical scheme of the present application will be described in detail below in conjunction with the specific implementation of the present application, but the following examples are only used to understand the present application, and cannot limit the present application. The embodiments in the present application and the features in the embodiments Combinable with each other, the application can be implemented in many different ways as defined and covered by the claims.

It can be known from the background technology that there is a problem of lateral etching in the existing gate oxide layer thinning etching process. The inventors of the present application have studied the above problem and creatively used the sidewall protection layer formed on the sidewall of the gate , and the combination of the dry etching process and the wet etching process, the etching thinning of the oxide layer in the high-voltage area and the oxide layer in the low-voltage area is realized, and the lateral damage at the bottom of the gate is avoided. The inventors found that the thickness of the gate oxide layer in the semiconductor device etched by the above method is uniform, which overcomes the technical drawbacks caused by the existing etching process.

As shown in Figure 1, the gate etching method provided by the present application includes the following steps: S101, depositing a protective layer on the gate oxide layer and the gate structure, the protective layer includes a gate oxide protective layer, a gate sidewall protection layer and the gate top protection layer; S102, using dry etching to remove the gate oxide protection layer and the gate top protection layer; S103, using the gate sidewall protection layer as a mask, using a wet etching process to remove the Etching and thinning the gate oxide layer; and S104, removing the gate sidewall protection layer. It can be seen from the above steps that in the present application, a gate sidewall protective layer is first formed on the sidewall of the gate, and then the gate oxide layer is wet-etched using the protective layer as a mask. Because there is a certain etching ratio between the gate sidewall protection layer and the gate oxide layer, the gate sidewall protection layer acts as a mask to protect the gate oxide layer covered by it during the wet etching process. role, thereby forming a protective effect on the sidewall of the gate. For the gate oxide layer covered by the gate sidewall protection layer, the etchant can only etch and thin a part of the gate oxide layer or cannot etch and thin the gate oxide layer at all. Therefore, after the above steps, the thinning and etching of the gate oxide layer of the semiconductor device can be realized, and the lateral etching of the bottom of the gate can also be avoided.

Now, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. These example embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of these exemplary embodiments to those of ordinary skill in the art. In the drawings, the layers are exaggerated for clarity and the thickness of the region, and the same reference numerals are used to designate the same devices, and thus their descriptions will be omitted.

Figure 1 shows a schematic flow chart of the method for thinning the gate oxide layer provided by the present application, and Figures 2-5 show the cross-sectional structure of the semiconductor device obtained after each step in the method for thinning the gate oxide layer provided by the present application schematic diagram. The method for thinning the gate oxide layer provided by the present application will be further explained below with reference to FIGS. 1-5 .

Firstly, step S101 is implemented to deposit a protection layer 204 on the gate oxide layer 202 and the gate structure 203. The protection layer 204 includes a gate oxide protection layer 2041, a gate sidewall protection layer 2042 and a gate top protection layer 2043; FIG. 2 shows a schematic diagram of a cross-sectional structure of a semiconductor device after the protective layer 204 is deposited.

It can be seen from FIG. 2 that the gate oxide protection layer 2041 covers the gate oxide layer 202 to protect the gate oxide layer; the gate sidewall protection layer 2042 covers the entire gate sidewall and covers part of the gate oxide layer. layer to protect the sidewall of the gate; the gate top protection layer 2043 covers the top of the entire gate structure 203 to protect the top of the gate. In this step, the materials used to form the gate oxide layer 202 and the gate structure 203 are commonly used materials in the field, and will not be repeated here. Preferably, the gate oxide layer is SiO ₂ , and the deposition process includes thermal oxidation, chemical vapor deposition, sputtering and the like. As for the protection layer 204 , the material forming it should have a certain etch ratio with the material forming the gate oxide layer. Preferably, the material forming the protection layer 204 is silicon nitride, titanium nitride or silicon dioxide. More preferably, the etching ratio between the gate sidewall protection layer 2042 and the gate oxide layer 202 is less than 1:50. The process of depositing the protective layer 204 may be chemical vapor deposition, heteroepitaxy, plasma enhanced chemical vapor deposition, etc. For those skilled in the art, an appropriate deposition process can be selected according to actual work requirements. Moreover, although the protection layer 204 includes a gate oxide protection layer 2041, a gate sidewall protection layer 2042, and a gate top protection layer 2043, during the formation of the protection layer 204, the gate oxide protection layer 2041, the gate The sidewall protection layer 2042 and the gate top protection layer 2043 can be integrally formed or formed in sections. In addition, in the process of implementing the present application, the thickness of the protective layer 204 can be selected according to the requirements of etching thicknesses required by different gate oxide layers. Preferably, the protective layer 204 has a thickness of 10-50 nanometers. More preferably, the ratio of the thickness of the protective layer 204 to the etched thickness of the gate oxide layer 202 (thickness of the gate oxide layer removed by etching) is in the range of 1:1 to 1.5:1.

Next, step S102 is implemented, and the gate oxide protection layer 2041 and the gate top protection layer 2043 are removed by dry etching to form a schematic cross-sectional structure diagram of the semiconductor device body as shown in FIG. 3 . The inventors of the present application adopted dry etching in this step, the purpose of which is to use the anisotropy of dry etching to etch and remove only the gate oxide protection layer 2041 and the gate top protection layer 2043, while leaving Gate sidewall protection layer 2042 . In the specific embodiment provided by the present application, the dry etching includes the following steps: placing the semiconductor device shown in Figure 2 on the carrier of the reactor, adjusting the distance between the focus ring and the substrate; turning on the heating power supply, Under the temperature and pressure, the gas is ionized to form plasma; the plasma bombards the surface of the gate oxide protection layer 2041 and the gate top protection layer 2043, and the atoms of the gate oxide protection layer 2041 and the gate top protection layer 2043 The gate oxide protection layer 2041 and the gate top protection layer 2043 are removed by striking. During the etching process, the required etching time can be adjusted according to the thicknesses of the gate oxide protection layer 2041 and the gate top protection layer 2043 . Preferably, the thickness of the gate oxide protection layer 2041 and the gate top protection layer 2043 is in the range of 10-50 nanometers, the dry etching time is 10-30s, the pressure is 10-100mTorr, and the temperature is 0 -60℃, the power is 100-800W. The gate oxide protection layer 2041 and the gate top protection layer 2043 are preferably completely removed in this step. In order to achieve complete removal, the etch process can also be controlled to 10%-15% overetch.

Then step S103 is implemented, using the gate sidewall protection layer 2042 as a mask, and using a wet etching process to etch and thin the gate oxide layer 202 to form a schematic cross-sectional structure of the semiconductor device substrate as shown in FIG. 4 . In the specific embodiment provided by the present application, the wet etching process is: completely immerse the HF etching solution on the surface of the substrate 201, and allow the HF etching solution to contact the gate oxide layer 202 on the substrate 201; The gate oxide layer 202 is gradually peeled off, and the peeled products leave the etching surface and diffuse into the etching solution. Of course, during the wet etching process, the etching time can be adjusted according to the thickness of the gate oxide layer 202 and the target thickness after thinning, and the etching solution is not limited to HF etching solution, other wet etching The commonly used etchant can also be applied to this application. If HF solution is selected as the etching solution, the concentration of the above HF solution (volume ratio of water to HF) is preferably in the range of 20-100:1. The above-mentioned hydrofluoric acid treatment time is 100-800 seconds, within this range, the etching uniformity is better, and it also effectively takes into account the stability of etching and the production capacity per unit time. Preferably, this step can control the overetching needs Within 50%, to ensure that the gate oxide layer is thinned to a predetermined thickness. Because there is a certain etch ratio between the gate sidewall protection layer 2042 and the gate oxide layer 202, during the wet etching process, the gate sidewall protection layer 2042 serves as a mask to cover the gate oxidation layer 202. Layers are protective. For the gate oxide layer covered by the gate sidewall protection layer 2042 , the etchant can only etch and thin a part of the gate oxide layer or cannot etch and thin this part of the gate oxide layer at all.

Finally, step S104 is implemented to remove the gate sidewall protection layer 2042 , and the cross-sectional structure of the formed semiconductor device body is shown in FIG. 5 . In the specific embodiment provided in this application, the process of removing the gate sidewall protective layer 2042 may be: immerse the semiconductor device obtained in step S103 into a protective layer dissolving agent, heat and dissolve the protective layer. The protective layer dissolving agent referred to here refers to a solution capable of specifically dissolving the protective layer without affecting other components in the semiconductor device. Preferably, the protective layer dissolving agent used in this application is 85% phosphoric acid, the dissolution temperature is 160° C., and the reaction time is 600 seconds. After being treated with a protective layer dissolving agent, the gate sidewall protective layer is gradually peeled off, and the peeled product leaves the etching surface and diffuses into the solution, and is discharged along with the solution. After step S104 is completed, the entire thinning process is completed. It can be seen from FIG. 5 that after the thinning process provided by the present application, the gate oxide layer 202 is thinned, but the oxide layer at the bottom of the gate 203 has no lateral grooves, which completely overcomes the existing thinning process. Technical defects in the thin process.

Another aspect of the present application is to provide a method for fabricating a MOS device. As shown in Figure 6, the manufacturing method includes: providing a semiconductor substrate, preparing source and drain electrodes, a gate oxide layer and a gate on the substrate; thinning the gate oxide layer; A P region or an N region is formed under the drain; wherein, the gate oxide layer is thinned by using the above gate oxide layer thinning process. The manufacturing method further includes: preparation of contact holes, metallization wiring, deposition of passivation layer and subsequent lead connection and packaging process. The MOS device prepared by the above manufacturing method not only realizes the uniformity of the thickness of the gate oxide layer in the high and low voltage regions during the thinning process of the gate oxide layer, but also avoids the lateral damage at the bottom of the gate, so The performance of the obtained MOS device is more stable.

The selective etching method provided by the present application will be further described below with specific examples.

Example 1

Provide a P-type silicon substrate, deposit a silicon dioxide layer (gate oxide layer) with a thickness of 10 nanometers on the P-type silicon substrate, and then form a source on the silicon wafer through photolithography, etching and electrode material deposition processes Electrode, drain, gate; Deposit a silicon nitride film (protective layer) on the surface of the gate and silicon dioxide layer by chemical vapor deposition process, the thickness of the silicon nitride film is 30 nanometers; remove by dry etching The silicon nitride film on the top of the gate and the surface of the gate oxide layer, the silicon nitride film on the side wall of the gate is retained, the etching gas is oxygen and fluorine-containing gas, the reaction power is 300 watts, and the etching temperature is 50 ° C. The etching time is 15 seconds; immerse the wafer in the HF etching solution, let the HF etching solution react with the gate oxide layer on the substrate for 500 seconds, then gradually peel off the gate oxide layer, and the stripped product leaves the etching The surface diffuses into the solution and is removed with the solution, where the concentration of HF acid (volume ratio of water to HF) is 100:1. The semiconductor device obtained in the above steps is immersed in a protective layer dissolving agent, and heated to dissolve the protective layer. The protective layer dissolving agent used is 85% phosphoric acid, the dissolving temperature is 160° C., and the reaction time is 600 seconds.

The P region or N region is formed under the source and drain electrodes by ion implantation, and finally the production of low-voltage MOS devices is completed through contact hole preparation, metallization wiring, deposition of passivation layer, subsequent lead connection, and packaging process.

Observing the gate microstructure of the low-voltage MOS device of the present embodiment through a field-effect scanning electron microscope (SEM), the operation steps are: cleaning the MOS device chip to remove surface pollutants; placing the chip in a constant temperature drying box, such as 60 ℃, remove the adsorbed water on the chip; put the chip in the gold spraying equipment, spray a layer of gold on the surface of the chip, for example, spray gold for 60 seconds, the purpose is to improve the conductivity of the chip; take out the chip after spraying gold , placed in the sample chamber, after vacuuming, turn on the power, observe and photograph the microstructure of the chip.

FIG. 7 shows a scanning electron microscope image (SEM) of the gate of the low-voltage MOS device of this embodiment. As shown in Figure 7, the substrate is evenly covered with a layer of silicon dioxide (gate oxide layer), and the substrate is not damaged by etching; the thickness of the silicon dioxide layer between the gate and the substrate is 5 nanometers , the silicon dioxide layer has a uniform thickness and no lateral grooves. The test results show that the etching and thinning of the gate oxide layer of the prepared low-voltage MOS device has been successfully completed through the gate etching method provided by the application, and the substrate and gate are not damaged, and the low-voltage MOS device has been achieved. skills requirement.

Example 2

Provide a P-type silicon substrate, deposit a silicon dioxide layer with a thickness of 20 nanometers on the silicon wafer, and then form the source and drain electrodes on the silicon wafer through photolithography, etching and electrode material deposition processes; through chemical vapor deposition The process deposits a silicon nitride film on the surface of the gate and the oxide layer as a gate protection layer, and the thickness of the titanium nitride film is 45 nanometers; the protection on the top of the gate and the surface of the gate oxide layer is removed by dry etching layer, the etching gas is oxygen and helium, the sputtering power is 300 watts, the etching temperature is 50°C, and the etching time is 12 seconds; the wafer is immersed in the HF etching solution, and the HF etching solution and the substrate The oxide layer on the bottom reacts for 500 seconds, and then the gate oxide layer is gradually peeled off. The stripped product leaves the etched surface and diffuses into the solution, and is discharged with the solution. The concentration of HF acid (volume ratio of water to HF) is 50:1 . The semiconductor device obtained in the above steps is immersed in a protective layer dissolving agent, and heated to dissolve the protective layer. The protective layer dissolving agent used is 85% phosphoric acid, the dissolving temperature is 150° C., and the reaction time is 700 seconds.

The P region or N region is formed under the source and drain electrodes by ion implantation, and finally the manufacture of high-voltage MOS devices is completed through contact hole preparation, metallization wiring, deposition of passivation layer, subsequent lead connection, and packaging process.

Observing the gate microstructure of the high-voltage MOS device of the present embodiment through a field-effect scanning electron microscope (SEM), the operation steps are: cleaning the MOS device chip to remove surface pollutants; placing the chip in a constant temperature drying box, such as 60 ℃, remove the adsorbed water on the chip; put the chip in the gold spraying equipment, spray a layer of gold on the surface of the chip, for example, spray gold for 60 seconds, the purpose is to improve the conductivity of the chip; take out the chip after spraying gold , placed in the sample chamber, after vacuuming, turn on the power, observe and photograph the microstructure of the chip.

FIG. 8 shows a scanning electron microscope image (SEM) of the high voltage MOS device of this embodiment. As shown in Figure 8, the substrate is covered with a layer of silicon dioxide, and the substrate is not damaged by etching; the thickness of the silicon dioxide layer between the gate and the substrate is 25 nanometers, and the silicon dioxide layer The thickness is uniform and no grooves are produced laterally. The test results show that the etching and thinning of the gate oxide layer of the prepared high-voltage MOS device has been successfully completed through the gate etching method provided by the application, and the substrate and gate are not damaged, and the high-voltage MOS device has been achieved. skills requirement.

As can be seen from the above embodiments, the above-mentioned examples of the present application have achieved the following technical effects:

1. During the wet etching process, the sidewall of the epitaxial layer is used to protect the gate oxide layer, so that the gate oxide layer does not undergo lateral corrosion.

2. By combining the dry etching and wet etching processes, the balance of the thickness of the oxide layer in the high and low pressure areas is achieved, and the substrate is not damaged, and the thickness of the obtained semiconductor device is uniform, thus overcoming the existing etching process The resulting technical disadvantages.

3. The gate etching method can select the thickness of the epitaxial protective layer according to the etching thickness requirements of different gate oxide layers, so that the etching method is widely applicable to low-voltage MOS devices and high-voltage MOS devices.

The above are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, there may be various modifications and changes in the present application. Within the spirit and principles of this application, any modifications, equivalent replacements, improvements, etc., should be included within the scope of protection of this application. The above is only a preferred embodiment of this application, and is not intended to limit this application. , for those skilled in the art, this application may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims (11)

1. A method for thinning gate oxide layer, characterized in that the method comprises: S101, depositing a protection layer (204) on the gate oxide layer (202) and the gate structure (203), the protection layer (204) including a gate oxide protection layer (2041), a gate sidewall protection layer ( 2042) and gate top protection layer (2043); S102, removing the gate oxide protective layer (2041) and the gate top protective layer (2043) by dry etching; S103, using the gate sidewall protection layer (2042) as a mask, etch and thin the gate oxide layer (202) by using a wet etching process; and S104, removing the gate sidewall protection layer (2042). 2. The method according to claim 1, characterized in that, in the step S103, the gate oxide layer (202) partially covered by the gate sidewall protection layer (2042) is etched and thinned . 3. The method according to claim 1 or 2, characterized in that, in the step S103, the etching between the gate sidewall protection layer (2042) and the gate oxide layer (202) The ratio is less than 1:50. 4. The method according to claim 3, wherein the wet etching process uses HF solution as the etching solution, preferably, the volume ratio of water and HF in the HF solution is 20-100:1 . 5. The method according to claim 1, characterized in that, in the step S102, the dry etching is anisotropic etching, preferably, the pressure of the dry etching is 10-100mTorr , the temperature is 0-60°C, and the power is 100-800W. 6. The method according to claim 1, wherein the step S104 comprises: immersing the semiconductor device obtained in the step S103 into a protective layer dissolving agent, heating and dissolving the protective layer; preferably, The protective layer dissolving agent is 85% phosphoric acid, the reaction temperature is 160° C., and the reaction time is 600 seconds. 7. The method according to any one of claims 1 to 6, characterized in that, the protective layer (204) is made of one or two or more selected from silicon nitride, titanium nitride, silicon dioxide material. 8. The method according to any one of claims 1 to 6, characterized in that, the protective layer (204) has a thickness of 10-50 nanometers. 9. The method according to claim 8, characterized in that the ratio of the thickness of the protection layer (204) to the etching thickness of the gate oxide layer (202) is in the range of 1.5-1.1:1. 10. A manufacturing method of a MOS device, characterized in that the manufacturing method comprises: providing a semiconductor substrate on which a source, a drain, a gate oxide layer and a gate are fabricated; Thinning the gate oxide layer by the method according to any one of claims 1 to 9; A P region or N region is formed under the source and drain electrodes by ion implantation. 11 . The manufacturing method according to claim 10 , further comprising: contact hole preparation, metallization wiring, deposition of a passivation layer, and subsequent lead connection and packaging processes.