JPH05206263A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH05206263A
JPH05206263A JP1385192A JP1385192A JPH05206263A JP H05206263 A JPH05206263 A JP H05206263A JP 1385192 A JP1385192 A JP 1385192A JP 1385192 A JP1385192 A JP 1385192A JP H05206263 A JPH05206263 A JP H05206263A
Authority
JP
Japan
Prior art keywords
silicon nitride
oxide film
nitride film
element isolation
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1385192A
Other languages
Japanese (ja)
Inventor
Yoshihiro Tokuyama
宜宏 徳山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1385192A priority Critical patent/JPH05206263A/en
Publication of JPH05206263A publication Critical patent/JPH05206263A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To provide a method for manufacturing a semiconductor device in which an element isolation for causing no bird's beak can be formed without complicated steps even at a wide or narrow element isolation region selectively. CONSTITUTION:After a silicon nitride film 3 is deposited on a patterned semiconductor substrate 1, it is etched back to obtain a structure in which its silicon nitride film 5a remains as a sidewall on a wide element active region and its silicon nitride film 5 remains uniformly on a narrow element active region. Then, locos oxidation is executed to form a LOCOS oxide film only on the wide element active region. Then, the remaining silicon nitride film is removed, the exposed substrate is etched to selectively form a groove, and the groove is filled in with the oxide film.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】 本発明は半導体装置の製造方法
に関する。更に詳しくは、素子分離形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method. More specifically, the present invention relates to a device isolation forming method.

【0002】[0002]

【従来の技術】 図2は従来の方法を経時的に説明する
図である。まず、シリコン基板10上に熱酸化膜20を
形成し、その熱酸化膜20上にシリコン窒化膜30を順
次形成する〔図3(a)〕。
2. Description of the Related Art FIG. 2 is a diagram for explaining a conventional method over time. First, the thermal oxide film 20 is formed on the silicon substrate 10, and the silicon nitride film 30 is sequentially formed on the thermal oxide film 20 [FIG. 3 (a)].

【0003】次に、素子分離領域P10のパターニングを
行う〔図3(b)〕。そして、高温で酸化することによ
り、ロコス酸化膜40を形成する〔図3(c)〕。
Next, the element isolation region P 10 is patterned [FIG. 3 (b)]. Then, the locos oxide film 40 is formed by oxidizing at a high temperature [FIG. 3 (c)].

【0004】[0004]

【発明が解決しようとする課題】 ところが、上述した
ように従来の方法では、ロコス酸化膜40の活性領域へ
の入り込み、いわゆるバーズビークが生じるため、実効
的な活性領域の減少となり、微細化の妨げとなるという
問題が生じていた。そこで、例えばOSELD等の改良
ロコス法を用いても、ロコス酸化を行う限りバーズビー
クが生じるため、依然として上記の問題はなくならな
い。
However, as described above, in the conventional method, since the so-called bird's beak occurs, which is the so-called bird's beak, which penetrates into the active region of the locos oxide film 40, the effective active region is reduced and miniaturization is hindered. There was a problem that became. Therefore, for example, even if an improved Locos method such as OSELD is used, bird's beak occurs as long as Locos oxidation is performed, and therefore the above-mentioned problem still remains.

【0005】一方、バーズビークのない構造として、シ
リコンをエッチングし、酸化膜を埋め込む方法、いわゆ
るトレンチ法も提案されているが、広大な領域を埋め込
むためには、工程が複雑化するという問題が生じてい
る。
On the other hand, as a structure without a bird's beak, a method of etching silicon to bury an oxide film, that is, a so-called trench method has been proposed, but burying a vast region causes a problem that the process becomes complicated. ing.

【0006】本発明は以上の問題点を解決すべくなされ
たもので、素子分離領域の広いところにおいても複雑な
工程を経ることなく、また、狭いところにおいてもバー
ズビークを生じることなく、微細な素子分離形成を行う
ことができ、しかも、これらの作り分けが容易な半導体
装置の製造方法を提供することを目的とする。
The present invention has been made to solve the above problems, and it does not require complicated steps even in a wide area of an element isolation region and does not cause bird's beaks in a narrow area. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be formed separately and which can be easily manufactured separately.

【0007】[0007]

【課題を解決するための手段】 上記の目的を達成する
ために、本発明の半導体装置の製造方法は、半導体基板
上に第1の酸化膜を形成した後、その第1の酸化膜上に
第1のシリコン窒化膜を形成し、その後その第1のシリ
コン窒化膜上に第2の酸化膜を形成した後、素子分離領
域となる基板直上の第1のシリコン窒化膜および第2の
酸化膜を除去することにより上記第1の酸化膜を露出さ
せ、その後、その露出した第1の酸化膜および残存する
第2の酸化膜上に所定厚みの第2のシリコン窒化膜を堆
積した後、上記第2の酸化膜が露出するまでエッチバッ
クすることにより、広い素子分離領域には、サイドウォ
ールとして上記第2のシリコン窒化膜を残存させるとと
もに狭い素子分離領域には、上記第2のシリコン窒化膜
を残存させ、その後、ロコス酸化を行った後、上記第2
のシリコン窒化膜を除去することにより露出した上記半
導体基板を所定深さエッチングすることにより溝を形成
し、その後その溝に第3の酸化膜を埋め込むことにより
特徴付けられる。
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a method of forming a first oxide film on a semiconductor substrate and then forming the first oxide film on the first oxide film. After forming a first silicon nitride film and then forming a second oxide film on the first silicon nitride film, the first silicon nitride film and the second oxide film immediately above the substrate to be the element isolation regions. To expose the first oxide film, and then deposit a second silicon nitride film of a predetermined thickness on the exposed first oxide film and the remaining second oxide film. By etching back until the second oxide film is exposed, the second silicon nitride film remains as a sidewall in the wide element isolation region, and the second silicon nitride film in the narrow element isolation region. Remain, then , Locos oxidation, then the second
The semiconductor substrate exposed by removing the silicon nitride film is etched to a predetermined depth to form a groove, and then the third oxide film is embedded in the groove.

【0008】[0008]

【作用】 第2のシリコン窒化膜を堆積した後、エッチ
バックすることにより、広い素子分離領域には、サイド
ウォールとして第2のシリコン窒化膜が、狭い素子分離
領域には、一様に第2のシリコン窒化膜が残存する構造
を得る。したがって、次に、ロコス酸化を行うことによ
り、広い素子分離領域にのみロコス酸化膜が形成され
る。その後、その残存した第2のシリコン窒化膜を除去
することにより露出した基板をエッチングすれば、選択
的に溝が形成され、その溝を酸化膜で埋め込むことによ
り、広い素子分離領域においても、また狭い素子分離領
域においても、同時に素子分離がなされる。
After the second silicon nitride film is deposited and etched back, the second silicon nitride film is formed as a sidewall in the wide element isolation region and the second silicon nitride film is uniformly formed in the narrow element isolation region. To obtain a structure in which the silicon nitride film is left. Therefore, next, by performing locos oxidation, the locos oxide film is formed only in the wide element isolation region. After that, by etching the exposed substrate by removing the remaining second silicon nitride film, a groove is selectively formed, and by filling the groove with an oxide film, even in a wide element isolation region, Even in a narrow element isolation region, element isolation is performed at the same time.

【0009】[0009]

【実施例】 図1および図2は本発明実施例を経時的に
説明する図である。1下、図面に基づいて説明する。ま
ず、シリコン基板1に熱酸化膜2を100〜300Åの
厚さに形成する。その後、その熱酸化膜2上にシリコン
窒化膜3を1000〜2000Åの厚さに形成した後、
CVD酸化膜4を2000〜4000Åの厚さに形成す
る〔図1(a)〕。
Embodiments FIGS. 1 and 2 are views for explaining an embodiment of the present invention with time. 1 below, it demonstrates based on drawing. First, the thermal oxide film 2 is formed on the silicon substrate 1 to a thickness of 100 to 300Å. After that, after forming the silicon nitride film 3 on the thermal oxide film 2 to a thickness of 1000 to 2000Å,
The CVD oxide film 4 is formed to a thickness of 2000 to 4000 Å [FIG. 1 (a)].

【0010】次に、フォトリソグラフィ技術およびエッ
チングにより、CVD酸化膜4およびシリコン窒化膜3
を除去し、パターニングを行い、パターンP1 およびパ
ターンP2 を形成する。パターンP1 およびパターンP
2 はそれぞれ素子分離領域が広いもの、狭いものであ
る。なお、本実施例ではパターンP2 の幅は0.2 〜0.6
μmとした。〔図1(b)〕。
Next, the CVD oxide film 4 and the silicon nitride film 3 are formed by photolithography and etching.
Are removed and patterning is performed to form patterns P 1 and P 2 . Pattern P 1 and pattern P
2 has a wide element isolation region and a narrow one. In this embodiment, the width of the pattern P 2 is 0.2 to 0.6.
μm. [FIG.1 (b)].

【0011】次に、CVD法により、素子分離領域が形
成された基板上にシリコン窒化膜5を2000〜400
0Åの厚さに形成する。この時の膜厚はパターンP2
幅により自由に変更できる〔図1(c)〕。
Next, a silicon nitride film 5 is formed by the CVD method on the substrate in which the element isolation region is formed, 2000 to 400.
Form to a thickness of 0Å. The film thickness at this time can be freely changed by changing the width of the pattern P 2 [FIG. 1 (c)].

【0012】次に、RIE法により、シリコン窒化膜5
をエッチバックする。この工程において、広い素子分離
領域では、0.2 〜0.4 μmの幅のサイドウォール5aが
形成され、一方、狭い素子分離領域ではサイドウォール
は形成されず、シリコン窒化膜5は埋め込まれたままの
状態を維持する〔図1(d)〕。
Next, the silicon nitride film 5 is formed by the RIE method.
To etch back. In this step, the sidewalls 5a having a width of 0.2 to 0.4 μm are formed in the wide element isolation region, while the sidewalls are not formed in the narrow element isolation region, and the silicon nitride film 5 remains buried. Maintain [Fig. 1 (d)].

【0013】次に、950〜1100℃の温度条件で湿
式酸化を行うことにより、広い素子分離領域では、30
00〜5000Åの厚さのロコス酸化膜2aが形成さ
れ、一方、狭い素子分離領域ではロコス酸化膜は形成さ
れない〔図2(a)〕。
Next, wet oxidation is carried out under the temperature condition of 950 to 1100 ° C., so that 30
The locos oxide film 2a having a thickness of 00 to 5000Å is formed, while the locos oxide film is not formed in the narrow element isolation region [FIG. 2 (a)].

【0014】次に、RIE法により、サイドウォール5
aおよび埋め込まれたシリコン窒化膜5を除去すること
により、シリコン基板1を露出させる〔図2(b)〕。
さらに、RIE法により、狭い素子分離領域ではその幅
で、広い素子分離領域ではサイドウォール5aの幅で、
露出したシリコン基板1を0.3 〜0.5 μmエッチングす
ることにより、トレンチ型の溝が形成される〔図2
(c)〕。
Next, the sidewall 5 is formed by the RIE method.
The silicon substrate 1 is exposed by removing a and the embedded silicon nitride film 5 [FIG. 2 (b)].
Further, by the RIE method, the width of the narrow element isolation region is the width, and the width of the sidewall 5a is the wide element isolation region,
A trench type groove is formed by etching the exposed silicon substrate 1 by 0.3 to 0.5 μm [FIG.
(C)].

【0015】次に、シリコン基板1上の熱酸化膜2、シ
リコン窒化膜3をフッ酸および熱リン酸処理により除去
する。その後、露出したシリコン基板1およびロコス酸
化膜2a上に、例えばNSG膜もしくはBPSG膜等の
CVD酸化膜6を4000〜6000Åの厚さに形成す
る〔図2(d)〕。
Next, the thermal oxide film 2 and the silicon nitride film 3 on the silicon substrate 1 are removed by hydrofluoric acid and hot phosphoric acid treatment. Then, a CVD oxide film 6 such as an NSG film or a BPSG film is formed on the exposed silicon substrate 1 and locos oxide film 2a to a thickness of 4000 to 6000Å [FIG. 2 (d)].

【0016】最後に、RIE法により、シリコン基板1
が露出するまでエッチバックを行うことにより、所望の
最終形状を得る〔図2(e)〕。
Finally, the silicon substrate 1 is formed by the RIE method.
The desired final shape is obtained by performing etch back until the film is exposed [FIG. 2 (e)].

【0017】[0017]

【発明の効果】 以上説明したように、本発明によれ
ば、広い素子分離領域ではロコス酸化膜の周辺に微細な
トレンチ型の溝を形成し、一方狭い素子分離領域ではト
レンチ型の溝を形成するよう構成したから、素子分離領
域の周辺および微細な素子分離領域は、バーズビークを
生じることもなくなり、微細化を促進することができ
る。また、サイドウォールを利用して広い素子分離領域
と狭い素子分離領域の作り分けをするようにしたから、
マスクを追加する等の複雑な工程を経ることなく、容易
に形成することができる。
As described above, according to the present invention, a fine trench type groove is formed around the locos oxide film in the wide element isolation region, while a trench type groove is formed in the narrow element isolation region. With this configuration, bird's beaks do not occur in the periphery of the element isolation region and the fine element isolation region, and miniaturization can be promoted. Moreover, since the wide element isolation region and the narrow element isolation region are separately formed using the side wall,
It can be easily formed without going through complicated steps such as adding a mask.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明実施例を経時的に説明する図FIG. 1 is a diagram illustrating an embodiment of the present invention over time.

【図2】 本発明実施例を経時的に説明する図FIG. 2 is a diagram illustrating an embodiment of the present invention over time.

【図3】 従来例を説明する図FIG. 3 is a diagram illustrating a conventional example.

【符号の説明】[Explanation of symbols]

1・・・・シリコン基板 2・・・・熱酸化膜 3,5・・・・シリコン窒化膜 4,6・・・・CVD酸化膜 2a・・・・ロコス酸化膜 5a・・・・サイドウォール P1 ,P2 ・・・・パターン1 ... Silicon substrate 2 ... Thermal oxide film 3, 5 ... Silicon nitride film 4, 6 ... CVD oxide film 2a ... Locos oxide film 5a ... Sidewall P 1 , P 2 ... ・ Pattern

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に第1の酸化膜を形成した
後、その第1の酸化膜上に第1のシリコン窒化膜を形成
し、その後その第1のシリコン窒化膜上に第2の酸化膜
を形成した後、素子分離領域となる基板直上の第1のシ
リコン窒化膜および第2の酸化膜を除去することにより
上記第1の酸化膜を露出させ、その後、その露出した第
1の酸化膜および残存する第2の酸化膜上に所定厚みの
第2のシリコン窒化膜を堆積した後、上記第2の酸化膜
が露出するまでエッチバックすることにより、広い素子
分離領域には、サイドウォールとして上記第2のシリコ
ン窒化膜を残存させるとともに狭い素子分離領域には、
上記第2のシリコン窒化膜を残存させ、その後、ロコス
酸化を行った後、上記第2のシリコン窒化膜を除去する
ことにより露出した上記半導体基板を所定深さエッチン
グすることにより溝を形成し、その後その溝に第3の酸
化膜を埋め込むことを特徴とする半導体装置の製造方
法。
1. A first oxide film is formed on a semiconductor substrate, a first silicon nitride film is formed on the first oxide film, and then a second silicon nitride film is formed on the first silicon nitride film. After the oxide film is formed, the first silicon nitride film and the second oxide film immediately above the substrate to be the element isolation region are removed to expose the first oxide film, and then the exposed first oxide film is removed. After depositing a second silicon nitride film having a predetermined thickness on the oxide film and the remaining second oxide film, etching back is performed until the second oxide film is exposed. The second silicon nitride film is left as a wall and the narrow element isolation region is
After leaving the second silicon nitride film, and then performing locos oxidation, the semiconductor substrate exposed by removing the second silicon nitride film is etched to a predetermined depth to form a groove, After that, a third oxide film is embedded in the groove, which is a method of manufacturing a semiconductor device.
JP1385192A 1992-01-29 1992-01-29 Manufacture of semiconductor device Pending JPH05206263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1385192A JPH05206263A (en) 1992-01-29 1992-01-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1385192A JPH05206263A (en) 1992-01-29 1992-01-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05206263A true JPH05206263A (en) 1993-08-13

Family

ID=11844784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1385192A Pending JPH05206263A (en) 1992-01-29 1992-01-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05206263A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399520A (en) * 1993-03-31 1995-03-21 Hyundai Electronics Industries Co., Ltd. Method for the formation of field oxide film in semiconductor device
US5719426A (en) * 1996-04-26 1998-02-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing process thereof
JPH1050818A (en) * 1996-06-26 1998-02-20 Lg Semicon Co Ltd Isolation film formation of semiconductor element
US5866466A (en) * 1995-12-30 1999-02-02 Samsung Electronics Co., Ltd. Methods of fabricating trench isolation regions with risers

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399520A (en) * 1993-03-31 1995-03-21 Hyundai Electronics Industries Co., Ltd. Method for the formation of field oxide film in semiconductor device
US5866466A (en) * 1995-12-30 1999-02-02 Samsung Electronics Co., Ltd. Methods of fabricating trench isolation regions with risers
US5719426A (en) * 1996-04-26 1998-02-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing process thereof
US6410973B2 (en) 1996-04-26 2002-06-25 Mitsubishi Denki Kabushiki Kaisha Thin film SOI MOSFET
JPH1050818A (en) * 1996-06-26 1998-02-20 Lg Semicon Co Ltd Isolation film formation of semiconductor element

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