JPS54146970A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS54146970A
JPS54146970A JP5577678A JP5577678A JPS54146970A JP S54146970 A JPS54146970 A JP S54146970A JP 5577678 A JP5577678 A JP 5577678A JP 5577678 A JP5577678 A JP 5577678A JP S54146970 A JPS54146970 A JP S54146970A
Authority
JP
Japan
Prior art keywords
region
layer
contact window
emitter
base contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5577678A
Other languages
Japanese (ja)
Inventor
Yasunobu Oshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5577678A priority Critical patent/JPS54146970A/en
Publication of JPS54146970A publication Critical patent/JPS54146970A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To enlarge an electrode superposition margin to improve dielectric strength by forming a base region on a semiconductor substrate and causing a poly- crystal Si layer including impurity, which becomes the diffusion source for emitter region formation, to adhere to the surface near a base contact window.
CONSTITUTION: SiO2 film 1 is formed in a part other than region 3 on the Si substrate where base region 3 is formed, and thin SiO2 film 3 is caused to adhere to all the surface. Next, poly-crystal Si layer 5 including impurity for emitter region formation is accumulated on an active region except the region on the base contact window. At this time, layer 5 is formed up to the part near the base contact window to generate margin in both sides of the emitter contact window, so that the exposure of emitter junction dependent upon positional slip-page may be eliminated to prevent the generation of dielectric strength defects. After that, layer 5 is used as a diffusion source to form emitter region 6, and Pt silicide layer 7 is caused to adhere onto the base contact window and layer 5. Then, metal 8 for electrode is provided throughout the surface, and resin film pattern 9 is used as a mask to etch metal 8, thereby obtaining leading-out electrode 8' having a desired shape.
COPYRIGHT: (C)1979,JPO&Japio
JP5577678A 1978-05-10 1978-05-10 Production of semiconductor device Pending JPS54146970A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5577678A JPS54146970A (en) 1978-05-10 1978-05-10 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5577678A JPS54146970A (en) 1978-05-10 1978-05-10 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54146970A true JPS54146970A (en) 1979-11-16

Family

ID=13008276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5577678A Pending JPS54146970A (en) 1978-05-10 1978-05-10 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54146970A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03179772A (en) * 1989-12-08 1991-08-05 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03179772A (en) * 1989-12-08 1991-08-05 Toshiba Corp Semiconductor device

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