JPS54109775A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54109775A
JPS54109775A JP1729978A JP1729978A JPS54109775A JP S54109775 A JPS54109775 A JP S54109775A JP 1729978 A JP1729978 A JP 1729978A JP 1729978 A JP1729978 A JP 1729978A JP S54109775 A JPS54109775 A JP S54109775A
Authority
JP
Japan
Prior art keywords
pattern
film
resist pattern
heat treatment
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1729978A
Other languages
Japanese (ja)
Other versions
JPS6217373B2 (en
Inventor
Hiroshi Kuroda
Hideaki Shimoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1729978A priority Critical patent/JPS54109775A/en
Publication of JPS54109775A publication Critical patent/JPS54109775A/en
Publication of JPS6217373B2 publication Critical patent/JPS6217373B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To eliminate the pinholes occurring at the pattern edge by forming the photo resist pattern on the semiconductor substrate and then softening the pattern, and thus to avoid the short circuit between the electrodes for the high-density IC as well as to obtain the micropattern in a high yield.
CONSTITUTION: The areas excluding the electrode wiring forming region on the surface of Si substrate 31 is covered with 1st photo resist pattern 33, thus ensuring a short-time heat treatment at the temperature higher than the softening point of the resist. As a result, the edge of pattern 33 is tilted by heat and then Al film 35 is deposited on the entire surface. Thus, Al film 35a1 and 35a2 are formed between patterns 33 to be used as the wiring later, and Al film 35c and 35b are formed at the tilted side surface and the upper surface respectively. In this case, the solvent in pattern 33 is almost evaporated by the previous heat treatment, so no pinhole is caused to Al film 35. After this, 2nd resist pattern 36 which is reverse to pattern 33 is formed to be used as the mask to etch off the exposed part of film 35, thus only film 35a1 and 35a2 remaining.
COPYRIGHT: (C)1979,JPO&Japio
JP1729978A 1978-02-16 1978-02-16 Manufacture of semiconductor device Granted JPS54109775A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1729978A JPS54109775A (en) 1978-02-16 1978-02-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1729978A JPS54109775A (en) 1978-02-16 1978-02-16 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS54109775A true JPS54109775A (en) 1979-08-28
JPS6217373B2 JPS6217373B2 (en) 1987-04-17

Family

ID=11940116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1729978A Granted JPS54109775A (en) 1978-02-16 1978-02-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54109775A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140735A (en) * 1983-12-28 1985-07-25 Fujitsu Ltd Manufacture of semiconductor device
US6177337B1 (en) 1998-01-06 2001-01-23 International Business Machines Corporation Method of reducing metal voids in semiconductor device interconnection

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140735A (en) * 1983-12-28 1985-07-25 Fujitsu Ltd Manufacture of semiconductor device
US6177337B1 (en) 1998-01-06 2001-01-23 International Business Machines Corporation Method of reducing metal voids in semiconductor device interconnection

Also Published As

Publication number Publication date
JPS6217373B2 (en) 1987-04-17

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