JPS5766651A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5766651A
JPS5766651A JP14162780A JP14162780A JPS5766651A JP S5766651 A JPS5766651 A JP S5766651A JP 14162780 A JP14162780 A JP 14162780A JP 14162780 A JP14162780 A JP 14162780A JP S5766651 A JPS5766651 A JP S5766651A
Authority
JP
Japan
Prior art keywords
layer
wiring
heating
etched
slope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14162780A
Other languages
Japanese (ja)
Inventor
Kazuaki Yamanochi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14162780A priority Critical patent/JPS5766651A/en
Publication of JPS5766651A publication Critical patent/JPS5766651A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form a gentle slope to the internal peripheral surface of a piercing hole to prevent disconnection of a wiring layer by treating with heating and melting an insulating layer formed on a substrate. CONSTITUTION:An insulating film 12, a wiring layer 13 and a PSG layer 14 are formed on a silicon substrate 11, and the layer 14 is etched taking a photoresist layer 15 as a mask. Then, after the layer 15 is removed, the layer 14 is melted with heating. At this time, a slope of an edge part of the opening of the piercing hole 16 becomes gentle. Next, the layer 14 is etched to allow the layer 13 to be exposed. Then, a wiring pattern 17 is formed.
JP14162780A 1980-10-09 1980-10-09 Manufacture of semiconductor device Pending JPS5766651A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14162780A JPS5766651A (en) 1980-10-09 1980-10-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14162780A JPS5766651A (en) 1980-10-09 1980-10-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5766651A true JPS5766651A (en) 1982-04-22

Family

ID=15296431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14162780A Pending JPS5766651A (en) 1980-10-09 1980-10-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5766651A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4948743A (en) * 1988-06-29 1990-08-14 Matsushita Electronics Corporation Method of manufacturing a semiconductor device
US5399532A (en) * 1991-05-30 1995-03-21 At&T Corp. Integrated circuit window etch and planarization
US5552342A (en) * 1993-08-20 1996-09-03 Nippondenso Co., Ltd. Method for producing a contact hole in a semiconductor device using reflow and etch

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4948743A (en) * 1988-06-29 1990-08-14 Matsushita Electronics Corporation Method of manufacturing a semiconductor device
US5399532A (en) * 1991-05-30 1995-03-21 At&T Corp. Integrated circuit window etch and planarization
US5552342A (en) * 1993-08-20 1996-09-03 Nippondenso Co., Ltd. Method for producing a contact hole in a semiconductor device using reflow and etch

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