JPS5483771A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5483771A
JPS5483771A JP15197077A JP15197077A JPS5483771A JP S5483771 A JPS5483771 A JP S5483771A JP 15197077 A JP15197077 A JP 15197077A JP 15197077 A JP15197077 A JP 15197077A JP S5483771 A JPS5483771 A JP S5483771A
Authority
JP
Japan
Prior art keywords
layer
break
substrate
upper edge
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15197077A
Other languages
Japanese (ja)
Inventor
Hiroshi Koshimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15197077A priority Critical patent/JPS5483771A/en
Publication of JPS5483771A publication Critical patent/JPS5483771A/en
Pending legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE: To prevent a break by forming a taper after the formation of a highly- precise thin film pattern.
CONSTITUTION: On field oxidized film 2 on substrate 1, poly Si wiring 3 is formed. Substrate 1 of the corresponding condtitution is covered with synthetic rubber photo resist 4 and an O2-plasma treatment is done to expose the upper edge of layer 3. Next, it is processed at 150° for 30 minutes in N2 and then, the upper edge of layer 3 is etched by a solution of fluoric acid, nitric acid, and water acetic acid. Resist 4 is removed, phosphorus is diffused to layer 3, and the corner is rounded; and then, Al is vapor-deposited and the wiring layer is formed, so that no break will be made.
COPYRIGHT: (C)1979,JPO&Japio
JP15197077A 1977-12-16 1977-12-16 Manufacture of semiconductor device Pending JPS5483771A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15197077A JPS5483771A (en) 1977-12-16 1977-12-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15197077A JPS5483771A (en) 1977-12-16 1977-12-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5483771A true JPS5483771A (en) 1979-07-04

Family

ID=15530191

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15197077A Pending JPS5483771A (en) 1977-12-16 1977-12-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5483771A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59123234A (en) * 1982-12-28 1984-07-17 Tohoku Metal Ind Ltd Microscopic processing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59123234A (en) * 1982-12-28 1984-07-17 Tohoku Metal Ind Ltd Microscopic processing method
JPH0479130B2 (en) * 1982-12-28 1992-12-15 Tokin Corp

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