JPH0479130B2 - - Google Patents

Info

Publication number
JPH0479130B2
JPH0479130B2 JP57230364A JP23036482A JPH0479130B2 JP H0479130 B2 JPH0479130 B2 JP H0479130B2 JP 57230364 A JP57230364 A JP 57230364A JP 23036482 A JP23036482 A JP 23036482A JP H0479130 B2 JPH0479130 B2 JP H0479130B2
Authority
JP
Japan
Prior art keywords
oxide film
corner
workpiece
film
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57230364A
Other languages
Japanese (ja)
Other versions
JPS59123234A (en
Inventor
Eiji Yamanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokin Corp
Original Assignee
Tokin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokin Corp filed Critical Tokin Corp
Priority to JP23036482A priority Critical patent/JPS59123234A/en
Publication of JPS59123234A publication Critical patent/JPS59123234A/en
Publication of JPH0479130B2 publication Critical patent/JPH0479130B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Description

【発明の詳細な説明】 本発明は例えば半導体装置の製造に適用して効
果がある微細加工方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microfabrication method that is effective when applied to, for example, the manufacture of semiconductor devices.

近年、特に半導体工業に於ては、あらゆる対象
が小型化を目指しており、数多くの微細加工方法
が提案され実施されて来ている。特に最近では電
子ビーム露光装置やX線露光装置等の優れた微細
加工装置が実用化されつつある。しかしながら、
これら優れた性能を持つた設備は極めて高価でか
つ取扱いが複雑なために、気軽に導入することは
出来ないのが実状である。
In recent years, especially in the semiconductor industry, all objects are aimed at miniaturization, and many microfabrication methods have been proposed and implemented. In particular, excellent microfabrication apparatuses such as electron beam exposure apparatuses and X-ray exposure apparatuses have recently been put into practical use. however,
The reality is that these facilities with excellent performance are extremely expensive and complicated to handle, so they cannot be easily introduced.

本発明の一般的な目的は、前述の如き高価な設
備を用いないで、極めて容易かつ安価に微細加工
を行なうことができる微細加工方法を提供するこ
とにある。
A general object of the present invention is to provide a microfabrication method that allows microfabrication to be carried out extremely easily and inexpensively without using the expensive equipment described above.

本発明の具体的な目的は、表面に凹凸や段部を
有する被加工物に対し、該凸部や段部のコーナー
部のみを選択的に除去することを、極めて容易か
つ安価に達成することができる微細加工方法を提
供することにある。
A specific object of the present invention is to extremely easily and inexpensively achieve the selective removal of only the corners of the protrusions and steps of a workpiece having unevenness and steps on its surface. The objective is to provide a microfabrication method that allows for

本発明によれば、表面に凹凸又は段部を有する
被加工物の該表面に、O2ガス雰囲気又はO2ガス
と水蒸気との混合ガス雰囲気中での加熱処理によ
り、前記凸部又は前記段部のコーナー部のみに他
の部分よりも膜厚の薄い部分が生じるように酸化
膜を形成する工程と、前記コーナー部の前記酸化
膜のみが除去されるように、前記酸化膜表面全域
にエツチングを施すことによつて、前記コーナー
部の前記酸化膜のみを開孔する工程と、該開孔さ
れた前記酸化膜をマスクとして前記被加工物の前
記表面にエツチングを施すことによつて、前記凸
部又は前記段部の前記コーナー部のみをエツチン
グ除去する工程とを含む微細加工方法が得られ
る。
According to the present invention, the surface of a workpiece having irregularities or steps on the surface is heated by heat treatment in an O 2 gas atmosphere or a mixed gas atmosphere of O 2 gas and water vapor. a process of forming an oxide film so that a thinner part is formed only at the corner part of the part, and etching the entire surface of the oxide film so that only the oxide film at the corner part is removed; a step of opening only the oxide film at the corner portion, and etching the surface of the workpiece using the opened oxide film as a mask. A microfabrication method is obtained which includes a step of etching and removing only the corner portion of the convex portion or the stepped portion.

以下、本発明の実施例について図面を参照して
説明する。
Embodiments of the present invention will be described below with reference to the drawings.

本発明では、第1に、第1図に示される如き表
面に角形状の凹凸を有する半導体基板1をO2
ス雰囲気中又は水蒸気を含むO2ガス雰囲気中で
加熱酸化し、第2図のように、全面に酸化膜2を
形成する。その際、酸化膜2の厚みは1000オング
ストローム以下100オングストローム以上である
ことが望ましい。この酸化工程により凸部のコー
ナー部Aの部分の酸化膜は他の平面領域すなわち
凸部の頂面及び側面、更に凹部の底面の厚みに比
べ、1/2〜1/3の厚みに形成される。その理由を第
3図で説明する。
In the present invention, first, a semiconductor substrate 1 having square irregularities on the surface as shown in FIG. 1 is heated and oxidized in an O 2 gas atmosphere or an O 2 gas atmosphere containing water vapor, and then An oxide film 2 is formed on the entire surface as shown in FIG. In this case, the thickness of the oxide film 2 is desirably less than 1000 angstroms and more than 100 angstroms. Through this oxidation process, the oxide film on the corner A of the convex portion is formed to have a thickness that is 1/2 to 1/3 of the thickness of other flat areas, that is, the top and side surfaces of the convex portion, and the bottom surface of the concave portion. Ru. The reason for this will be explained with reference to FIG.

第3図のように、表面に角形状の段部を有する
例えばシリコン等の半導体基板1の該表面に熱酸
化により膜厚1000オングストローム以下の酸化膜
2を形成した場合、基板1の頂面部と側面部の大
部分の領域は膜厚tであり、段部のコーナー部A
の部分では膜厚がt/2〜t/3となる。という
のは、シリコンの例では、段部の頂面又は側面の
うち、コーナー部Aから距離t以上離れた領域に
於ては、酸化膜2の成長に供給されるO2分子と
Si原子とが化学量論的であり、x方向又はy方向
の一方向だけの原子のやりとりでSiO2膜厚が決
まる。これに対し、コーナー部Aの領域に於て
は、O2分子の量は充分であるが、Si原子はx、
yの二方向へ移動し反応してSiO2膜を形成しな
ければならず、コーナー部AはSi不足の領域とな
つている。従つて、コーナー部Aに形成される
SiO2膜2の厚みも当然薄くなるのである。
As shown in FIG. 3, when an oxide film 2 with a thickness of 1000 angstroms or less is formed by thermal oxidation on the surface of a semiconductor substrate 1 made of silicon or the like having an angular step on the surface, the top surface of the substrate 1 and Most areas of the side surface have a film thickness of t, and the corner part A of the step part has a film thickness of t.
The film thickness is t/2 to t/3 at the portion. This is because, in the case of silicon, in a region of the top surface or side surface of the stepped portion that is more than a distance t from the corner portion A, the O 2 molecules supplied to the growth of the oxide film 2 and
Si atoms are stoichiometric, and the SiO 2 film thickness is determined by the exchange of atoms in only one direction, the x or y direction. On the other hand, in the corner A region, the amount of O 2 molecules is sufficient, but the Si atoms are
It must move in two directions of y and react to form a SiO 2 film, and the corner A is a Si-deficient region. Therefore, it is formed in the corner part A.
Naturally, the thickness of the SiO 2 film 2 also becomes thinner.

以上の様にして段部あるいは凸部のコーナーA
に、他の部分よりも薄い酸化膜2が形成された半
導体基板1を、酸化膜専用エツチヤント(すなわ
ち酸化膜がSiO2の場合はフツ化アンモニウム系
エツチヤント)に浸漬すると、第4図に見られる
様にコーナーAのみの酸化膜(SiO2膜)2が除
去開孔され、酸化膜2に開孔部Bが形成されるの
である。もちろん、エツチング時間は、平坦部の
SiO2膜2の膜厚t(第3図)が完全除去される時
間の1/2〜1/3の時間ということになる。
As described above, the corner A of the step or convex part is
When the semiconductor substrate 1 on which the oxide film 2 is formed, which is thinner than the other parts, is immersed in an etchant specifically for the oxide film (i.e., an ammonium fluoride-based etchant when the oxide film is SiO 2 ), the result is shown in FIG. In this way, the oxide film (SiO 2 film) 2 only at the corner A is removed and opened, and the opening B is formed in the oxide film 2. Of course, the etching time is
This means that the time required is 1/2 to 1/3 of the time required to completely remove the film thickness t (FIG. 3) of the SiO 2 film 2.

次に、半導体基板1の専用エツチヤント(例え
ば半導体基板1がシリコンの場合には、弗酸、硝
酸系のエツチヤント)中で、半導体基板1を浸漬
撹拌することにより、第5図のCに示される様
に、段部又は凸部のコーナー部のみを簡単にエツ
チング除去できるのである。
Next, the semiconductor substrate 1 is dipped and stirred in a special etchant for the semiconductor substrate 1 (for example, a hydrofluoric acid or nitric acid-based etchant when the semiconductor substrate 1 is made of silicon), thereby producing the etchant shown in FIG. 5C. In this way, only the corner portions of the stepped portions or convex portions can be easily etched away.

本発明の応用としては、例えば、切込み構造を
有する、静電誘導型トランジスタやその他のトラ
ンジスタの電極分離等に利用出来るし、又、単一
段部(第1図の状態)を微細な多段(第5図の状
態)に加工することに利用できる。また、本発明
は、被加工物が半導体材料の場合のみならず、被
加工物が、O2ガス雰囲気あるいはO2ガスと水蒸
気との混合ガス雰囲気中で加熱して酸化膜を形成
可能な材料(例えば、金属)であれば、適用可能
であることは言うまでもない。
As an application of the present invention, it can be used, for example, to separate the electrodes of static induction transistors and other transistors having a notch structure, and it can also be used to convert a single stage part (the state shown in Figure 1) into fine multi-stage parts (the state shown in Fig. 1). It can be used for processing (the state shown in Figure 5). Furthermore, the present invention is applicable not only when the workpiece is a semiconductor material, but also when the workpiece is a material that can form an oxide film by heating in an O 2 gas atmosphere or a mixed gas atmosphere of O 2 gas and water vapor. (for example, metal), it goes without saying that it is applicable.

以上説明したように、本発明には、表面に凹凸
や段部を有する被加工物に対し、該凸部や段部の
コーナー部のみを選択的に除去することを、極め
て容易かつ安価に達成することができるという効
果がある。
As explained above, the present invention can extremely easily and inexpensively achieve selective removal of only the corners of the protrusions and steps in a workpiece having unevenness and steps on the surface. The effect is that it can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第5図は本発明の微細加工方法を説明
するための図で、第1図は凹凸を表面に持つた半
導体基板の断面図、第2図は半導体基板1に全面
熱酸化により酸化膜を形成した状態の断面図、第
3図は第2図の凸部のコーナー部A及びその近傍
の拡大図、第4図はコーナー部Aを選択的に窓開
けした様子を示す断面図、第5図はコーナー部の
酸化膜窓から選択的に半導体基板のコーナー部A
のみをエツチング除去した様子を示す断面図であ
る。 1……半導体基板(例えばSi)、2……酸化膜
(例えばSiO2)、A……コーナー部分、B……コ
ーナー開孔部、C……エツチングされた部分。
FIGS. 1 to 5 are diagrams for explaining the microfabrication method of the present invention. FIG. 1 is a cross-sectional view of a semiconductor substrate with an uneven surface, and FIG. 3 is an enlarged view of the corner portion A of the convex portion in FIG. 2 and its vicinity; FIG. 4 is a sectional view showing the corner portion A selectively opened. , FIG. 5 shows the corner A of the semiconductor substrate selectively starting from the oxide film window at the corner.
FIG. 3 is a cross-sectional view showing a state in which only the etched portion has been removed by etching. 1... Semiconductor substrate (for example, Si), 2... Oxide film (for example, SiO 2 ), A... Corner portion, B... Corner opening, C... Etched portion.

Claims (1)

【特許請求の範囲】[Claims] 1 表面に凹凸又は段部を有する被加工物の該表
面に、O2を含有するガス雰囲気中での加熱処理
により、前記凸部又は前記段部のコーナー部の表
面と他の表面とにおける、O2分子と前記被加工
物の原子との反応確率の相違を利用して、前記コ
ーナー部の表面のみに前記他の表面よりも膜厚の
薄い部分を有する酸化膜を形成する工程と、前記
コーナー部の前記酸化膜のみが除去されるよう
に、前記酸化膜表面全域にエツチングを施すこと
によつて、前記コーナー部の前記酸化膜のみを開
孔する工程と、該開孔された前記酸化膜をマスク
として前記被加工物の前記表面にエツチングを施
すことによつて、前記凸部又は前記段部の前記コ
ーナー部のみをエツチング除去する工程とを含む
微細加工方法。
1. The surface of a workpiece having an uneven surface or a step is subjected to heat treatment in a gas atmosphere containing O2 , so that the surface of the corner of the protrusion or the step and other surfaces are heated. forming an oxide film having a thinner part than the other surface only on the surface of the corner part by utilizing the difference in reaction probability between O 2 molecules and atoms of the workpiece; a step of opening only the oxide film at the corner portions by etching the entire surface of the oxide film so that only the oxide film at the corner portions is removed; A microfabrication method comprising the step of etching the surface of the workpiece using a film as a mask, thereby etching away only the corner portion of the convex portion or the step portion.
JP23036482A 1982-12-28 1982-12-28 Microscopic processing method Granted JPS59123234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23036482A JPS59123234A (en) 1982-12-28 1982-12-28 Microscopic processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23036482A JPS59123234A (en) 1982-12-28 1982-12-28 Microscopic processing method

Publications (2)

Publication Number Publication Date
JPS59123234A JPS59123234A (en) 1984-07-17
JPH0479130B2 true JPH0479130B2 (en) 1992-12-15

Family

ID=16906696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23036482A Granted JPS59123234A (en) 1982-12-28 1982-12-28 Microscopic processing method

Country Status (1)

Country Link
JP (1) JPS59123234A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6154028A (en) * 1984-08-24 1986-03-18 Waseda Daigaku Magnetic recording medium and its production

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52131471A (en) * 1976-04-28 1977-11-04 Hitachi Ltd Surface treatment of substrate
JPS5483771A (en) * 1977-12-16 1979-07-04 Nec Corp Manufacture of semiconductor device
JPS5759331A (en) * 1980-09-26 1982-04-09 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52131471A (en) * 1976-04-28 1977-11-04 Hitachi Ltd Surface treatment of substrate
JPS5483771A (en) * 1977-12-16 1979-07-04 Nec Corp Manufacture of semiconductor device
JPS5759331A (en) * 1980-09-26 1982-04-09 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS59123234A (en) 1984-07-17

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