JPS5585042A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5585042A
JPS5585042A JP16555878A JP16555878A JPS5585042A JP S5585042 A JPS5585042 A JP S5585042A JP 16555878 A JP16555878 A JP 16555878A JP 16555878 A JP16555878 A JP 16555878A JP S5585042 A JPS5585042 A JP S5585042A
Authority
JP
Japan
Prior art keywords
contact hole
conductive film
substrate
film
formed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16555878A
Inventor
Hideaki Arima
Yoji Masuko
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16555878A priority Critical patent/JPS5585042A/en
Publication of JPS5585042A publication Critical patent/JPS5585042A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the pollution of a substrate, by a method wherein a surface of the substrate exposed by a contact hole is coated with a conductive film, and a wiring layer is formed.
CONSTITUTION: A contact hole is opened to an insulating film 2 on a substrate 1, a conductive thin-film of polysilicon, Ti, W, Au, etc. is formed on the whole surface, and a conductive film 5 is built up by selectively etching the said thin-film by means of photo-etching while leaving the conductive film with sufficient area containing an opening surface of the contact hole. A wiring layer 3 is formed by selectively etching the conductive film newly formed. Since the contact hole is covered with the conductive film 5 even when the contact hole cannot perfectly be coated with the wiring layer 3 by the positional slippage of a photo-resist pattern, the substrate is not exposed, and pollution can be prevented.
COPYRIGHT: (C)1980,JPO&Japio
JP16555878A 1978-12-21 1978-12-21 Semiconductor device Pending JPS5585042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16555878A JPS5585042A (en) 1978-12-21 1978-12-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16555878A JPS5585042A (en) 1978-12-21 1978-12-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5585042A true JPS5585042A (en) 1980-06-26

Family

ID=15814635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16555878A Pending JPS5585042A (en) 1978-12-21 1978-12-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5585042A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4517225A (en) * 1983-05-02 1985-05-14 Signetics Corporation Method for manufacturing an electrical interconnection by selective tungsten deposition
US4612257A (en) * 1983-05-02 1986-09-16 Signetics Corporation Electrical interconnection for semiconductor integrated circuits
US4801559A (en) * 1981-07-21 1989-01-31 Fujitsu Limited Process for forming planar wiring using polysilicon to fill gaps
US4981816A (en) * 1988-10-27 1991-01-01 General Electric Company MO/TI Contact to silicon

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4801559A (en) * 1981-07-21 1989-01-31 Fujitsu Limited Process for forming planar wiring using polysilicon to fill gaps
US4517225A (en) * 1983-05-02 1985-05-14 Signetics Corporation Method for manufacturing an electrical interconnection by selective tungsten deposition
US4612257A (en) * 1983-05-02 1986-09-16 Signetics Corporation Electrical interconnection for semiconductor integrated circuits
US4981816A (en) * 1988-10-27 1991-01-01 General Electric Company MO/TI Contact to silicon

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