JPS59107525A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59107525A
JPS59107525A JP57217960A JP21796082A JPS59107525A JP S59107525 A JPS59107525 A JP S59107525A JP 57217960 A JP57217960 A JP 57217960A JP 21796082 A JP21796082 A JP 21796082A JP S59107525 A JPS59107525 A JP S59107525A
Authority
JP
Japan
Prior art keywords
nitride film
substrate
warpage
silicon nitride
crystal defects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57217960A
Other languages
Japanese (ja)
Inventor
Koichi Hashimoto
浩一 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57217960A priority Critical patent/JPS59107525A/en
Publication of JPS59107525A publication Critical patent/JPS59107525A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent the inducing of warpage and crystal defects on a substrate wafer by a method wherein an Si nitride film is adhered to both front and back sides of an Si substrate. CONSTITUTION:An Si nitride film 5 for selective oxidation, an Si nitride film 5' for prevention of warpage, an Si nitride film 6 for interlayer insulation of a double-layer wiring, and an Si nitride film 6' for prevention of warpage are adhered to the front and back sides of an Si substrate 4 respectively. In this case, due to the presence of Si nitride films 5' and 6' on the back side of the substrate, no warpage on the substrate wafer and the crystal defects resulting from said warpage can be prevented, thereby enabling to manufacture IC wafers and to obtain the ICs of high efficiency with a high yield rate.

Description

【発明の詳細な説明】 不発明は半導体装置に係り、特に製造歩留シの良い半導
体装置の構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a structure of a semiconductor device with a high manufacturing yield.

近年ＩＣの高集積化に伴い、多層配線化が進んでおり、
多層配線用層間絶縁膜にシリコン窒化膜が多く用いられ
ている。又高性能化の要請による寄性容景低減のため誘
電体分離技術が用いられておシ、この場合もシリコン基
板ノ・一基板表面に付着された、シリコン窒化膜をマス
クとし高温選択酸化で形成することが一般的である。In recent years, as ICs have become more highly integrated, multilayer wiring has progressed.
Silicon nitride films are often used as interlayer insulating films for multilayer wiring. In addition, dielectric separation technology is used to reduce parasitic appearance due to the demand for higher performance, and in this case too, high-temperature selective oxidation is performed using a silicon nitride film attached to the surface of a silicon substrate as a mask. It is common to form

前渚の場合約３００°Ｃ１後者の場合１０００’Ｃの高
温作業が必要で表面へだけのシリコン窒化膜付着では、
第１図のように基板１のシリコンと付着シリコン窒化膜
２，３との熱膨張係数の差により熱歪が発生し基板シリ
コン基板ノ・−がそり、又Ｓｉへの結晶欠陥誘発の原因
となる。ウエノ・−のそシは３０゛０〜５００　ｌ＋に
達する場合がある。ウェハーのそりは目金露光時の回合
ずれ、或いは回合不能の状態とガリＩＣの収率を顕著に
低下させる。同様に結晶欠陥もトランジスタのリーク電
流増大につながりＩＣの収率を顕著に低下させる。The former requires high-temperature work of approximately 300°C and the latter 1000'C, and silicon nitride film deposition only on the surface requires high-temperature work.
As shown in Figure 1, thermal strain occurs due to the difference in thermal expansion coefficient between the silicon of the substrate 1 and the deposited silicon nitride films 2 and 3, which causes the silicon substrate to warp and induce crystal defects in the Si. Become. Ueno-socket can reach 30゛0-500 l+. Warping of the wafer causes misalignment or inability to align during eyelet exposure, and significantly reduces the yield of Gali IC. Similarly, crystal defects also lead to an increase in transistor leakage current and significantly reduce the IC yield.

従って本発明の目的は収率をそこなうことなく高性能Ｉ
Ｃ４−提供することにある。Therefore, the object of the present invention is to provide high performance I without compromising yield.
C4 - To provide.

不発明によれはまず基板の選択酸化時に、マスクとして
用いる８００〜１ｓｏｏＸのシリコン窒化膜を基板の表
・裏に刺着し、表面のシリコン窒化膜を写真技術により
選択的に除去した林、１０００°Ｃの酸化雰囲気中で加
熱する。According to the non-inventive method, first, during selective oxidation of a substrate, a silicon nitride film of 800 to 1 sooX was attached to the front and back of the substrate to be used as a mask, and the silicon nitride film on the surface was selectively removed using a photographic technique. Heat in an oxidizing atmosphere at °C.

この場合不発明の特徴である裏面のシリコン窒化膜の存
在のため、ウエノ・−のそシ及びそれに起因する結晶欠
陥の誘発は生じない。In this case, due to the presence of the silicon nitride film on the back surface, which is a feature of the present invention, wafer cracking and crystal defects caused by it do not occur.

次に実施例を説明する。シリコン窒化膜を用いるプロセ
スは多層配線用層間絶縁膜としてであシ、・第２図のよ
うに基板４の表面、裏面に各々数１０００Ｘ〜１５００
０λ程度のシリコン窒化膜５　、５’。Next, an example will be described. The process using silicon nitride film is suitable for use as an interlayer insulating film for multilayer wiring, and as shown in FIG.
Silicon nitride films 5 and 5' having a thickness of about 0λ.

６．６’ｆｆｉ伺着する。この場合基板ウェハーは約３
００°Ｃ程度になるが裏面のシリコン窒化膜の存在のた
め、基板ウェハーのそり及結晶欠陥の誘発も生じない。6. Arrive at 6'ffi. In this case the substrate wafer is approximately 3
Although the temperature is about 00°C, due to the presence of the silicon nitride film on the back surface, warping of the substrate wafer and crystal defects are not induced.

以上の各・ぐ基板ウェハーの裏面に刺着されたシリコン
窒化膜の存在で基板ウェハーのそりもなく、結晶欠陥も
誘発せずＩＣのウェハー製造がＥＪ能となシ高収率、高
性能なＩＣ提供が可能となる。Due to the presence of the silicon nitride film stuck on the back side of the substrate wafer, the substrate wafer does not warp, crystal defects are not induced, and IC wafer manufacturing can be performed with EJ performance, resulting in high yield and high performance. It becomes possible to provide IC.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来構造の断面図、第２図は不発明による半導
体ウェハーの断面図、である。 なお図において、１・・従来のそシのあるシリコン基板
、２・・・・・・選択酸化用シリコン窒化膜、３・・２
層配線の眉間絶縁用シリコン窒化膜、４　・・そりの生
じないシリコン基板、５・・　選択酸化用シリコン窒化
Ｍ（Ｍ板表面）、５′・・・そシ防止用シリコン審化膜
（基板裏面）、６ｍ・・２層配線の層間絶縁用シリコン
窒化膜、６′・−そシ防止用シリコン窒化膜（基板裏面
）、である。FIG. 1 is a sectional view of a conventional structure, and FIG. 2 is a sectional view of a semiconductor wafer according to the invention. In the figure, 1... conventional silicon substrate with ribs, 2... silicon nitride film for selective oxidation, 3... 2
Silicon nitride film for insulation between the eyebrows of layer wiring, 4... Silicon substrate that does not cause warpage, 5... Silicon nitride M for selective oxidation (M board surface), 5'... Silicon reinforcing film for warpage prevention (substrate (back side), 6m... silicon nitride film for interlayer insulation of two-layer wiring, 6' - silicon nitride film for warpage prevention (back side of substrate).

Claims (1)

【特許請求の範囲】[Claims] シリコン基板の表面と裏面とにシリコン窒化膜が付着さ
れたことを慣、徴とする半導体装置。A semiconductor device characterized by the fact that a silicon nitride film is attached to the front and back surfaces of a silicon substrate.
JP57217960A 1982-12-13 1982-12-13 Semiconductor device Pending JPS59107525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57217960A JPS59107525A (en) 1982-12-13 1982-12-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57217960A JPS59107525A (en) 1982-12-13 1982-12-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59107525A true JPS59107525A (en) 1984-06-21

Family

ID=16712417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57217960A Pending JPS59107525A (en) 1982-12-13 1982-12-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59107525A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52134376A (en) * 1976-05-06 1977-11-10 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS5469964A (en) * 1977-11-15 1979-06-05 Toshiba Corp Production of semiconductor device
JPS5724547A (en) * 1980-07-22 1982-02-09 Toshiba Corp Manufacture of semiconductor element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52134376A (en) * 1976-05-06 1977-11-10 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS5469964A (en) * 1977-11-15 1979-06-05 Toshiba Corp Production of semiconductor device
JPS5724547A (en) * 1980-07-22 1982-02-09 Toshiba Corp Manufacture of semiconductor element

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