JPS6386450A - Manufacture of substrate for formation of semiconductor element - Google Patents
Manufacture of substrate for formation of semiconductor elementInfo
- Publication number
- JPS6386450A JPS6386450A JP23271386A JP23271386A JPS6386450A JP S6386450 A JPS6386450 A JP S6386450A JP 23271386 A JP23271386 A JP 23271386A JP 23271386 A JP23271386 A JP 23271386A JP S6386450 A JPS6386450 A JP S6386450A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- amorphous
- single crystal
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 title description 14
- 238000004519 manufacturing process Methods 0.000 title description 7
- 230000015572 biosynthetic process Effects 0.000 title description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 abstract description 7
- 239000010980 sapphire Substances 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 238000001947 vapour-phase growth Methods 0.000 abstract description 2
- 229910052596 spinel Inorganic materials 0.000 description 3
- 239000011029 spinel Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要〕
サファイヤ基板や、マグネシャスピネル基板のような絶
縁性基板上に、単結晶シリコン(Si)層を形成して5
ilicon−ON−Insulator (以下SO
Iと称する)基板を形成し、このSi層に半導体素子を
形成するSol基板の形成方法であって、予め絶縁性基
板の裏面側にアモルファスSi層を形成した後、この基
板の表面にStエピタキシャル層を形成することで、S
iエピタキシャル層形成の際の熱処理によって絶縁性基
板が反らないようにする。[Detailed Description of the Invention] [Summary] A monocrystalline silicon (Si) layer is formed on an insulating substrate such as a sapphire substrate or a magnetic spinel substrate.
ilicon-ON-Insulator (hereinafter SO
A method for forming a Sol substrate in which a substrate (referred to as I) is formed and a semiconductor element is formed on this Si layer, in which an amorphous Si layer is formed in advance on the back side of an insulating substrate, and then an St epitaxial layer is formed on the surface of this substrate. By forming a layer, S
i Prevent the insulating substrate from warping due to heat treatment during epitaxial layer formation.
本発明は半導体素子形成用基板の製造方法に係わり、特
にSOI基板の製造方法に関する。The present invention relates to a method of manufacturing a substrate for forming semiconductor elements, and particularly to a method of manufacturing an SOI substrate.
サファイア基板や、マグネシャスピネル基板のような絶
縁性基板上に単結晶のSi層を形成し、SO■構造の半
導体素子形成用基板を形成し、このSi層に半導体素子
を形成すると、素子間分離工程が容易となったり、或い
は形成される素子の浮遊容量が減少する等の利点が有る
ため、高耐圧、高集積のIC等の半導体装置形成に最近
多く利用されるように成ってきている。A single-crystal Si layer is formed on an insulating substrate such as a sapphire substrate or a magnetic spinel substrate to form a substrate for forming a semiconductor element with an SO■ structure, and when a semiconductor element is formed on this Si layer, it is possible to Recently, it has been increasingly used in the formation of semiconductor devices such as high-voltage, highly integrated ICs because it has advantages such as facilitating the separation process and reducing the stray capacitance of the formed elements. .
従来、このようなSol構造の半導体素子形成用基板を
形成する際、第3図に示すように、厚さが50〜500
μ閑のサファイア、或いはマグネシャスピネルの絶縁性
基板l上に950℃〜1050℃の成長温度で、シラン
(5iH4)ガスを熱分解して、単結晶のSiエピタキ
シャルN2を0.1〜10μI程度の厚さに形成してい
た。Conventionally, when forming a substrate for forming a semiconductor element having such a Sol structure, as shown in FIG.
Silane (5iH4) gas is thermally decomposed on an insulating substrate of μ-free sapphire or magnetic spinel at a growth temperature of 950°C to 1050°C, and single-crystal Si epitaxial N2 is grown at a rate of about 0.1 to 10 μI. It was formed to a thickness of .
ところで、上記したサファイア基板の熱膨張率は、4.
6 Xl0−’/ ℃で、単結晶のSiの熱膨張率は、
2.5 Xl0−’/ ”Cで、その各々の熱膨張率は
異なっている。By the way, the coefficient of thermal expansion of the above-mentioned sapphire substrate is 4.
At 6 Xl0-'/°C, the coefficient of thermal expansion of single crystal Si is:
2.5 Xl0-'/''C, each having a different coefficient of thermal expansion.
そのため、基板表面に単結晶のSi層を850℃〜10
00℃の成長温度で形成後、室温まで基板を冷却すると
二基板が表面の方向に向かって凸型に反る問題があり、
この基板上に形成される単結晶のSi層にクランク3が
発生する問題があった。Therefore, a single crystal Si layer is placed on the substrate surface at 850°C to 10°C.
When the substrates are cooled to room temperature after being formed at a growth temperature of 00°C, there is a problem that the two substrates warp in a convex shape toward the surface.
There was a problem in that crank 3 occurred in the single crystal Si layer formed on this substrate.
この基板が反る問題は、形成されるSi層の膜厚が厚い
程、また絶縁物の基板が薄い程、顕著に現れる傾向があ
る。This problem of substrate warping tends to become more pronounced as the thickness of the formed Si layer increases and as the insulating substrate becomes thinner.
このような基板を用いて、その上に半導体素子を形成す
ると、その素子の特性が劣下する問題がある。When such a substrate is used and a semiconductor element is formed thereon, there is a problem that the characteristics of the element deteriorate.
本発明は上記した問題点を除去し、形成されるsor基
板が反らないようにした新規な半導体素子形成用基板の
製造方法の提供を目的とする。It is an object of the present invention to provide a novel method for manufacturing a substrate for forming semiconductor elements, which eliminates the above-mentioned problems and prevents the formed SOR substrate from warping.
本発明の半導体素子形成用基板の製造方法は、絶縁性基
板の裏面に予めアモルファスシリコンを形成した後、該
基板上にシリコン層をエピタキシャル成長する。In the method of manufacturing a substrate for forming a semiconductor element of the present invention, amorphous silicon is previously formed on the back surface of an insulating substrate, and then a silicon layer is epitaxially grown on the substrate.
本発明の半導体素子形成用基板の製造方法は、低温の気
相成長方法を用いて基板の裏面側に、予めアモルファス
Si層を、基板表面に形成するSiエタキシャル層と略
同−の厚さに形成する。このようにしてアモルファスS
i層を形成後、絶縁性基板の表面に単結晶のSi層を形
成する際の熱処理によって、このアモルファスSi層の
熱膨張係数が、単結晶のSiエピタキシャル層と同様な
熱膨張係数を有するようになるため、基板がこのエピタ
キシャル成長の際の熱処理で反らないようにして形成さ
れるSiエピタキシャル層内にクランクが発生しないよ
うにする。The method of manufacturing a substrate for forming a semiconductor element of the present invention uses a low-temperature vapor phase growth method to previously form an amorphous Si layer on the back side of the substrate to a thickness approximately the same as that of the Si etaxial layer formed on the surface of the substrate. Form. In this way, amorphous S
After forming the i-layer, heat treatment is performed when forming a single-crystal Si layer on the surface of the insulating substrate, so that the coefficient of thermal expansion of this amorphous Si layer is similar to that of the single-crystal Si epitaxial layer. Therefore, cranks are prevented from occurring in the Si epitaxial layer formed by preventing the substrate from warping during the heat treatment during epitaxial growth.
以下、図面を用いながら本発明の一実施例につき詳細に
説明する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第1図に示すように、厚さが50〜500μ−の単結晶
のサファイア基板11の裏面側に30〜200℃の成長
温度でプラズマCVD法によりアモルファスSi層12
を形成する。As shown in FIG. 1, an amorphous Si layer 12 is formed on the back side of a single crystal sapphire substrate 11 with a thickness of 50 to 500 μm by plasma CVD at a growth temperature of 30 to 200°C.
form.
ここで成長温度としては、なるべく室温に近い温度が、
その後基板を成長装置より取り出して室温まで冷却する
際の熱的歪を基板が受けないようにするために、好まし
い。Here, the growth temperature should be as close to room temperature as possible.
This is preferable in order to prevent the substrate from being subjected to thermal strain when the substrate is subsequently taken out from the growth apparatus and cooled to room temperature.
このアモルファスSi層12の厚さは、基板表面に形成
する単結晶のSi層とほぼ同一の厚さに形成する。The thickness of this amorphous Si layer 12 is approximately the same as that of the single crystal Si layer formed on the substrate surface.
次いで第2図に示すように基板の表面側にCVD法を用
いて成長温度を850℃〜1000℃の温度として厚さ
が0.1〜10μ−の単結晶のSi層13を形成する。Next, as shown in FIG. 2, a single-crystal Si layer 13 having a thickness of 0.1 to 10 .mu.m is formed on the front surface of the substrate using the CVD method at a growth temperature of 850 DEG C. to 1000 DEG C..
このようにすれば、基板表面に単結晶のSiエピタキシ
ャル層を形成する場合、その温度上昇によって絶縁性基
板11の裏面側に付着しているアモルファスSi層は、
多結晶Si層の結晶構造に移行し、基板の熱膨張を妨げ
る応力を殆ど加えない。In this way, when forming a single-crystal Si epitaxial layer on the substrate surface, the amorphous Si layer adhering to the back side of the insulating substrate 11 due to the temperature rise will be
The crystal structure of the polycrystalline Si layer is shifted to that of the polycrystalline Si layer, and almost no stress is applied to the substrate to prevent its thermal expansion.
また単結晶のSiエピタキシャル層が形成された後には
、この裏面側のアモルファスSi層は多結晶、或いは単
結晶となって、基板の表面側に形成された単結晶のSi
層とほぼ同一の熱膨張率となるため、基板の反りを押さ
えることができる。Furthermore, after the single crystal Si epitaxial layer is formed, the amorphous Si layer on the back side becomes polycrystalline or single crystal, and the single crystal Si layer formed on the front side of the substrate becomes polycrystalline or single crystal.
Since the thermal expansion coefficient is almost the same as that of the layer, it is possible to suppress warping of the substrate.
このようにすれば、表面に半導体素子形成用の単結晶の
Siエピタキシャル層を形成した場合でも、形成される
SOI基板に反りが発生せず、かつ基板にクラック等が
発生しないため、高信頼度のSol基板が得られる。In this way, even if a single-crystal Si epitaxial layer for semiconductor element formation is formed on the surface, the formed SOI substrate will not warp and cracks will not occur in the substrate, resulting in high reliability. A Sol substrate is obtained.
以上述べたように、本発明の半導体素子形成用基板の製
造方法によれば、形成されるsoy基板に反りを発生せ
ず、高信頼度のSOI基板が得られ、このような基板上
に素子を形成すれば、高集積化した半導体装置が得られ
る効果がある。As described above, according to the method of manufacturing a substrate for forming a semiconductor element of the present invention, a highly reliable SOI substrate can be obtained without causing warpage in the formed SOI substrate, and elements can be formed on such a substrate. By forming this, a highly integrated semiconductor device can be obtained.
第1図、および第2図は本発明の方法を工程順に示す断
面図、
第3図は従来のsor基板の形成方法を説明するための
断面図である。
図に於いて、
11はサファイア基板、12はアモルファスSt層、第
4ε胡のアU七ケスS1形メV工翠1図第1図
オ崎菱七五つ隼参馴J’BSi層形へJじ消」石へ第2
図
骸/l sot羞導し?形戒方竣(r歌を勧1田Z@3
図1 and 2 are cross-sectional views showing the method of the present invention in the order of steps, and FIG. 3 is a cross-sectional view for explaining the conventional method of forming a SOR substrate. In the figure, 11 is a sapphire substrate, 12 is an amorphous St layer, 4th ε Hu's A U seven cases S1 type V engineering 1 Figure 1 Osaki Hishishi seven five Hayabusa familiar J'BSi layer J Jizu” to the stone 2nd
Mukuro/l sot guide? Completed form of precepts
figure
Claims (1)
タキシャル成長して基板を形成する方法に於いて、 前記絶縁性基板(11)の裏面側に予めアモルファスシ
リコン層(12)を形成した後、該基板(11)上に単
結晶シリコン層(13)をエピタキシャル成長すること
を特徴とする半導体素子形成用基板の製造方法。[Claims] In a method of forming a substrate by epitaxially growing a silicon layer on the surface of a single-crystal insulating substrate (11), an amorphous silicon layer (12) is formed in advance on the back side of the insulating substrate (11). ) is formed, and then a single crystal silicon layer (13) is epitaxially grown on the substrate (11).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23271386A JPS6386450A (en) | 1986-09-29 | 1986-09-29 | Manufacture of substrate for formation of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23271386A JPS6386450A (en) | 1986-09-29 | 1986-09-29 | Manufacture of substrate for formation of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6386450A true JPS6386450A (en) | 1988-04-16 |
Family
ID=16943615
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23271386A Pending JPS6386450A (en) | 1986-09-29 | 1986-09-29 | Manufacture of substrate for formation of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6386450A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012044115A (en) * | 2010-08-23 | 2012-03-01 | Fujitsu Ltd | Method of manufacturing semiconductor device, and semiconductor device |
US20120058621A1 (en) * | 2000-11-27 | 2012-03-08 | Fabrice Letertre | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
JP2013513944A (en) * | 2009-12-11 | 2013-04-22 | ナショナル セミコンダクター コーポレーション | Backside stress compensation of gallium nitride or other nitride-based semiconductor devices |
JP2015216329A (en) * | 2014-05-13 | 2015-12-03 | 日本電信電話株式会社 | Method for manufacturing semiconductor device |
-
1986
- 1986-09-29 JP JP23271386A patent/JPS6386450A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120058621A1 (en) * | 2000-11-27 | 2012-03-08 | Fabrice Letertre | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
US10002763B2 (en) * | 2000-11-27 | 2018-06-19 | Soitec | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
JP2013513944A (en) * | 2009-12-11 | 2013-04-22 | ナショナル セミコンダクター コーポレーション | Backside stress compensation of gallium nitride or other nitride-based semiconductor devices |
JP2018190988A (en) * | 2009-12-11 | 2018-11-29 | ナショナル セミコンダクター コーポレーションNational Semiconductor Corporation | Backside stress compensation for gallium nitride or other nitride-based semiconductor devices |
JP2021158391A (en) * | 2009-12-11 | 2021-10-07 | ナショナル セミコンダクター コーポレーションNational Semiconductor Corporation | Backside stress compensation for gallium nitride or other nitride-based semiconductor device |
JP2012044115A (en) * | 2010-08-23 | 2012-03-01 | Fujitsu Ltd | Method of manufacturing semiconductor device, and semiconductor device |
JP2015216329A (en) * | 2014-05-13 | 2015-12-03 | 日本電信電話株式会社 | Method for manufacturing semiconductor device |
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