JPS62101024A - Epitaxial-growth wafer - Google Patents

Epitaxial-growth wafer

Info

Publication number
JPS62101024A
JPS62101024A JP24233485A JP24233485A JPS62101024A JP S62101024 A JPS62101024 A JP S62101024A JP 24233485 A JP24233485 A JP 24233485A JP 24233485 A JP24233485 A JP 24233485A JP S62101024 A JPS62101024 A JP S62101024A
Authority
JP
Japan
Prior art keywords
substrate
thin film
semiconductor thin
films
epitaxial growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24233485A
Other languages
Japanese (ja)
Inventor
Goro Sasaki
吾朗 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP24233485A priority Critical patent/JPS62101024A/en
Publication of JPS62101024A publication Critical patent/JPS62101024A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To offset compressive force and expansion force, and to manufacture a wafer having no warpage by forming the same semiconductor thin-films on both surfaces of a substrate. CONSTITUTION:Silicon such as double-side polished silicon is used as a substrate 1, and a gallium-arsenic layer 2 is shaped onto both surfaces through an organic metallic decomposition vapor phase growth method. Accordingly, crystalline semiconductor thin-films cannot be formed onto both surfaces of the substrate by a device which has been used, but the thin-films can be shaped by employing an improved device in which a reaction gas flows on both surfaces of the substrate as shown in the figure.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、エピタキシャル成長ウェファに関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to epitaxial growth wafers.

〔従来技術とその°問題点〕[Prior art and its problems]

従来より、種々の結晶性半導体基板面上に、種々の単層
あるいは多層よりなる結晶性半導体薄膜を有するエピタ
キシャル成長ウェファが製造されており、これらのエピ
タキシャル成長ウェファを用いて各種の電子デバイスあ
るいは光デノくイスが作製されている。良好な電気的特
性を有する前記半導体薄膜層を得るためには、一般に5
00°C以上の温度において、前記半導体薄膜層を前記
基板面上に形成する。
Conventionally, epitaxial growth wafers having various single-layer or multilayer crystalline semiconductor thin films on various crystalline semiconductor substrates have been manufactured, and these epitaxial growth wafers are used to manufacture various electronic devices or optical devices. A chair is being made. In order to obtain the semiconductor thin film layer with good electrical properties, generally 5.
The semiconductor thin film layer is formed on the substrate surface at a temperature of 00°C or higher.

従来は、前記基板の片面上にのみ前記半導体薄膜層を形
成していたため、前記基板と前記半導体薄膜層の熱膨張
係数が異なるとき、半導体薄膜層形成後室温まで冷却す
るとエピタキシャル成長ウェファが反り、デバイスを製
造する工程において種々の障害を生じていた。
Conventionally, the semiconductor thin film layer was formed only on one side of the substrate, so when the thermal expansion coefficients of the substrate and the semiconductor thin film layer were different, the epitaxial growth wafer would warp when cooled to room temperature after forming the semiconductor thin film layer, causing the device to deteriorate. Various problems have occurred during the manufacturing process.

〔問題を解決するための手段〕[Means to solve the problem]

本発明は、上記問題点を解決するために、基板両面上に
半導体薄膜層を形成せしめたものである。
In order to solve the above problems, the present invention forms semiconductor thin film layers on both sides of a substrate.

〔作 用〕[For production]

基板片面のみに半導体薄膜層を形成した従来の構造にお
いて、エピタキシャル成長ウェファに反りを生じていた
原因は、半導体薄膜層と基板の熱膨張係数の違いにより
、半導体薄膜層を形成した際の温度と室温との温度差に
より半導体薄膜層に基板に対して圧縮力あるいは膨張力
が生じるためであり、この圧縮力あるいは膨張力が基板
の片面のみに作用するためにバイメタルの原理によりエ
ピタキシャル成長ウェファに反りを生じる。したがって
、基板の両面に同じ半導体薄膜を形成することにより、
前記圧縮力あるいは膨張力は相殺し合ってエピタキシャ
ル成長ウェファに反りは生じない。
In the conventional structure in which a semiconductor thin film layer was formed only on one side of the substrate, the cause of warpage in the epitaxially grown wafer was due to the difference in thermal expansion coefficient between the semiconductor thin film layer and the substrate, and the temperature at which the semiconductor thin film layer was formed and the room temperature. This is because compression or expansion force is generated in the semiconductor thin film layer with respect to the substrate due to the temperature difference between . Therefore, by forming the same semiconductor thin film on both sides of the substrate,
The compression or expansion forces cancel each other out, so that no warpage occurs in the epitaxially grown wafer.

〔実施例〕〔Example〕

第1図に本発明の一実施例を示す。本実施例では、両面
研磨した。例えばシリコンを基板1として、その両面上
に有機金属分解気相成長法に上りガリウム・ひ素層2を
形成したものである。このように基板両面上に結晶性半
導体薄膜を形成するには、従来用いられていた装置では
不可能であったため、例えば第2図に示したように基板
の両面に反応ガスが流れるように改善した装置を用いる
ことにより可能となる。
FIG. 1 shows an embodiment of the present invention. In this example, both sides were polished. For example, a silicon substrate 1 is used, and gallium/arsenic layers 2 are formed on both sides thereof by metal organic decomposition vapor phase epitaxy. Forming a crystalline semiconductor thin film on both sides of the substrate in this way was impossible with conventional equipment, so improvements were made to allow the reactive gas to flow on both sides of the substrate, for example, as shown in Figure 2. This is possible by using a device that

〔発明の効果〕〔Effect of the invention〕

本発明により反りの無いエピタキシャル成長ウェファを
製造することが可能になる。
The present invention makes it possible to produce epitaxially grown wafers without warping.

東回面の簡単な説明 第1図は、本発明の一実施例であるエピタキシャル成長
ウェファの断面図、第2図はエピタキシャル成長ウェフ
ァを製造するための装置の模式図であり、第2図(a)
は横方向から本装置を見た図、第2図(b)はその断面
図である。
Brief explanation of the east plane FIG. 1 is a cross-sectional view of an epitaxially grown wafer that is an embodiment of the present invention, and FIG. 2 is a schematic diagram of an apparatus for manufacturing the epitaxially grown wafer.
2 is a view of the device viewed from the side, and FIG. 2(b) is a cross-sectional view thereof.

l:シリコン基板、2:ガリウム・ひ素層、3:基板、
4二基板支持台、5:反応管、6:反応ガス、7二基板
加熱用光源、8:基板加熱用反射鏡。
l: silicon substrate, 2: gallium arsenic layer, 3: substrate,
4: Two substrate support stands, 5: Reaction tube, 6: Reaction gas, 7: Two substrate heating light sources, 8: Substrate heating reflector.

Claims (4)

【特許請求の範囲】[Claims] (1)結晶性半導体基板面上に該基板と異なる熱膨張係
数を有する単層または多層よりなる結晶性半導体薄膜を
有するウェファにおいて、前記基板両面上に前記薄膜層
を有することを特徴とするエピタキシャル成長ウエフア
(1) Epitaxial growth in a wafer having a crystalline semiconductor thin film consisting of a single layer or multiple layers having a coefficient of thermal expansion different from that of the substrate on the surface of the crystalline semiconductor substrate, characterized in that the thin film layer is provided on both surfaces of the substrate. Uehua.
(2)結晶性半導体基板がシリコンあるいはゲルマニウ
ムよりなり、結晶性薄膜が化合物半導体よりなることを
特徴とする特許請求範囲第1項記載のエピタキシャル成
長ウェファ。
(2) The epitaxial growth wafer according to claim 1, wherein the crystalline semiconductor substrate is made of silicon or germanium, and the crystalline thin film is made of a compound semiconductor.
(3)化合物半導体がガリウム・ひ素であることを特徴
とする特許請求範囲第2項記載のエピタキシャル成長ウ
ェファ。
(3) The epitaxially grown wafer according to claim 2, wherein the compound semiconductor is gallium arsenide.
(4)基板の両面に反応ガスが流れる気相成長装置を用
いたことを特徴とする特許請求範囲第1項記載のエピタ
キシャル成長ウェファ。
(4) The epitaxial growth wafer according to claim 1, characterized in that a vapor phase growth apparatus is used in which a reactive gas flows on both sides of the substrate.
JP24233485A 1985-10-28 1985-10-28 Epitaxial-growth wafer Pending JPS62101024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24233485A JPS62101024A (en) 1985-10-28 1985-10-28 Epitaxial-growth wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24233485A JPS62101024A (en) 1985-10-28 1985-10-28 Epitaxial-growth wafer

Publications (1)

Publication Number Publication Date
JPS62101024A true JPS62101024A (en) 1987-05-11

Family

ID=17087649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24233485A Pending JPS62101024A (en) 1985-10-28 1985-10-28 Epitaxial-growth wafer

Country Status (1)

Country Link
JP (1) JPS62101024A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63304618A (en) * 1987-06-03 1988-12-12 Hitachi Cable Ltd Semiconductor wafer and manufacture thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5258363A (en) * 1975-11-10 1977-05-13 Hitachi Ltd Formation of semiconductor layer
JPS53113473A (en) * 1977-03-14 1978-10-03 Nec Corp Vapor phase growth method of si crystal

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5258363A (en) * 1975-11-10 1977-05-13 Hitachi Ltd Formation of semiconductor layer
JPS53113473A (en) * 1977-03-14 1978-10-03 Nec Corp Vapor phase growth method of si crystal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63304618A (en) * 1987-06-03 1988-12-12 Hitachi Cable Ltd Semiconductor wafer and manufacture thereof

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