JP2898320B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device such as a light emitting diode.

[Prior Art] A light emitting diode in which a compound semiconductor layer is formed on a silicon substrate has been proposed, and this configuration is manufactured by a two-stage growth method. That is, this is a technique in which after forming a compound semiconductor layer in an amorphous state at a relatively low temperature on a silicon substrate, annealing is performed, and then the compound semiconductor layer is formed at a normal growth temperature. When the thickness of such a compound semiconductor layer is 4 μm or more, there is a problem that cracks are generated in GaAs due to a difference in thermal expansion coefficient between silicon and the compound semiconductor such as GaAs. The thermal expansion coefficients of silicon and GaAs are 2.5 × 10 ⁻⁶ and 5.8 × 10 ⁻⁶ , respectively.

In order to solve such a problem, a coating layer made of an electrically insulating material such as SiO ₂ is formed on a silicon substrate in a predetermined pattern, and a through hole is formed in a predetermined portion for forming a light emitting diode array. And a method of selectively growing GaAs on the silicon substrate in the through hole has been proposed.

FIG. 8 is a sectional view for explaining such a method.
In the first step, as shown in FIG. 8A, an electrically insulating coating layer 2 made of SiO ₂ or the like is formed on the surface-treated silicon substrate 1 over the entire surface. In the second stage, as shown in FIG. 8 (2), the through holes 3 are selectively formed corresponding to the shape of the light emitting diode array. In the third stage, as shown in FIG. 8 (3), a GaAs layer 4 is formed on the silicon substrate 1 in the through hole 3.
Grow selectively. After subjecting the GaAs layer 4 to a heat treatment,
A semiconductor element having a PN junction is formed to form a semiconductor array. The heat treatment is to apply a thermal cycle between a temperature higher than the temperature at which the GaAs layer 4 was grown and a temperature lower than the temperature at the time of growth.

[Problems to be Solved by the Invention] In such prior art, according to the experiment of the present inventor, 85 ° C. was set as a temperature higher than the temperature at the time of growing the GaAs layer 4.
The etch pit density (abbreviated EPD) was 7 × 10 ⁶ cm ⁻² after a total of four thermal cycles were performed between 0 ° C. and a temperature lower than the growth temperature. . On the other hand, when the GaAs layer 4 is grown on the entire surface of the silicon substrate 1 without forming the coating layer 2, the etch pit density is 5 ×
10 ⁶ cm ^-2 . Therefore, the covering layer 2 is formed and GaAs
Even if the layer 4 is selectively grown, the effect of performing a heat treatment by applying a thermal cycle is small.

An object of the present invention is to provide a method for manufacturing a semiconductor device capable of reducing the etch pit density.

Means for Solving the Problems According to the present invention, a silicon substrate is covered with an electrically insulating coating layer, a hole is formed in the coating layer by etching, and a groove corresponding to the hole is formed in the silicon substrate. Forming
Next, a III-V compound semiconductor layer is buried and grown in the trench at a required temperature, and thereafter, a thermal cycle is applied to the buried layer between a temperature higher and lower than the required temperature. This is a method for manufacturing a semiconductor device.

[Operation] According to the present invention, the step of coating a silicon substrate with an electrically insulating coating layer and forming a hole in the coating layer and the step of forming a groove in the silicon substrate are simultaneously performed by etching. Workability is good, and productivity is improved. A III-V group compound semiconductor layer is buried and grown in the trench at a required temperature.
A thermal cycle is applied to the group V compound semiconductor layer between a temperature higher than the required temperature and a temperature lower than the required temperature. Therefore, a relatively large thermal stress acts on the buried layer in the groove of the silicon substrate due to thermal stress during a thermal cycle. Thereby, misfit dislocations at the interface between the silicon substrate and the buried layer can be reduced, and the etch pit density can be reduced.

Embodiment FIG. 1 is a cross-sectional view of a semiconductor device 1 according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor device 1. First, as shown in FIG. 2A, an electrically insulating coating layer 3 is formed on a silicon substrate 2 by a plasma chemical vapor deposition method. This coating layer 3 is, for example, silicon nitride or silicon oxide. This coating layer 3
Is, for example, 1000 °.

Next, as shown in FIG. 2 (2), a photoresist 4 is formed on the coating layer 3 and a through hole 5 is formed in a portion where the semiconductor element 1 is to be formed. Next, as shown in FIG. 2 (3), through holes 6 are formed in the coating layer 3 using an etching solution such as hydrofluoric acid or ammonium fluoride, and the silicon substrate 2 faces the through holes 6. A groove or recess 7 is formed. According to the experiment of the present inventor, the depth d1 of the groove 7 is desirably 1 μm or more, preferably 1.5 μm or more, in order to reduce misfit dislocations and reduce the etch pit density. Choose. For example, semiconductor element 1
Is configured as a light emitting diode, and when the planar shape of the light emitting region is 60 × 60 μm, the length D1 of one side of the groove 7 is 60 μm.
Choose m. The coating layer 3 is thus etched by
Since the through holes 6 are formed in the silicon substrate 2 and the grooves 7 facing the through holes 6 are simultaneously formed in the silicon substrate 2, the manufacturing process is simplified and the productivity is excellent.

The inner surface 7a of the groove 7 has a crystal plane <111>, which helps reduce misfit dislocations by combining misfit dislocations when a thermal cycle described below is applied.

After forming the through holes 6 and the grooves 7 in this manner, the resist 4 is removed.

Subsequent steps are performed with reference to the graph shown in FIG. First, the groove 7 formed in the silicon substrate 2 is
In W1, thermal cleaning of the groove 7 is performed to remove oxides on the surface. For this purpose, the substrate 2 on which the coating layer 3 is formed is evacuated to, for example, about 10 ^-7 Torr, and the substrate 2 is brought to a temperature T3 of 900 by induction heating.
The temperature is raised to 1,0001,000 ° C., preferably 950 ° C., and at this time, an atmosphere of hydrogen gas H _{2 as} a carrier gas and arsine AsH ₃ is continued for about 10 minutes.

In the next period W2, the thermally cleaned substrate 2
A first layer 51 as a low-temperature buffer layer is formed in the groove 7 as shown in FIG. 2 (4). The first layer 51 is set at a temperature T1 of, for example, 400 to 450 ° C., preferably 420 ° C., and trimethylgallium (CH 3)
₃ ) While supplying ₃ Ga (abbreviated TMG), arsine AsH ₃
Supply. TMG gas is introduced at a flow rate of, for example, 30 to 80 sccm, and arsine is supplied at a flow rate of 500 to 700 sccm. In this manner, the first layer 51 made of amorphous GaAs is
To 400 °, preferably 200 °.

In the next period W3, the second layer 52, which is a GaAs crystal layer, is fully grown. For this purpose, a TMG gas is transported by a hydrogen gas as a carrier gas, and arsine is added to the TMG gas.
℃, more preferably about 720 ℃. The flow rate of arsine is 500-700 sccm, and the total flow rate of hydrogen gas, TMG gas and arsine is 2200 sccm. Thus, the second layer 52 is formed with a thickness of, for example, 1.5 μm or more.

In this state, a first heat cycle is given in a period W4. At this time, a temperature T1a lower than the temperature T2 during crystal growth, for example, 100 ° C. or room temperature, and a temperature T2a higher than the temperature T2 during crystal growth, for example, 700 to 950 ° C., preferably about 850 ° C.
In the range, the temperature is repeatedly increased / decreased to give a thermal cycle. For example, temperature T2a is repeated four times. The holding time W4a of the temperature T2a is, for example, about 5 minutes. At this time, hydrogen gas and arsine are supplied. The temperature T2a is preferably a high temperature in order to eliminate or coalesce misfit dislocations, but in order to prevent As from becoming vapor and scattered, that is, to maintain the partial pressure of As. Is set to the temperature T2a in the range of 700 to 950 ° C. as described above.

By giving a thermal cycle during such a period W4, the silicon substrate 2 and the first layer 51,
Misfit dislocations generated at the interface with the layer 52 are reduced.
That is, by giving this thermal cycle, the first
The layer 51 and the second layer 52 generate a relatively large thermal stress in the groove 7 of the substrate 2, thereby sufficiently reducing the misfit dislocation as described above. The reason is that the linear expansion coefficient of silicon of the substrate 2 is 25 to 42 × 10 ⁻⁶ , while the linear expansion coefficient of GaAs that is the first layer 51 and the second layer 52 is 64 × 10 6.
^-6 , because such a difference in linear expansion coefficient causes thermal stress as described above. The coating layer 3 also functions to generate a large thermal stress in the first layer 51 and the second layer 52.

The surface of the second layer 52 substantially matches the upper surface of the substrate 2.

Next, in a period W5, a third layer 53 made of GaAs is formed at a temperature T2 in an atmosphere of hydrogen gas, TMG gas and arsine with a layer thickness of 0.8 μm, for example, as shown in FIG. 2 (5).

Thereafter, in order to form a light emitting diode on the third layer 53 as shown in FIG.
54 are formed, and thereafter, in a period W7, a p-AlGaAs layer 55 is formed, and this Pp junction surface is obtained as a light emitting surface.

According to the experiment of the present inventor, the etch pit density at the interface between the surface of the groove 7 of the silicon substrate 2 and the first layer 51 is:
It was 5 × 10 ⁶ cm ⁻² , confirming that it was significantly reduced as compared with the above-mentioned prior art.

FIG. 4 is a sectional view of another embodiment of the present invention. This embodiment is similar to the embodiment shown in FIGS. 1 to 3 and corresponding parts are denoted by the same reference numerals. It should be noted that, in this embodiment, the third layer 53 in FIG. 1 is omitted, and the n-AlGa
An As layer 54 and a p-AlGaAs layer 55 are formed.

In forming such a semiconductor element 1a shown in FIG. 4, the manufacturing process shown in FIG. 5 is employed.
The manufacturing process shown in FIG. 5 corresponds to the third embodiment of the above-described embodiment.
It is similar to the figure, and in this embodiment, in particular, the third layer 53 is not formed, and thus the growth period W5 is omitted. Other manufacturing steps are the same as those of the embodiment described with reference to FIG.

FIG. 6 is a graph showing the experimental results of the present inventor. First layer of FIG. 1 formed in groove 7 of silicon substrate 2
It is understood that the etch pit density can be reduced by increasing the total layer thickness d2 of the first layer 51, the second layer 52, and the third layer 53.

In the present invention, the first layer 5 is formed in the groove 7 of the silicon substrate 2.
1. In order to improve the crystallinity in producing a semiconductor device by giving a thermal cycle while epitaxially growing the second layer 52 and the third layer 53, an organic metal group thermal decomposition vapor deposition method ( MOCVD (abbreviation) is used, and a specific manufacturing apparatus for performing the MOCVD is shown in FIG.

The MOCVD apparatus is provided with a reaction tube 21 made of, for example, quartz or the like, inside which a susceptor 22 coated with graphite with silicon carbide SiC is placed, on which the silicon substrate 10 is mounted. A high-frequency coil 24 is wound around the reaction tube 21, and high-frequency power is supplied from a high-frequency power supply (not shown) to heat the susceptor 22 by induction.

The first tank 25 which is communicated with the reaction tube 21 is filled with hydrogen gas H ₂ carrier gas, arsine AsH ₃ is filled in the second tank 26. The hydrogen gas from the first tank 25 is highly purified through a purifier 28, and its flow rate is adjusted by mass flow controllers (hereinafter abbreviated as MFC) 29, 30. Also, the gas flow rate from the second tank 26
Adjusted by 1.

The above-mentioned TMG (trimethylgallium) is used as an organic metal, which is liquid at normal temperature and stored in a bubbler 33 installed in a thermostat 34.

The carrier gas from the purifier 28 is supplied to the bubbler 3 by the MFC 30.
It is introduced into 3 and performs bubbling.
The TMG in 3 is gasified and introduced into the reaction tube 21. This carrier gas is also used as a carrier gas for the gas from the second tank 26 via the MFC 29. MOCV like this
Gas control valves 37 and 38 and valves 40 to 44 are provided in a piping system for connecting components constituting the D apparatus.

An ultra-high vacuum exhaust device 35 and an exhaust gas treatment device 36 are connected to the reaction tube 21, and the ultra-high vacuum exhaust device 35 is used to remove residual gas in the reaction tube 21 prior to film formation. And
A toxic arsenic compound and the like in the exhaust gas during the film forming operation and after the film forming operation are removed using the exhaust gas processing device 36.

As another embodiment of the present invention, argon Ar or the like may be used as the carrier gas instead of hydrogen gas. The crystal layer may be, for example, GaP, AlGaAs, or the like in addition to the GaAs of the above-described embodiment, or may be InAs or another crystal layer.

[Effects of the Invention] As described above, according to the present invention, a III-V compound semiconductor layer is buried and grown in a groove formed in a silicon substrate facing a through hole of a coating layer. The thermal growth is applied to the layer grown between the temperature higher and lower than the required temperature during the growth, so that the buried layer is subjected to a relatively large thermal stress in the groove. As a result, misfit dislocations are reduced, and the etch pit density can be reduced. In addition, since the step of forming the through hole in the coating layer and forming the groove facing the through hole in the silicon substrate is performed by etching, the workability is good and the productivity can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device manufactured by the method of one embodiment of the present invention, FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor device of one embodiment of the present invention, and FIG. FIG. 4 is a graph showing a manufacturing process, FIG. 4 is a sectional view of a semiconductor device manufactured by the method of another embodiment of the present invention, FIG. 5 is a graph showing a manufacturing process of another embodiment of the present invention, FIG. Is a graph showing the relationship between the thickness of the semiconductor layer and the etch pit density, FIG. 7 is a system diagram showing a manufacturing apparatus for carrying out the present invention,
FIG. 8 is a sectional view for explaining a manufacturing process of the prior art. 1, 1a ... semiconductor element, 2 ... silicon substrate, 3 ... coating layer, 5, 6 ... through hole, 7 ... groove, 51 ... first layer, 52 ... second layer, 53 ... 3rd layer

Claims (1)

(57) [Claims] 1. A silicon substrate is coated with an electrically insulating coating layer, a hole is formed in the coating layer by etching, and a groove is formed in the silicon substrate corresponding to the hole.
Next, a III-V compound semiconductor layer is buried and grown in the trench at a required temperature, and thereafter, a thermal cycle is applied to the buried layer between a temperature higher and lower than the required temperature. Semiconductor device manufacturing method.