JPH03173182A - Semiconductor element and manufacture of the same - Google Patents

Abstract

PURPOSE:To lower the etched pit density by growing a III-V compound semiconductor layer to fill a groove corresponding to a through hole in a silicon substrate on which an insulating coating layer is formed. CONSTITUTION:An electrical insulating coating layer having a through hole 6 is formed on a silicon substrate 2 and a groove 7 facing the through hole 6 is made in the silicon substrate 2 and filled with a III-V compound semiconductor layer grown therein at the required temperature. Heat cycles are applied to the embedded layer 7 between higher and lower temperatures than the required temperature. Therefore, the comparatively large thermal stress of the grown embedded layer in the heat cycles acts on the groove 7 of the silicon substrate. Hence misfit dislocation on the interface between the silicon substrate and the grown embedded layer is reduced and the etched pit density is lowered. To reduce the misfit dislocation and lower the etched pit density, the depth a1 of the groove 7 is preferably 1mum or larger or more preferably 1.5mum or larger.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device such as a light emitting diode, and a method for manufacturing the same.

[Prior Art] A light emitting diode in which a compound semiconductor layer is formed on a silicon substrate has been proposed, and this structure is manufactured by a two-step growth method. That is, this is a technique in which an amorphous compound semiconductor layer is formed on a silicon substrate at a relatively low temperature, annealed, and then a compound semiconductor layer is formed at a normal growth temperature.

When the thickness of such a compound semiconductor layer exceeds 4 μm, there is a problem that cracks occur in the GaAs due to the difference in coefficient of thermal expansion between silicon and the compound semiconductor, such as GaAs. The thermal expansion coefficients of silicon and GaAs are 2.5 x 10-6 and 5.8 x 10-', respectively.
It is.

In order to solve these problems, a coating layer made of an electrically insulating material such as SiO is formed on a silicon substrate in a predetermined pattern, and then applied to a predetermined portion to form a light emitting diode array. A method has been proposed in which a through hole is formed and GaAs is selectively grown on a silicon substrate within the through hole.

FIG. 8 is a cross-sectional view illustrating such a method. The first step, as shown in FIG. 8 (1), is to deposit an electrically insulating film made of S i 02 or the like on a surface-treated silicon substrate 1. A transparent coating layer 2 is formed on the entire surface.

In the second step, as shown in FIG. 8(2), through holes 3 are selectively formed in accordance with the shape of the light emitting diode array.

In the third step, as shown in FIG. 8(3), a GaAs layer 4 is selectively grown on the silicon substrate 1 in the through hole 3. After heat-treating the GaAs layer 4, a semiconductor element having a PN junction is formed to construct a semiconductor array. The heat treatment means applying a thermal cycle between a temperature higher and lower than the temperature at which the GaAs layer 4 is grown.

[Issues to be solved by the invention In such prior art, according to the experiments of the present inventor,
8 as a temperature higher than the temperature during growth of the GaAs layer 4.
After a total of four thermal cycles between a temperature of 50° C. and a temperature lower than the growth temperature, the etch bit density (abbreviated as EPD) was 7×10′ cm−”. On the other hand, when the GaAs layer 4 was grown on the entire surface of the silicon substrate 1 without forming the coating Ji2, the ETS density was 5X10'cm-2.Therefore, by forming the coating layer 2, the GaAs layer 4 was Even if the As layer 4 is selectively grown, the effect of heat treatment by adding a thermal cycle is small.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce etch bit density.

[Means for Solving the Problems] The present invention involves forming grooves corresponding to the through holes in a silicon substrate on which an electrically insulating coating layer having through holes is formed, and filling the grooves with:
- A semiconductor element characterized in that a group V compound semiconductor layer is grown in a buried manner.

The present invention also provides the steps of forming an electrically insulating coating layer on a silicon substrate, forming through holes in the coating layer by etching, and forming grooves corresponding to the through holes in the silicon substrate,
Next, ①-V group compound semiconductor layer is grown so as to be buried in the layer at a required temperature, and then a thermal cycle is applied to the buried layer between a temperature higher and a temperature lower than the required temperature. A method of manufacturing a semiconductor device is characterized in that:

[Function] According to the present invention, an electrically insulating coating layer having a through hole is formed on a silicon substrate, a groove is formed in the silicon substrate facing the through hole, and a ■-v group compound is injected into this groove. A semiconductor layer is buried and grown at a predetermined temperature, and a thermal cycle is applied to the buried-grown compound semiconductor layer between a temperature higher and a temperature lower than the required temperature. Therefore, relatively large thermal stress acts on the buried layer within the groove of the silicon substrate due to thermal stress during thermal cycles. As a result, misfit dislocations at the interface between the silicon substrate and the buried layer can be reduced, and the etch bit density can be reduced.

Further, according to the present invention, the steps of forming holes in the coating layer and forming holes in the silicon substrate are performed simultaneously by etching, thus improving workability and productivity.

[Example 1] FIG. 1 is a cross-sectional view of a semiconductor device 1 according to an example of the present invention, and FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device 1. First, as shown in FIG. 2(1), an electrically insulating coating layer 3 is formed on a silicon substrate 2 by plasma chemical vapor deposition. This covering layer 3 is, for example, silicon nitride or silicon oxide. The thickness of this coating layer 3 is, for example, 1000 layers.

Next, as shown in FIG. 2(2), a photoresist 4 is formed on the covering layer 3, and a through hole 5 is formed in a region where the semiconductor element 1 is to be formed. Next, as shown in FIG. 2(3), a through hole 6 is formed in the coating layer 3 using an etching solution such as hydrofluoric acid or ammonium fluoride, and a hole 6 is formed in the silicon substrate 2 facing the through hole 6. A groove or recess 7 is formed. According to experiments conducted by the present inventor, the depth al of this groove 7 is preferably selected to be 1 μm or more, preferably 15 μm or more, in order to reduce misfit dislocations and reduce the etch bit density. For example, when the semiconductor element 1 is configured as a light emitting diode and the planar shape of its light emitting area is 60×60 μm, the length Dl of one side of the square 7 is selected to be 60 μm.

In this way, the through holes 6 are formed in the coating layer 3 by etching, and the grooves 7 facing the through holes 6 are simultaneously formed in the silicon substrate 2, so that the manufacturing process is simplified and productivity is excellent.

The inner surface 7a of the groove 7 binds the crystal plane <111>, thereby helping to reduce misfit dislocations by coalescing them when a thermal cycle described below is applied.

After forming the through holes 6 and forming the grooves 7 in this manner, the resist 4 is removed.

The subsequent steps are performed with reference to the graph shown in FIG.
1, the groove 7 is thermally cleaned to remove acidic substances on its surface. For this purpose, the substrate 2 on which the coating layer 3 is formed is evacuated to, for example, about 10-' Torr, and the substrate 2 is heated to a temperature of T by induction heating.
3, the temperature is raised to 900 to 1,000°C, preferably 950°C, and at this time hydrogen gas H2 as a carrier gas is heated.
and arsine AsH, and continue for about 10 minutes.

In the next period W2, the thermally cleaned substrate 2
A first layer 51, which is a low temperature buffer layer, is formed in the groove 7 as shown in FIG. 2(4). This first layer 51 has a temperature T1
For example, the temperature is set at 400 to 450°C, preferably 420°C, and trimethylgallium (CH3) 3G a (abbreviated as TMG) is supplied using hydrogen gas as a carrier gas, as well as arsine AsH. TMG gas is introduced at a flow rate of, for example, 30 to 80 seconds, and arsine is supplied at a flow rate of 500 to 700 seconds.

In this way, the first layer 5 made of amorphous GaAs
1 to a thickness of 100 to 400 layers, preferably 200 layers. )1' In the next period W3, the 21st m5 which is the GaAs crystal layer
2 to grow. For this purpose, TMG gas is transported by hydrogen gas, which is a carrier gas, and arsine is added to it, and the temperature is T2. For example, 620-750℃
, preferably 660 to 720°C, more preferably about 720°C.

The flow rate of arsine is 500 to 700 sec, and the total flow rate of hydrogen gas, TMG gas, and arsine is 2200 sec.
Supply in m. Thereby, the thickness of the second layer 52 is, for example, 1.5 μm or more.

In this state, a first thermal cycle is applied during period W4. At this time, a temperature T1a lower than the temperature T2 during crystal growth,
For example, 100℃ or room temperature and the temperature T during crystal growth.
a temperature T2a higher than 2, for example 700-950°C,
A thermal cycle is provided by repeatedly increasing/decreasing the temperature, preferably in a range of about 850°C. For example, temperature T2a is repeated four times. The holding time W4a of the temperature T2a is, for example, about 5 minutes. At this time, hydrogen gas and arsine are supplied. Although it is preferable that the temperature T2a is high enough to eliminate or coalesce misfit dislocations, it must be set at a high temperature in order to prevent As from becoming vapor and scattering, that is, to maintain the partial pressure of As. , as mentioned above, is set at the temperature T2a in the range of 700 to 950°C.

By applying a thermal cycle during such a period W4, the silicon substrate 2 and the first layer 51, which is a GaAs layer, are
Misfit dislocations generated at the interface between the first layer and the second layer 52 are reduced. That is, by applying this thermal cycle, the first layer 51 and the second layer 52 are heated within the well 7 of the substrate 2.
Relatively large thermal stresses are created, which, as mentioned above, are sufficient to reduce misfit dislocations. it is,
The linear expansion coefficient of silicon of the substrate 2 is 25 to 42×101
, whereas the first layer 51 and the second layer 52 are G
The linear expansion coefficient of aAs is 64X10, and such a
This is because thermal stress is generated as described above due to the difference in expansion coefficients. The covering layer 3 also has a first layer 51 and a second layer 51.
It serves to generate large thermal stresses in layer 52.

The surface of the second layer 52 substantially coincides with the top surface of the substrate 2 .

Next, in period W5, a third layer 53 made of GaAs is formed at temperature T2 in an atmosphere of hydrogen gas, TMG gas, and arsine, with a layer thickness of, for example, 0.8 μm, as shown in FIG. 2 (5). .

Thereafter, in order to form a light emitting diode on the third layer 53 as shown in FIG.
After forming the aAs layer 54, in period W7, p-A
An I GaAs layer 55 is formed, and this pn junction surface is obtained as a light emitting surface.

According to experiments by the inventor of the present invention, the etch pit density at the interface between the surface of the edge 7 of the silicon substrate 2 and the first layer 51 is as follows:
5X10'cm-'', compared to the prior art mentioned above.
A significant reduction was confirmed.

FIG. 4 is a sectional view of another embodiment of the invention.

This embodiment is similar to the embodiment shown in FIGS. 1 to 3 above, and corresponding parts are given the same reference numerals. The layer 53 is omitted, and on the second layer 52 there is a n layer constituting the light emitting diode.
-A1' GaAs layer 54 and p-AlGaAs layer 55 are formed.

In constructing the semiconductor element 1a shown in FIG. 4, the manufacturing process shown in FIG. 5 is adopted.

The manufacturing process shown in FIG. 5 is the third step in the above embodiment.
Similar to the figure, especially in this example, since the third layer 53 is not formed, its growth period W5 is omitted. Other manufacturing steps are similar to the embodiment described in connection with FIG.

FIG. 6 is a graph showing the experimental results of the inventor of the present invention.

The first layer 51 in FIG. 1 formed in the groove 7 of the silicon substrate 2
It can be seen that the etch bit density can be reduced by increasing the total layer thickness d2 of the second layer 52 and the third layer 53.

In the present invention, the first layer 51 is formed on the base 7 of the silicon substrate 2.
, the second layer 52 and the third layer 53 are epitaxially grown and subjected to a thermal cycle to improve crystallinity when manufacturing a semiconductor element. A specific manufacturing apparatus for carrying out this MOCV method is shown in FIG.

The MOCVD apparatus is provided with a reaction tube 21 made of, for example, quartz, and silicon carbide (Si) is placed inside.
A susceptor 22 coated with graphite is arranged,
A high frequency coil 24 is wound around the zero reaction tube 21 on which the silicon substrate 10 is placed, and high frequency power is supplied from a high frequency power source (not shown) to heat the susceptor 22 by induction.

A first tank 25 communicating with the reaction tube 21 is filled with hydrogen gas H2 carrier gas, and a second tank 26 is filled with arsine A s H).

The hydrogen gas from the first tank 25 is highly purified through the purifier 28, and its flow rate is adjusted by a mass flow controller (hereinafter abbreviated as MFC).The gas flow rate from the second tank 26 is also , are each adjusted by the MFC 31.

TMG (trimethyl gallium) is used as the organic metal, and is liquid at room temperature, and is stored in a bubbler 33 installed in a constant temperature bath 34.

The carrier gas from the purifier 28 is introduced into the bubbler 33 by the MFC 30 to perform bubbling, whereby TMG in the bubbler 33 is gasified and introduced into the reaction tube 21 . This carrier gas is also used as a carrier gas for the gas from the second tank 26 via the MFC 29. The piping system that connects the components that make up such MOCVD equipment includes gas regulating valves 37, 38 and R/
Revs 40-44 are provided.

An ultra-high vacuum evacuation device 35 and an exhaust gas treatment device 36 are connected to the reaction tube 21, and the ultra-high vacuum evacuation device 3
5 is used to remove residual gas in the reaction tube 21 prior to film formation, and an exhaust gas treatment device 36 is used to remove toxic arsenic compounds in the exhaust gas during and after the film formation process. do.

As an embodiment of the pond of the present invention, the carrier gas may be argon (Ar, etc.) instead of hydrogen gas. In addition to GaAs in the above embodiment, the crystal layer is made of GaP, Aj
! It may be GaAs or the like, and it may also be I nA.
s or other crystal layers.

[Effects of the Invention] As described above, according to the present invention, the ■-V group compound semiconductor layer is buried and grown in the hole formed in the silicon substrate facing the through hole of the coating layer, and the buried growth is Because the layer is thermally cycled between higher and lower temperatures than required during its growth, the buried layer is exposed to a relatively large thermal stress, which causes Misfit dislocations are reduced, and the etch pit density can be reduced. Furthermore, since the steps of forming the through holes in the coating layer and forming grooves facing the through holes in the silicon substrate are performed by etching, the workability is good and the productivity can be improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, and FIG.
The figure is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG. 1, FIG. 3 is a graph showing the manufacturing process shown in FIG. 2, and FIG. 5 is a graph for explaining the manufacturing method of the semiconductor device shown in FIG. 4, FIG. 6 is a graph showing the relationship between the thickness of the semiconductor layer and the niche pitch 1~density, and FIG. FIG. 8 is a system diagram showing a manufacturing apparatus for carrying out the invention, and is a sectional view illustrating the manufacturing process of the prior art. 1.1a...Semiconductor element, 2...Silicon substrate, 3
...Covering layer, 5.6...Through hole, 7...Groove, 51...
・First layer, 52...second layer, 53...third layer

Claims (2)

[Claims] (1) In a silicon substrate on which an electrically insulating coating layer having through holes is formed, grooves are formed corresponding to the through holes, and in the grooves III-
A semiconductor device characterized in that a group V compound semiconductor layer is grown in a buried manner. (2) Form an electrically insulating coating layer on a silicon substrate, form a through hole in the coating layer by etching, form a groove corresponding to the through hole in the silicon substrate, and then fill the groove with III- A semiconductor device characterized in that a group V compound semiconductor layer is grown so as to be buried at a predetermined temperature, and then a thermal cycle is applied to the buried layer between a temperature higher and a temperature lower than the required temperature. manufacturing method.