JP3005281B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor element formed by forming a single crystal semiconductor layer, for example, a GaAs layer, made of a group III-V compound semiconductor on a silicon substrate, and a semiconductor device comprising the same. To a method for manufacturing.

[Prior Art] When a GaAs crystal layer is formed on a silicon substrate by a metal organic chemical vapor deposition (abbreviated MOCVD) method, first, as shown in FIG. in the presence of hydrogen gas H ₂ and arsine AsH _3, the temperature T1
3 (for example, 950 ° C.) for about 10 minutes to remove the oxide layer on the surface of the silicon substrate and perform thermal cleaning.

Next, in the period W12, in the presence of hydrogen gas, arsine, and trimethylgallium (CH ₃ ) ₃ Ga (abbreviated as TMG), the temperature T11
(Eg, 420 ° C.), thereby forming a thin layer of approximately 200 ° of GaAs in the amorphous state on the silicon substrate.

Then, in period W13, hydrogen gas, arsine and TMG
Is maintained at a temperature T12 (for example, 660 to 760 ° C.), whereby the amorphous GaAs is crystallized and a GaAs crystal layer is further laminated.

In this way, a crystal whose surface morphology is a mirror surface is obtained.

[Problems to be solved by the invention] In such a prior art, although a single-domain single-crystal GaAs crystal layer can be obtained with a mirror surface, many interfaces are formed at the interface between the silicon substrate and the GaAs formed thereon. Fit dislocations occur and their etch pit densities (abbreviations)
EPD) is a very high value of 1 × 10 ⁸ cm ⁻² .

An object of the present invention is to provide a semiconductor device capable of reducing the etch pit density and a method of manufacturing the same.

Means for Solving the Problems According to the present invention, a base layer is formed by growing a GaP layer on a silicon substrate at a temperature lower than the crystal growth temperature and then performing annealing within the crystal growth temperature. After growing a GaAs _1-x P _x (0 <x <1) layer below the crystal growth temperature on the underlayer, annealing is performed within the crystal growth temperature to form an intermediate underlayer. Thereafter, a group III-V compound semiconductor layer is formed on the intermediate base layer.

The present invention, on a silicon substrate, a base layer is formed by annealing in the range of crystal growth temperature after growing a layer of AlP below the crystal growth temperature, then, AlAs on the underlying layer _{1 After} growing a layer of xP _x (where 0 <x <1) below the crystal growth temperature, annealing is performed within the crystal growth temperature to form an intermediate underlayer. A method for manufacturing a semiconductor device, comprising forming a group III-V compound semiconductor layer.

[Operation] According to the manufacturing method of the present invention, a layer of GaP or AlP is grown on a silicon substrate at a temperature lower than the crystal growth temperature, and then annealed within the range of the crystal growth temperature to form an underlayer.
Next, on this underlayer, when the underlayer is GaP, GaA
s _1-x P _x layer or AlAs _1-x P _x when the underlying layer is AlP
Is grown below the crystal growth temperature, and then annealed within the crystal growth temperature range to form an intermediate underlayer, and then a III-V compound semiconductor layer is formed on the intermediate underlayer. The lattice constant from the silicon substrate
As a result, the etch pit density can be further reduced, and the crystallinity of the III-V compound semiconductor layer can be significantly improved.

Example FIG. 1 is a graph showing a procedure of a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor device manufactured thereby. References in FIG.
Reference numeral 10 denotes a silicon semiconductor substrate.
Has a surface obtained by turning off from the <100> crystal plane of the silicon single crystal in the <011> crystal plane direction by 0.5 to 4 degrees, preferably twice.

First, the silicon substrate 10 is subjected to thermal cleaning in a period W1 to remove oxide on the surface thereof. For this purpose, the substrate 10 is heated by induction heating in an atmosphere in which the substrate 10 is evacuated to, for example, about 10 ⁻⁷ Torr.
Is raised to 900 to 1,000 ° C., preferably 950 ° C. as a temperature T3. At this time, an atmosphere of hydrogen gas H _{2 as} a carrier gas and arsine AsH ₃ is maintained for about 10 minutes.

In the next period W2, the thermally cleaned substrate 10
A first underlayer 11 as a first underlayer, which is a low-temperature buffer layer made of GaP, is formed thereon. This first layer 11 has a temperature
T1 is set to a temperature lower than the crystal growth temperature, for example, a low temperature of 400 to 500 ° C., preferably 420 to 450 ° C., and trimethylgallium (CH ₃ ) ₃ Ga
Supplies (abbreviation TMG), supplies a phosphine PH _3. TMG gas is introduced at a flow rate of, for example, 30 to 80 sccm,
The phosphine is supplied at a flow rate of 500-700 sccm. Thus, the first layer 11 made of amorphous GaP is formed to a thickness of 100 to 200.
Å, preferably 120-130Å, formed thin.

In the next period W3, a second layer 12 as a second underlayer made of GaAs as another low-temperature buffer layer is formed on the first layer 11. The second layer 12 has a temperature T2 of, for example, 400 to 500
C., preferably 420-450 ° C., and trimethylgallium (CH ₃ ) ₃ Ga (abbreviated TMG) is supplied by hydrogen gas as a carrier gas, and arsine AsH ₃ is supplied. TMG gas is introduced at a flow rate of, for example, 30 to 80 sccm, and arsine is supplied at a flow rate of 500 to 700 sccm. Thus, the second layer 12 made of amorphous GaAs is formed with a layer thickness of 100 to 400.
Å, preferably 200Å.

The temperature T2 at which the second layer 12 is formed is equal to or higher than the temperature T1 at which the first layer 11 is formed (T2 ≧ T1), and is lower than the crystal growth temperature. The thickness of the second layer 12 is equal to or greater than the thickness of the first layer 11. Thereby, misfit dislocations at the interface between the silicon substrate 10 and the first layer 11 can be sufficiently reduced.

The sum of the thickness of the first layer 11 and the thickness of the second layer 12 needs to be less than 500 ° to reduce misfit dislocations.

In the next period W4, the third layer 13, which is a GaAs crystal layer, is fully grown. For this purpose, a TMG gas is transported by a hydrogen gas as a carrier gas, and arsine is added thereto to raise the crystal growth temperature T2a, for example, 620 to 750 ° C, preferably 660 to 720 ° C, and more preferably about 720 ° C. Warm up.
The flow rate of arsine is 500-700 sccm, and the total flow rate of hydrogen gas, TMG gas and arsine is 2200 sccm. Thus, the third layer 13 is formed with a thickness of, for example, 1.5 μm. Further, a light emitting diode having a pn junction surface made of, for example, n-AlGaAs and p-AlGaAs is formed on the third layer 13.

Table 1 shows lattice constants and linear expansion coefficients of silicon Si, GaP, and GaAs.

The first layer 11 of GaP has an intermediate value between the lattice constant and the coefficient of linear expansion between silicon and GaAs. Therefore, the first layer 11 is etched to reduce misfit dislocations between the silicon substrate and the first layer 11. It is understood that the pit density can be reduced.

As shown in FIGS. 1 and 2, on the silicon substrate 10, the first layer 11 which is a GaP crystal layer and the second and third layers 12 and 13 which are GaAs crystal layers are epitaxially grown. In manufacturing semiconductor devices with improved performance,
An organometallic thermal decomposition vapor deposition method (abbreviated MOCVD method) is used, and a specific manufacturing apparatus for performing the MOCVD method is shown in FIG.

The MOCVD apparatus is provided with a reaction tube 21 made of, for example, quartz or the like, inside which a susceptor 22 coated with graphite with silicon carbide SiC is placed, on which the silicon substrate 10 is mounted. A high-frequency coil 24 is wound around the reaction tube 21, and high-frequency power is supplied from a high-frequency power supply (not shown) to heat the susceptor 22 by induction.

The first tank 25 which is communicated with the reaction tube 21 is filled with the carrier gas is hydrogen gas H _2, arsine AsH ₃ is filled in the second tank 26. The hydrogen gas from the first tank 25 is highly purified through a purifier 28, and its flow rate is adjusted by mass flow controllers (hereinafter abbreviated as MFC) 29, 30. Also, the gas flow rate from the second tank 26
Adjusted by MFC31.

The above-mentioned TMG (trimethylgallium) is used as an organic metal, which is liquid at normal temperature and stored in a bubbler 33 installed in a thermostat 34.

The carrier gas from the purifier 28 is supplied to the bubbler 3 by the MFC 30.
It is introduced into 3 and performs bubbling.
The TMG in 3 is gasified and introduced into the reaction tube 21. This carrier gas is also used as a carrier gas for the gas from the second tank 26 via the MFC 29. MOCV like this
Gas control valves 37 and 38 and valves 40 to 44 are provided in a piping system for connecting components constituting the D apparatus.

An ultra-high vacuum exhaust device 35 and an exhaust gas treatment device 36 are connected to the reaction tube 21, and the ultra-high vacuum exhaust device 35 is used to remove residual gas in the reaction tube 21 prior to film formation. And
A toxic arsenic compound and the like in the exhaust gas during the film forming operation and after the film forming operation are removed using the exhaust gas processing device 36.

In another embodiment of the present invention, argon or the like may be used as the carrier gas instead of hydrogen gas. As the first layer 11, AlAs or AlP may be used instead of GaP. Al
The lattice constant of As is 5.661, and the lattice constant of AlP is 5.462.

According to the experiment of the present inventor, the etch pit density at the interface between the silicon substrate 10 and the first layer 11 of GaP is 5 × 10 ⁷
It was confirmed that it could be reduced to × 6 × 10 ⁷ cm ⁻² .

FIG. 4 is a graph showing a procedure of a method of manufacturing a semiconductor device according to another embodiment of the present invention, and FIG. 5 is a sectional view of a semiconductor device manufactured thereby. Parts corresponding to the above-described embodiments are denoted by the same reference numerals. Silicon substrate
For 10, thermal cleaning is performed in a period W1. This step is performed during the period of the embodiment described with reference to FIG.
Same as W1.

In the next period W2, the thermally cleaned substrate 10
A first crystal layer 14, which is a base layer made of GaP, is formed thereon. In forming the first crystal layer 14, first, a period W2
1, the temperature T21 is less than the crystal growth temperature, for example 400
~ 500 ° C, preferably 420-450 ° C, amorphous G
Grow a thin layer of aP. The thickness of this layer is 50-200Å
And preferably 120 to 130 °. For the growth of this layer, TMG and phosphine are supplied by hydrogen gas as a carrier gas.

In the next period W22, the Ga grown in the previous period W21
The layer made of P is heated to a temperature T22 to perform annealing. This temperature T22 is, for example, 650 to 800 ° C. Thus, the first crystal layer 14 is formed.

Therefore, next, in the periods W3a and W3b, a plurality of (two in this embodiment) crystal layers, which are intermediate underlayers, are sequentially formed. Of these second crystal layers 15 and 16, crystal layer 15
aAs _1-x P _x (where 0 <x <1) and the other layer 16
Is GaAs _1-y P _y (where 0 <y <1), and x> y (1). In other words, the composition of P in the second crystal layers 15 and 16 further increases It is selected to be smaller as approaching the semiconductor layer 17 formed on the substrate.

Of the period W3a for forming the crystal layer 15, in the period W3a1,
At a temperature T21 below the crystal growth temperature, (GaAs) _1-x and (Ga
P) grow _x thinly with a film thickness of 50-200Å.

In the next period W3a2, the crystal growth temperature T22, for example, 650 to
The temperature is set to 800 ° C., whereby annealing is performed.

In order to form another crystal layer 16 on the crystal layer 15, in the period W3b1 of the period W3b, the (GaAs) _1-y and (GaP) _y are converted at the temperature T21 lower than the crystal growth temperature. It is grown in the same manner as layer 15. In this layer 16, the composition y of P is smaller than the composition x of P in the crystal layer 15 as described in the first formula.

In the next period W3b2, annealing is performed by heating to the crystal growth temperature T22, and thus the crystal layer 16 is formed.

In the next period W4, a semiconductor layer 17 made of GaAs is deposited on the uppermost crystal layer 16 of the second crystal layers 15 and 16 by temperature.
Formed at T22.

In this manner, the lattice constant of each of the first crystal layer 14 and the second crystal layers 15 and 16 changes from the substrate 10 to the semiconductor layer 17 so as to be approximated stepwise. Therefore, misfit dislocations can be reduced, and the etch pit density can be reduced.

According to the experiment of the present inventor, in the embodiment shown in FIGS. 4 and 5, the etch pit density was 5 × 10 ⁷
It was confirmed to have decreased to ６6 × 10 ⁷ cm ⁻² .

FIG. 6 is a sectional view of a semiconductor device according to another embodiment of the present invention. This embodiment is similar to the embodiment shown in FIGS. 4 and 5, and the corresponding parts have the same reference characters.
It should be noted that in this embodiment, not only the above-described crystal layers 15 and 16 but also a crystal layer 18 is formed as the second crystal layer. The crystal layer 15 has GaAs _1-x P _x (where 0 <x <1), and the crystal layer 16 has GaAs _1-y P _y (where 0 <y <1).
Another crystal layer 18 is GaAs _1-z P _z (where 0 <z <1)
X>y> z (2) In this manner, the crystal layers 15, 16, and 18 are sequentially formed by repeating the steps of growth and annealing, so that the lattice constant changes sequentially from the silicon 10 to the semiconductor layer 17 and the lattice constant is changed. The constant approaches the value of the semiconductor layer 17. This makes it possible to further reduce misfit dislocations. In another embodiment of the present invention, such a second
The number of crystal layers 15 to 18 may be four or more. According to the experimental results of the present invention, it has been found that preferably three to five layers are preferable.

These crystal layers 15 to 18 are formed in the same manner as in the embodiment shown in FIGS. 4 and 5 described above.

FIG. 7 is a sectional view of a semiconductor device according to another embodiment of the present invention. In this embodiment, a first crystal layer AlP19 is formed on a silicon substrate 10, and second (two in this embodiment) second crystal layers 20 and 21 are formed thereon. Tier 2
A semiconductor layer 22 made of GaAs is formed on the uppermost crystal layer 21 of the layers 0 and 21. Of the second crystal layers 20 and 21, the crystal layer 2
0 is AlAs _1-x P _x (where 0 <x <1), and the other crystal layer 21 is AlAs _1-y P _y (where 0 <y <1). In addition, compared to the composition of the crystal layer 20, the crystal layer 21
Is selected to be small. As a result, the lattice constant gradually changes in a stepwise manner from the silicon substrate 10 to the semiconductor layer 22, so that misfit dislocations can be reduced. The crystal layers 20 and 21 are formed by processes similar to the crystal layers 14 and 15 in the embodiment shown in FIGS. These crystal layers 20, 21 may be formed in three or more layers.

As the semiconductor layers 13 and 17, other than GaAs, InAs and other III-V group compound semiconductors may be used.

[Effects of the Invention] As described above, according to the present invention, the silicon substrate and the III-
A base layer of GaP, AlAs, or AlP is interposed between the group V compound semiconductor layer, and the lattice constant and the linear expansion coefficient of the base layer of GaP, AlAs, or AlP are determined based on that of a silicon substrate and III such as GaAs. Since the semiconductor element has an intermediate value with that of the group-V compound semiconductor layer, the etch pit density is reduced, and the crystallinity of the group III-V compound semiconductor layer can be significantly improved. Is achieved.

According to the present invention, GaP, AlAs,
Alternatively, a first underlayer, which is a thin low-temperature buffer layer of AlP, is formed, and a second underlayer made of a III-V compound semiconductor is formed thereon.
An underlayer is grown, and the second underlayer has a temperature equal to or higher than the first underlayer and lower than the crystal growth temperature, and has a thickness equal to or higher than that of the first underlayer. Having a crystal growth temperature of III on the second underlayer.
Since the third layer made of a -V compound semiconductor is formed, it is possible to grow a good crystal having significantly improved crystallinity of the third layer.

In the present invention, in manufacturing such a semiconductor element,
After growing a layer of GaP or AlP on a silicon substrate,
Annealing to form an underlayer, followed by GaP or A
GaAs _1-x P _x or AlAs _1-x P _x
Is grown, annealing is performed after the growth, an intermediate underlayer is sequentially formed, and then a group III-V compound semiconductor layer is formed. Therefore, the etch pit density can be reduced. In addition, the crystallinity of the group III-V compound semiconductor layer can be greatly improved to grow good crystals.

[Brief description of the drawings]

FIG. 1 is a view for explaining a method of manufacturing a semiconductor device according to one embodiment of the present invention, FIG. 2 is a cross-sectional view of the semiconductor device, and FIG. 3 implements a manufacturing method according to one embodiment of the present invention. FIG. 4 is a diagram for explaining a method of manufacturing a semiconductor device according to another embodiment of the present invention, FIG. 5 is a sectional view of a semiconductor device realized by the method of FIG. 4, FIG. 6 is a sectional view of a semiconductor device according to another embodiment of the present invention, FIG. 7 is a sectional view of a semiconductor device according to still another embodiment of the present invention, and FIG. It is a figure for explaining. 10 silicon substrate, 11 first layer, 12 second layer, 13
... Third layer, 14, 19... First crystal layer, 15, 16, 20, 21... Second crystal layer, 17.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/20 H01L 21/205 H01L 21/203

Claims (2)

(57) [Claims] To 1. A silicon substrate, annealed within the range of crystal growth temperature after a layer of GaP grown below the crystal growth temperature to form an underlayer, then, GaAs on an underlying layer _{1- After} growing a layer of xP _x (where 0 <x <1) below the crystal growth temperature, annealing is performed within the crystal growth temperature to form an intermediate underlayer. A method for manufacturing a semiconductor device, comprising forming a III-V compound semiconductor layer. To 2. A silicon substrate, a base layer is formed by annealing in the range of crystal growth temperature after growing a layer of AlP below the crystal growth temperature, then, AlAs on the underlying layer _{1 After} growing a layer of xP _x (where 0 <x <1) below the crystal growth temperature, annealing is performed within the crystal growth temperature to form an intermediate underlayer. A method for manufacturing a semiconductor device, comprising forming a III-V compound semiconductor layer.