TW200907124A - Method for forming group-III nitride semiconductor epilayer on silicon substrate - Google Patents

Method for forming group-III nitride semiconductor epilayer on silicon substrate Download PDF

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TW200907124A
TW200907124A TW96130085A TW96130085A TW200907124A TW 200907124 A TW200907124 A TW 200907124A TW 96130085 A TW96130085 A TW 96130085A TW 96130085 A TW96130085 A TW 96130085A TW 200907124 A TW200907124 A TW 200907124A
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layer
forming
nitride
substrate
group iii
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TW96130085A
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TWI379021B (en
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Chun-Yen Chang
Tsung-Hsi Yang
Jet-Chung Chang
Jui-Tai Ku
Shih-Guo Shen
Yi-Cheng Chen
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Univ Nat Chiao Tung
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Abstract

High quality GaN on Si (111) substrate is grown by using AlN/SixNy/Si structure. The growth procedure of AlN/SixNy/Si structure is described as follows. Firstly, one monolayer of Al is deposited on silicon substrate for forming AlN nucleation layer. Then, low growth rate of AlN nucleation layer is performed in the lower growth temperature with suitable III-V stoichiometric. In the meantime, SixNy barrier layer is also accomplished during AlN nucleation layer growth process. And then, 2D growth of AlN layer in higher growth temperature is performed. Thereafter, the high temperature GaN epilayer or group-III semiconductor can be grown on the AlN/SixNy/Si structure with high growth rate.

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200907124 九、發明說明: 【發明所屬之技術領域】 本發明為一種形成三族氮化物半導體的方法,特別是 一種於石夕基板上形成三族氮化物半導體磊晶層的方法。 【先前技術】 傳統上在藍寶石(Sapphire)或石夕(Si)基板上成長 三族氮化物發光二極體(LED),或進行高電子遷移率電晶 體(High Electron Mobility Transistor,HEMT)磊晶結 構時’為降低通道層(Channei iayer)或作用層(Active layer)中的缺陷密度,可在藍寶石或矽基板上成長大於 l//m的氮化鎵緩衝層。 由於石夕的熱膨脹係數為2·59χ106 K—1,而氮化鎵的熱 膨服係數為5.59χ1〇-6 K_i,故而兩者的熱膨脹係數差異很 大’導致所成長的氮化鎵厚度在超過1/zm時,容易發生裂 痕(Crack) ’因此無法得到無裂痕(Crackfree)且具大面積 之三族氮化物半導體磊晶層。 而在長成二族氮化物半導體材料所用的氮來源(N source)為氨(Amm〇nia)與氮氣(No。但矽容易與氨產 生氮化梦絕緣層’進而阻止氮化鎵成長。當湘金屬有機 氣相化學沉積法以成長氮化鎵磊晶層時則極為明顯。 此外,在矽基板上利用金屬有機氣相化學沉積法 (M0CVD)以成長氡化鎵蟲晶層時,則需克服回融腐餘 (MeltbackEtching)現象。此現象是因為在高溫時,鎵與 5 200907124 矽易形成合金,且產生極快的腐蝕反應,將矽基板及所成 長的結晶層摧毀,最後產生粗糙表面及在矽基板上產生深 洞。而利用氮化鋁(A1N;)當緩衝層,則可以得到較佳的結 果。但使用金屬有機氣相化學沉積法的成長溫度高,因此 在磊晶層及矽基板介面之間,會產生非常嚴重的内部擴散 現象,形成非刻意的高摻雜濃度,以及非刻意摻雜所產生 的缺陷影響’皆都會嚴重影響磊晶層的品質。 因此傳統上冒利用分子線遙晶(M〇iecuiar beam epitaxy, MBE)活性氮氣電漿,於高溫矽基板上形成單晶 氮化矽擴散阻障層(Barrier layer)以抑制内部鋁、矽擴 散現象。此技術係利用高能(450Wh^性氮氣電漿直接轟擊 碎基板以形成單晶的氮化梦,但易造成表面缺陷,產生高 缺陷密度的氮化鎵磊晶層。而後續氮化鋁的形成則是利用 高溫回火使鋁的預原子層與下層氮化矽反應所產生,因此 氮化矽結構改變’而其擴散阻障功能會下降。此外,因高 溫所產生的雜質也會影響其後的磊晶品質。而此技術的另 一缺點為成長氮化鎵磊晶層的速率每小時只有〇 微米 (/zm),而不利於塊材的氮化鎵成長。 經檢索中華民國專利編號1272730「在矽底材成長三 族氮化物半導體異質磊晶結構的方法」,其中提出利用MBE 高能(450W)活性氮氣電漿於高溫矽基板上形成單晶的石型 氮化矽擴散阻障層(-Sil Barrier layer)以抑制内部的 I呂、石夕擴散現象。此乃因利用高能活性氮氣電裝直接義擊 矽基板表面易損傷矽基板產生缺陷’造成高缺陷密度的氣 200907124 化鎵蟲晶層。但此技術的另一困難點為:在厚度1. 5奈米 (nm)的召型氮化矽(p-SisN4)上沉積鋁預沉積原子層, 然後施以高溫回火得到氮化鋁’在鋁與万型氮化矽(/3 -Si3N4)高溫反應所形成氮化鋁的同時,也會改變β型氮化 矽的結構,使得擴散阻障層功能降低。且長時間的高溫回 火步驟會使腔體中的雜質擴散’破壞超高真空的環境,影 響磊晶品質。故利用此技術成長氮化鎵磊晶層時,其成長 速率每小時只有〇. 〇8微米(/i m) ’不利於氮化鎵塊材的成 長。 此外,Cong, W 在文獻 Journal of Crystal Growth 276 ( 2005) 381-388中提出利用金屬有機氣相化學沉積法 於1080°C時成長厚度為30微米的氮化鋁緩衝層,因鋁和 矽的共熔(Eutectic)溫度為577°C,而氮化鎵成長溫度為 1030°C ’因此在氮化鋁/矽、氮化鎵/氮化鋁介面,因内部 的擴散現象,造成高濃度摻雜,從而影響磊晶品質。 而如美國專利第 7, 001,457 號「Crystal growth method, crystal growth apparatus, group-III nitride crystal and group-111 nitride semiconductor device」專利中雖提出三 族氮化物晶體的相關成長方法與形成三族氮化物晶體的元 件,但並未於矽基半導體基板上施作,亦未提出任何控制 或是提高三族氮化物晶體品質的方法。 【發明内容】 本發明可降低切基板上成長氮化錄時, 因晶格不匹 配所導致產生的大#缺陷密度,進贿決因氮化㈣緣層 7 200907124 形成而降低氮化鎵成長率的問題。 較佳方法,其步形成三族氮化物半議晶層的 核層於該:二f基板。接著同時形成擴散阻Ρ*層以及成 最後,形成繼續長”核層以形成金屬氮化層。 又一姨虱化物層於金屬氮化物屉 三族氮化物半導體遙晶層。 a表面上,以成為 本發明之於矽基板上形成三族氮 另一較佳方法,其步驟包括了: I導體蠢晶層的 首先提供1 夕基板。接著同時形 上 上 上 層。然後形成第—三族氮化物層於第一 -跟著形成第二金屬氮化物層於第一::== 再形成第二三族氮化物層於第二 面上屬氣化物層於該第二三族氮化物層表 =,ί=ϊ第三三族氮化物層於第三金屬氮化物層表 面上藉以成為三族氮化物半導體 从氧本ΓΓ百分之十(1G%)濃度=氟酸溶液去除石夕 步去除氟離子及污染 件下本㈣崎子層㈣基板上;且在適當條 件下乂低射頻功率、低溫梯 氮化石夕絕緣層以及氮化銘成核層。化f -驟而瓜成早日日 月在田含鎵(Ga-rich)的條件下,以每小時長成 200907124 ο. 微米(//m)之厚度,且以高溫成長氮化鎵緩衝層。 本發明在適當❹】的濃度條件τ,湘低射頻㈣功 率、低溫梯度變化成長單晶氮仙成㈣。由於低低射頻 2及低溫梯度的變化’因此在紹原子層下方會先形成單 j切絕緣層’㈣_子層與活減氣錢反應形成 ㈣、° f成長溫度時,氮化紹成長速 適春厚二==銘層有利於降低線缺陷密度,且成長 田尽度的氮化財利鎵表面終結氮化鎵蟲晶層的成長。 【實施方式】 個^發明的主要目的在於利用成長溫度梯度變化的〆 板:二形成氮化石夕擴散阻障層及氮化銘成核層於石夕基 缺陷密氮化物半導體切基板上低成長速率及高 構物成核層結 陷密度的問題外,在上低成長速率及高缺 層於一降低==成氮化残散阻障 的方Γ基板上形成三族氮化物半導體遙晶廣 下圖:例如第1A圖至第,圖所示,詳細步驟如 如第1A «所示,首先提供石夕基板m 使其表面^離子覆蓋短時間不形成氧化 200907124 物,再藉高溫去除氟離子移除污染物。 接著如第1B圖所示’進行以單一步驟形成擴散阻障 ,層及低溫成核層於石夕基板1〇1上;主要乃利用成長溫度的 .梯度變化,同時於石夕基板101上形成氮化石夕(Si具)擴散 阻障層以及低溫氮化紹(A1N)的成核層。首先,控制溫度 約在5〇〇°C ’以進行沉積銘原子層(AIN nucleation layer) 103A於♦基板lG1表面上,其目的為減少#活性氮氣電裝 A擊石夕基板101後所產生之缺陷。當在低成長溫度時,此 時溫度約為600t,通入適當五三比例的活性氮氣電浆及 鋁源,此時活性氮氣電漿會氮化位於前述所沉積鋁原子層 103A下方的矽基板層1〇1,從而反應形成氮化矽層1〇2, 而如第1C圖所示。 如第1C圖所示,起初鋁原子層(成核層)1〇3A成長 速率會非常慢’但同時活性氮氣電漿也會與銘原子層形成 IU匕銘(A1N)層103。經反射式高能量電子繞射儀(RH膽) 分析結果顯示其圖案為點狀。當到達氮化銘成長溫度時, 鋁原子層103A成長速率會變快,開始趨向二維成長,經反 射式高能量電子繞射儀分析結果顯示其圖案變成線條狀。隨 後,約於溫度550°C至65ITC間,較佳溫度6〇〇°c,以成長 以形成適當厚度的低溫氮化鋁層1〇3。 . 最後,如第1D圖所示,此時溫度約為740它,每小時 長成0· 5微米(//οι)之厚度,形成氮化鎵層1〇4成長於氮 化鋁層103表面上,以成為半導體結構。 本發明之於石夕基板上形成三族氣化物半導體蠢晶層的 200907124 方法的第二實施例如第2A圖至第2D圖所示,詳細步驟如 下圖: 如第2A圖所示’重複前述第ία圖至第1D圖之步驟, 使得結構具有矽基板201 ’氮化矽層202於矽基板201上, 低溫氮化鋁層(第1氮化鋁層)203於氮化矽層202上, 且氮化鎵層204於氮化鋁層203上之半導體結構;接著, 約於溫度740°C至800°C間,較佳溫度78(TC,以形成高溫 氮化銘層(第2氮化鋁層)205於氮化鎵層(第1氮化鎵 層)204表面上。 繼續如第2B圖所示,約於溫度74〇°C,每小時長成〇. 5 微米(#m)之厚度,形成氮化鎵層(第2氮化鎵層)2〇6 於氮化銘層205表面上。 跟著如第2C圖所示,約於溫度74〇。〇至8〇(rc間,較 佳溫度780°C,以形成高溫氮化鋁層(第3氮化鋁層)2〇7 於氮化鎵層206表面上。 最後如第2D圖所示,約於溫度74〇<t ’每小時長成〇 5 微米(//Hi)之厚度,形成氮化鎵層(第3氮化鎵層)2〇8 於氮化I呂層207表面上。 本發明於上述結構中插人數層氮化㈣成為氮化紹 介面層(AIN interlayer),藉由介面應力將線缺陷侷限於 介面’讓其無法繼續往外傳_,達到降低上層三族氮化物 遙晶層缺陷密度之目的。 第3圖為氮化紹介面層樣品的χ光繞射分析圖。由分 析圖可看出本發明賴長的單錢切㈣基板與氮化紹 200907124 層之間,而氮化鎵的磊晶品質相當好,由雙晶軸X光繞射 分析其晶面(002)半高寬約1200 arcsec ° 第4圖為氮化鋁介面層樣品的13](光激螢光分析圖。 由光譜圖可知其中性施子束缚激子半高寬為20meV,根據 蝕刻方式,其缺陷密度約lxl〇9cm 2,跟長在藍寶石基板上 之結果相近。 # >本發明之特點在於矽基板可在百分之十(1〇%)濃度的 氫氟酸(HF)中去除氧化物,以氟離子保護矽基板不受氧 化。且本發明在超高真空環境中,以高溫進-步去除氟離 子及污染物。 、本發明在矽基板上低溫成長鋁(A1)原子層,用於降低 活性亂氣電㈣擊破壞石夕基板表面,提供氮化紹形成 制石夕與鋁共溶現象。 以上所述僅為本發明之較佳實施例而已,並非用以限 定本發明之申請專職圍;凡其它未脫離本發明所揭示之 精神下所元成之等效改變或修飾,均應包含在下述杜 專利範圍内。 a 【圖式簡單說明】 第1A圖至第1D圖所示為本發明之第一實施例。 第2A圖至第2D圖所示為本發明之第二實施例。 第3圖所不為氮化鋁介面層樣品的X光繞射分析圖。 第4圖所不為氣化!呂介面層樣品的版光激榮光分析圖。 200907124 【主要元件符號說明】 101矽基板 102氮化矽層 103A鋁原子層 103氮化鋁層 104氮化鎵層 201矽基板 202氮化矽層 203氮化鋁層 204氮化鎵層 205氮化銘層 206氮化鎵層 207氮化鋁層 208氮化鎵層 13200907124 IX. Description of the Invention: [Technical Field] The present invention is a method for forming a Group III nitride semiconductor, and more particularly to a method for forming a Group III nitride semiconductor epitaxial layer on a Shih-Hs. substrate. [Prior Art] Traditionally, a Group III nitride light-emitting diode (LED) has been grown on a Sapphire or Si Xi substrate, or a High Electron Mobility Transistor (HEMT) epitaxial crystal has been developed. In order to reduce the defect density in the Channei iayer or the active layer, a gallium nitride buffer layer larger than 1/m can be grown on the sapphire or germanium substrate. Since the thermal expansion coefficient of Shixi is 2·59χ106 K-1, and the thermal expansion coefficient of gallium nitride is 5.59χ1〇-6 K_i, the thermal expansion coefficients of the two are very different, resulting in the thickness of the grown gallium nitride. When it exceeds 1/zm, cracks are likely to occur. Therefore, a crack-free and large-area trivalent nitride semiconductor epitaxial layer cannot be obtained. The nitrogen source (N source) used in the growth of the group II nitride semiconductor material is ammonia (Amm〇nia) and nitrogen (No. However, it is easy to form a nitride insulating layer with ammonia) to prevent the growth of gallium nitride. The organic metal vapor phase chemical deposition method of Xiang metal is very obvious when growing the gallium nitride epitaxial layer. In addition, when the metal organic vapor phase chemical deposition method (M0CVD) is used on the germanium substrate to grow the gallium bismuth crystal layer, Overcome the phenomenon of MeltbackEtching. This phenomenon is because at high temperatures, gallium and 5 200907124 are easy to form alloys, and produce extremely fast corrosion reaction, destroying the ruthenium substrate and the grown crystal layer, and finally producing a rough surface. And a deep hole is formed on the germanium substrate, and aluminum nitride (A1N;) is used as the buffer layer to obtain better results. However, the metal organic vapor phase chemical deposition method has a high growth temperature, so the epitaxial layer and Between the substrate interface, a very serious internal diffusion phenomenon occurs, and the formation of unintentional high doping concentration and the influence of defects caused by unintentional doping will seriously affect the quality of the epitaxial layer. This traditionally utilizes M〇iecuiar beam epitaxy (MBE) active nitrogen plasma to form a single crystal silicon nitride diffusion barrier layer on a high temperature tantalum substrate to suppress internal aluminum and germanium diffusion. This technology utilizes high energy (450Wh^ nitrogen plasma directly bombards the substrate to form a single crystal nitriding dream, but easily causes surface defects, resulting in a high defect density gallium nitride epitaxial layer. And subsequent aluminum nitride The formation is caused by the reaction of the pre-atomic layer of aluminum with the lower layer of tantalum nitride by high-temperature tempering, so the structure of the tantalum nitride is changed, and the diffusion barrier function is lowered. In addition, the impurities generated by the high temperature also affect the After the epitaxial quality, another disadvantage of this technology is that the rate of growth of the gallium nitride epitaxial layer is only 〇 micron (/zm) per hour, which is not conducive to the growth of GaN of the bulk material. 1272730 "Method for growing a heterogeneous epitaxial structure of a Group III nitride semiconductor in a ruthenium substrate", which proposes a silicon-type lanthanum nitride diffusion barrier for forming a single crystal on a high-temperature tantalum substrate by using MBE high-energy (450W) active nitrogen plasma. The barrier layer (-Sil Barrier layer) suppresses the internal Ilu and Shixia diffusion phenomenon. This is because the high-energy active nitrogen electric device is used to directly hit the surface of the substrate, which is easy to damage the substrate and cause defects. Gallium worm layer, but another difficulty of this technique is: depositing an aluminum pre-deposited atomic layer on a thickness of 1.5 nm (p-SisN4), and then applying high temperature tempering The aluminum nitride formed by the high temperature reaction of aluminum and yttrium-nitride (/3 -Si3N4) can also change the structure of the β-type tantalum nitride, so that the function of the diffusion barrier layer is reduced. The high temperature tempering step of time will cause the impurities in the cavity to diffuse to destroy the ultra-high vacuum environment and affect the epitaxial quality. Therefore, when the gallium nitride epitaxial layer is grown by this technique, the growth rate is only 〇. 〇8 μm/(m) is not conducive to the growth of the gallium nitride bulk material. In addition, Cong, W, in the Journal of Crystal Growth 276 (2005) 381-388, proposes the use of metal organic vapor phase chemical deposition to grow an aluminum nitride buffer layer with a thickness of 30 microns at 1080 ° C due to aluminum and tantalum. The Eutectic temperature is 577 ° C, and the gallium nitride growth temperature is 1030 ° C. Therefore, in the aluminum nitride / tantalum, gallium nitride / aluminum nitride interface, due to internal diffusion phenomenon, high concentration doping , thus affecting the quality of the epitaxial. For example, in the "Crystal growth method, crystal growth apparatus, group-III nitride crystal and group-111 nitride semiconductor device" patent of U.S. Patent No. 7,001,457, the related growth method of the group III nitride crystal and the formation of the three families are proposed. The nitride crystal element, but not applied to the germanium based semiconductor substrate, does not suggest any way to control or improve the quality of the Group III nitride crystal. SUMMARY OF THE INVENTION The present invention can reduce the large defect density caused by lattice mismatch when growing nitride on a substrate, and reduce the growth rate of GaN by nitriding (4) edge layer 7 200907124. The problem. Preferably, the step of forming a core layer of a Group III nitride semi-rear layer is on the:f-substrate. Then, a diffusion barrier layer* is formed at the same time, and finally, a continuation of the long core layer is formed to form a metal nitride layer. Another vaporization layer is formed on the metal nitride tab group of the group III nitride semiconductor telecrystal layer. Another preferred method for forming a Group III nitrogen on a substrate of the present invention comprises the steps of: first providing a substrate of a stray layer of I conductor; then simultaneously forming an upper layer and then forming a first group of nitrides. Forming a first metal-nitride layer on the first--following first::== forming a second group III nitride layer on the second surface of the vaporized layer on the second group III nitride layer= ί ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ And the contaminated parts of the (four) Qizi layer (four) substrate; and under appropriate conditions, low RF power, low temperature ladder nitride nitride insulation layer and nitriding Ming nucleation layer. F- sudden and melon into the early days in the field Under the condition of gallium-containing (Ga-rich), it grows to 200907 per hour. 124 ο. The thickness of the micrometer (//m), and the gallium nitride buffer layer is grown at a high temperature. The present invention grows the single crystal nitrogen scent into a concentration condition τ, a low-frequency (four) power, and a low-temperature gradient. Due to the low and low RF 2 and low temperature gradient changes, so a single j-cut insulating layer will be formed below the atomic layer. (4) _ sub-layer and live gas reduction reaction formation (4), ° f growth temperature, nitriding growth rate The spring thickness of the second == Ming layer is conducive to reducing the line defect density, and the growth of the field of the zirconia gallium surface terminates the growth of the gallium nitride crystal layer. [Embodiment] The main purpose of the invention is to use growth. Temperature gradient gradient ruthenium plate: two problems of low-growth rate and high-structure nucleation layer crater density on the Nissin-bonded Nitride semiconductor dicing substrate In addition, a low-growth rate and a high-definition layer are formed on a square substrate of a reduced nitriding barrier, and a group III nitride semiconductor is formed on the substrate. For example, FIG. 1A to FIG. The detailed steps are as shown in 1A «, first providing Shi Xi The plate m has its surface covered with ions for a short time without forming oxidized 200907124, and then removing the fluoride ions by high temperature to remove the contaminants. Then, as shown in FIG. 1B, a diffusion barrier, a layer and a low temperature nucleation layer are formed in a single step. On the Shixi substrate 1〇1; mainly using the gradient of growth temperature, and forming a nitride barrier (Si) diffusion barrier layer and a low-temperature nitrided (A1N) nucleation layer on the Shixi substrate 101. First, the temperature is controlled at about 5 ° C to carry out the deposition of the AIN nucleation layer 103A on the surface of the substrate lG1, the purpose of which is to reduce the activity of the active nitrogen battery A substrate 101. The defect is that when the temperature is low, the temperature is about 600t, and the active nitrogen plasma and aluminum source are fed into the appropriate ratio of five to three. At this time, the active nitrogen plasma is nitrided under the above-mentioned deposited aluminum atom layer 103A. The ruthenium substrate layer 1〇1 is reacted to form a tantalum nitride layer 1〇2 as shown in FIG. 1C. As shown in Figure 1C, initially the aluminum atomic layer (nucleation layer) 1〇3A will grow very slowly. But at the same time, the active nitrogen plasma will also form the IU 匕 (A1N) layer 103 with the Ming atomic layer. The results of the analysis by a reflective high-energy electronic diffractometer (RH bile) show that the pattern is punctiform. When the nitriding temperature is reached, the growth rate of the aluminum atomic layer 103A becomes faster and begins to grow in two dimensions. The analysis results of the reflective high-energy electron diffractometer show that the pattern becomes a line. Thereafter, it is grown at a temperature of about 550 ° C to 65 ITC, preferably at a temperature of 6 ° C, to grow to form a low-temperature aluminum nitride layer 1 〇 3 of a suitable thickness. Finally, as shown in Fig. 1D, the temperature is about 740 at this time, and the thickness is 0.5 μm (//οι) per hour, and the gallium nitride layer 1〇4 is formed on the surface of the aluminum nitride layer 103. On, to become a semiconductor structure. A second embodiment of the method of forming a dodecant layer of a tri-family vaporized semiconductor on a stone substrate of the present invention is shown in FIGS. 2A to 2D, and the detailed steps are as follows: as shown in FIG. 2A, the above-mentioned The steps from FIG. 1D to FIG. 1D are such that the structure has a tantalum substrate 201 'the tantalum nitride layer 202 on the tantalum substrate 201, and a low temperature aluminum nitride layer (first aluminum nitride layer) 203 on the tantalum nitride layer 202, and a semiconductor structure of the gallium nitride layer 204 on the aluminum nitride layer 203; then, about 740 ° C to 800 ° C, preferably 78 (TC) to form a high temperature nitride layer (2nd aluminum nitride) The layer 205 is on the surface of the gallium nitride layer (first gallium nitride layer) 204. Continued as shown in FIG. 2B, the temperature is about 74 〇 ° C, and the thickness is 〇 5 μm (#m) per hour. Forming a gallium nitride layer (second gallium nitride layer) 2 〇 6 on the surface of the nitriding layer 205. As shown in Fig. 2C, the temperature is about 74 〇 〇 to 8 〇 (between rc, preferably The temperature is 780 ° C to form a high-temperature aluminum nitride layer (third aluminum nitride layer) 2 〇 7 on the surface of the gallium nitride layer 206. Finally, as shown in Fig. 2D, about 74 〇 < t ' per The thickness of the film is 5 micrometers (//Hi), and a gallium nitride layer (third gallium nitride layer) is formed on the surface of the nitrided layer 207. The present invention inserts a layer of nitrogen into the above structure. (4) becomes the AIN interlayer. The interface defect is limited to the interface by the interface stress, so that it can not continue to pass outside, so as to reduce the defect density of the upper triad nitride crystal layer. It is a calender diffraction analysis diagram of the nitrided surface layer sample. It can be seen from the analysis chart that the single-cutting (four) substrate of the invention is between the substrate and the nitridium 200907124 layer, and the epitaxial quality of gallium nitride is quite good. The dichroic X-ray diffraction analysis of the crystal plane (002) half-height width of about 1200 arcsec ° Figure 4 is the aluminum nitride interface layer sample 13] (photo-fluorescence analysis chart. From the spectrum to know the neutral The half-height width of the applicator exciton is 20meV, and the defect density is about lxl〇9cm 2 according to the etching method, which is similar to the result of growing on the sapphire substrate. # > The invention is characterized in that the substrate is 10% (1〇%) concentration of hydrofluoric acid (HF) to remove oxides, fluoride ions to protect germanium substrates The invention is oxidized, and the invention further removes fluoride ions and pollutants at a high temperature in an ultra-high vacuum environment. The invention grows low-temperature aluminum (A1) atomic layer on a ruthenium substrate for reducing active gas (four) Destroying the surface of the stone substrate, providing the phenomenon of co-dissolution of the stone and the aluminum. The above is only a preferred embodiment of the present invention, and is not intended to limit the application for the full-time application of the present invention; The equivalent changes or modifications of the elements disclosed in the spirit of the invention should be included in the following patents. a [Simplified description of the drawings] Figs. 1A to 1D show the first embodiment of the present invention. . 2A to 2D are diagrams showing a second embodiment of the present invention. Figure 3 is not an X-ray diffraction analysis of the aluminum nitride interface layer sample. Figure 4 is not for gasification! Lu Jie surface layer sample version of the light glory analysis. 200907124 [Description of main components] 101矽 substrate 102 tantalum nitride layer 103A aluminum atom layer 103 aluminum nitride layer 104 gallium nitride layer 201 germanium substrate 202 tantalum nitride layer 203 aluminum nitride layer 204 gallium nitride layer 205 nitride Ming layer 206 gallium nitride layer 207 aluminum nitride layer 208 gallium nitride layer 13

Claims (1)

200907124 十、申請專利範圍: 1. 一種於矽基板上形成三 法,至少包含: 矢虱化物半導體磊晶層的方 提供一碎基板; 同時形成一擴散阻障層以 县忐兮士成核層於該矽基板上. 長成該成核層以形成-金屬氮傲上, 形成一三族氮化物層於該金屬曰,以及 該三族氮化物半導縣晶層。t化物層表面上,以成為 2. 如申請專利範圍第】項所述之於 物半導體蟲晶層的方法,其中土板上$成二知氮化 及該成核層於_基板L =、=成該擴散阻障層以 沉積一鋁原子層於該矽基板 \3 . 及 攸衣面上以成為該成核層;以 通入一活性氮氣電漿及—鋁 ^ 原子層下方之_基板層,心化所沉積之該銘 3. 如申請專利範圍第丨項所迷散阻障層。 物半導體遙晶層的方法,其中&板上形成二族鼠化 化矽。 、T讀擴散阻障層至少包含氮 4. 如申請專利範圍第1項所 物半導體蠢晶層的方法,就;石夕基板上形成三族氮化 鋁。 一中該成核層至少包含氮化 5. 如申請專利範圍第1項所 物半導體蟲晶層的方法,复基板上形成三族氮化 氮化鋁。 /、中礒金屬氮化物層至少包含 200907124 6. 如申請專利範圍第1項所述之於矽基板上形成三族氮化 物半導體磊晶層的方法,其中該三族氮化物層至少包含 氮化鎵。 7. —種於矽基板上形成三族氮化物半導體磊晶層的方 法,至少包含: 提供一砍基板; 同時形成一擴散阻障層以及一成核層於該矽基板上,係 沉積一銘原子層於該石夕基板表面上以成為一成核層,通入 一活性氮氣電漿及一鋁源,藉以氮化所沉積之該鋁原子層 下方之該矽基板層,反應形成該擴散阻障層; 長成該成核層以形成一金屬氮化物層;以及 形成一三族氮化物層於該金屬氮化層表面上,以成為該 二族氮化物半導體遙晶層。 8. 如申請專利範圍第7項所述之於矽基板上形成三族氮化 物半導體磊晶層的方法,其中該擴散阻障層至少包含氮 化石夕。 9. 如申請專利範圍第7項所述之於矽基板上形成三族氮化 物半導體磊晶層的方法,其中該成核層至少包含氮化 鋁。 10. 如申請專利範圍第7項所述之於矽基板上形成三族氮 化物半導體磊晶層的方法,其中該金屬氮化物層至少包 含氮化鋁。 11. 如申請專利範圍第7項所述之於矽基板上形成三族氮 化物半導體磊晶層的方法,其中該三族氮化物層至少包 15 200907124 含氮化錄。 12. —種於矽基板上形成三族氮化物半導體磊晶層的方 法,至少包含: 提供一碎基板; 同時形成一擴散阻障層以及一成核層於該矽基板上; 長成該成核層以形成一第一金屬氮化物層; 形成一第一三族氮化物層於該第一金屬II化物層表面 上; 形成一第二金屬氮化物層於該第一三族氮化物層表面 上; 形成一第二三族氮化物層於該第二金屬氮化物層表面 上; 形成一第三金屬氮化物層於該第二三族氮化物層表面 上;以及 形成一第三三族II化物層於該第三金屬氮化物層表面 上;以成為該三族氮化物半導體磊晶層。 13. 如申請專利範圍第12項所述之於矽基板上形成三族氮 化物半導體磊晶層的方法,其中同時形成該擴散阻障層 以及該成核層於該矽基板上,至少包含: 沉積一銘原子層於該砍基板表面上以成為該成核層;以 及 通入一活性氮氣電漿及一銘源,藉以氮化所沉積之該銘 原子層下方之該矽基板層,反應形成該擴散阻障層。 14. 如申請專利範圍第12項所述之於矽基板上形成三族氮 16 200907124 化物半導體磊晶層的方法,其中該擴散阻障層至少包含 氮化矽。 15. 如申請專利範圍第12項所述之於矽基板上形成三族氮 化物半導體磊晶層的方法,其中該成核層至少包含氮化 鋁。 16. 如申請專利範圍第12項所述之於矽基板上形成三族氮 化物半導體磊晶層的方法,其中該金屬氮化層至少包含 氮化鋁。 17. 如申請專利範圍第12項所述之於矽基板上形成三族氮 化物半導體磊晶層的方法,其中該三族氮化物層至少包 含氮化錄。 18. 如申請專利範圍第12項所述之於矽基板上形成三族氮 化物半導體磊晶層的方法,其中該第一金屬氮化層約於 550°C至650°C間形成。 19. 如申請專利範圍第12項所述之於矽基板上形成三族氮 化物半導體磊晶層的方法,其中該第二金屬氮化物層與 該第三金屬氮化物層約於740°C至800°C間形成。 20. —種於矽基板上形成三族氮化物半導體磊晶層的方 法,至少包含: 提供一碎基板; 同時形成一擴散阻障層以及一成核層於該矽基板上,係 沉積一銘原子層於該石夕基板表面上以成為一成核層,通入 一活性氮氣電漿及一铭源,藉以氮化所沉積之該銘原子層 下方之該矽基板層,反應形成該擴散阻障層; 17 200907124 長成該成核層以形成一第一金屬氮化物層; 形成一三族IL化物層於該第一金屬氮化層表面上; 形成一第二金屬氮化物層於該第一三族氮化物層表面 上; 形成一第二三族氮化物層於該第二金屬氮化物層表面 上; 形成一第三金屬氮化物層於該第二三族氮化物層表面 上;以及 形成一第三三族氮化物層於該第三金屬氮化物層表面 上,以成為該二族乳化物半導體轰晶層。 21. 如申請專利範圍第20項所述之於矽基板上形成三族氮 化物半導體磊晶層的方法,其中該擴散阻障層至少包含 氮化矽。 22. 如申請專利範圍第20項所述之於矽基板上形成三族氮 化物半導體磊晶層的方法,其中該成核層至少包含氮化 鋁。 23. 如申請專利範圍第20項所述之於矽基板上形成三族氮 化物半導體蠢晶層的方法,其中該金屬氮化層至少包含 氮化鋁。 24. 如申請專利範圍第20項所述之於矽基板上形成三族氮 化物半導體磊晶層的方法,其中該三族氮化物層至少包 含氣化鎵。 25. 如申請專利範圍第20項所述之於矽基板上形成三族氮 化物半導體磊晶層的方法,其中該第一金屬氮化層約於 18 200907124 550°C至650°C間形成。 26.如申請專利範圍第20項所述之於矽基板上形成三族氮 ^ 化物半導體磊晶層的方法,其中該第二金屬氮化物層與 該第三金屬氮化物層約於740°C至800°C間形成。 19200907124 X. Patent application scope: 1. A method for forming a ruthenium substrate, comprising at least: a sagittal semiconductor epitaxial layer providing a fragmented substrate; and simultaneously forming a diffusion barrier layer to a county gentleman nucleation layer On the germanium substrate, the nucleation layer is grown to form a metal nitride, and a tri-family nitride layer is formed on the metal germanium, and the group III nitride semiconducting layer. The method of claim 2, wherein the method of claim 2, wherein the earth plate is nitrided and the nucleation layer is on the substrate L =, Forming the diffusion barrier layer to deposit an aluminum atom layer on the germanium substrate and the coating surface to form the nucleation layer; to pass an active nitrogen plasma and a substrate under the aluminum atomic layer Layer, the deposition of the heart of the Ming 3. The viscous barrier layer as in the scope of the patent application. A method of semiconductor linear crystal layer in which a group of murine mice is formed on the & The T-reading diffusion barrier layer contains at least nitrogen. 4. The method for applying the semiconductor stray layer of the first application of the patent scope is as follows; In the first embodiment, the nucleation layer comprises at least a method of nitriding a semiconductor crystal layer of the first aspect of the patent application, and a group III nitride aluminum nitride is formed on the composite substrate. The method of forming a group III nitride semiconductor epitaxial layer on a germanium substrate as described in claim 1, wherein the germanium metal nitride layer comprises at least a nitride layer gallium. 7. The method for forming a group III nitride semiconductor epitaxial layer on a germanium substrate, comprising: providing a chopped substrate; simultaneously forming a diffusion barrier layer and a nucleation layer on the germanium substrate, depositing a mark The atomic layer is formed on the surface of the substrate to form a nucleation layer, and an active nitrogen plasma and an aluminum source are introduced to nitride the deposited substrate layer under the aluminum atom layer to form the diffusion resistance. a barrier layer; forming the nucleation layer to form a metal nitride layer; and forming a group III nitride layer on the surface of the metal nitride layer to form the group II nitride semiconductor crystal layer. 8. The method of forming a group III nitride semiconductor epitaxial layer on a germanium substrate as described in claim 7, wherein the diffusion barrier layer comprises at least nitrogen oxide. 9. A method of forming a group III nitride semiconductor epitaxial layer on a germanium substrate as described in claim 7 wherein the nucleation layer comprises at least aluminum nitride. 10. A method of forming a tri-group nitride semiconductor epitaxial layer on a germanium substrate as described in claim 7 wherein the metal nitride layer comprises at least aluminum nitride. 11. A method of forming a tri-group nitride semiconductor epitaxial layer on a germanium substrate as described in claim 7 wherein the tri-family nitride layer comprises at least 15 200907124. 12. The method for forming a group III nitride semiconductor epitaxial layer on a germanium substrate, comprising: providing a broken substrate; simultaneously forming a diffusion barrier layer and a nucleation layer on the germanium substrate; a core layer to form a first metal nitride layer; forming a first group III nitride layer on the surface of the first metal II layer; forming a second metal nitride layer on the surface of the first group III nitride layer Forming a second group III nitride layer on the surface of the second metal nitride layer; forming a third metal nitride layer on the surface of the second group III nitride layer; and forming a third group III And forming a layer on the surface of the third metal nitride layer; to form the epitaxial layer of the group III nitride semiconductor. 13. The method of forming a group III nitride semiconductor epitaxial layer on a germanium substrate according to claim 12, wherein simultaneously forming the diffusion barrier layer and the nucleation layer on the germanium substrate comprises: Depositing an atomic layer on the surface of the chopped substrate to become the nucleation layer; and introducing an active nitrogen plasma and a source of etched, thereby nitriding the deposited ruthenium substrate layer under the dynasty atomic layer, and reacting to form The diffusion barrier layer. 14. A method of forming a trivalent nitrogen 16 200907124 compound semiconductor epitaxial layer on a germanium substrate as described in claim 12, wherein the diffusion barrier layer comprises at least tantalum nitride. 15. A method of forming a tri-group nitride semiconductor epitaxial layer on a germanium substrate as described in claim 12, wherein the nucleation layer comprises at least aluminum nitride. 16. A method of forming a tri-group nitride semiconductor epitaxial layer on a germanium substrate as described in claim 12, wherein the metal nitride layer comprises at least aluminum nitride. 17. A method of forming a tri-group nitride semiconductor epitaxial layer on a germanium substrate as described in claim 12, wherein the group III nitride layer comprises at least a nitride. 18. A method of forming a tri-group nitride semiconductor epitaxial layer on a germanium substrate as described in claim 12, wherein the first metal nitride layer is formed between about 550 ° C and 650 ° C. 19. The method of forming a group III nitride semiconductor epitaxial layer on a germanium substrate according to claim 12, wherein the second metal nitride layer and the third metal nitride layer are at about 740 ° C to Formed at 800 ° C. 20. A method for forming a group III nitride semiconductor epitaxial layer on a germanium substrate, comprising: providing a broken substrate; simultaneously forming a diffusion barrier layer and a nucleation layer on the germanium substrate The atomic layer is formed on the surface of the substrate to form a nucleation layer, and an active nitrogen plasma and a source are introduced to nitride the deposited substrate layer under the layer of the atomic layer to form the diffusion resistance. a barrier layer; 17 200907124 to form the nucleation layer to form a first metal nitride layer; forming a three-grouped IL layer on the surface of the first metal nitride layer; forming a second metal nitride layer Forming a second group III nitride layer on the surface of the second metal nitride layer; forming a third metal nitride layer on the surface of the second group III nitride layer; A third group III nitride layer is formed on the surface of the third metal nitride layer to form the matrix of the dimer emulsion semiconductor. 21. A method of forming a tri-group nitride semiconductor epitaxial layer on a germanium substrate as described in claim 20, wherein the diffusion barrier layer comprises at least tantalum nitride. 22. A method of forming a tri-group nitride semiconductor epitaxial layer on a germanium substrate as described in claim 20, wherein the nucleation layer comprises at least aluminum nitride. 23. A method of forming a stray layer of a Group III nitride semiconductor on a germanium substrate as described in claim 20, wherein the metal nitride layer comprises at least aluminum nitride. 24. A method of forming a tri-group nitride semiconductor epitaxial layer on a germanium substrate as described in claim 20, wherein the group III nitride layer comprises at least gallium hydride. 25. A method of forming a tri-group nitride semiconductor epitaxial layer on a germanium substrate as described in claim 20, wherein the first metal nitride layer is formed between about 550 ° C and 650 ° C of 18 200907124. 26. The method according to claim 20, wherein the third metal nitride layer and the third metal nitride layer are formed at about 740 ° C. Formed between 800 ° C. 19
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TWI452724B (en) * 2010-09-28 2014-09-11 Toyoda Gosei Kk Method of manufacturing group-3 nitride semiconductor light emitting element
US9099627B2 (en) 2010-09-28 2015-08-04 Toyoda Gosei Co., Ltd. Method for producing group III nitride semiconductor light-emitting device
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CN114664642A (en) * 2022-03-23 2022-06-24 江苏第三代半导体研究院有限公司 HEMT structure based on III-group nitride homoepitaxy, and preparation method and application thereof

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