JPH03126270A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH03126270A JPH03126270A JP1265481A JP26548189A JPH03126270A JP H03126270 A JPH03126270 A JP H03126270A JP 1265481 A JP1265481 A JP 1265481A JP 26548189 A JP26548189 A JP 26548189A JP H03126270 A JPH03126270 A JP H03126270A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- intermediate layer
- compound semiconductor
- silicon substrate
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 150000001875 compounds Chemical class 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 67
- 239000011247 coating layer Substances 0.000 claims description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 18
- 238000010438 heat treatment Methods 0.000 abstract description 9
- 239000013078 crystal Substances 0.000 abstract description 7
- 230000008646 thermal stress Effects 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 241000700560 Molluscum contagiosum virus Species 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- JOTBHEPHROWQDJ-UHFFFAOYSA-N methylgallium Chemical compound [Ga]C JOTBHEPHROWQDJ-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Landscapes
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、たとえば発光ダイオードアレイなどの半導体
装置およびその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device such as a light emitting diode array, and a method for manufacturing the same.
［従来の技術］
シリコン基板上に化合物半導体層を形成した発光ダイオ
ードが提案され、この構成は２段階成長法により作製さ
れる。すなわち比較的低温にてアモルファス状態の化合
物半導体層をシリコン基板上に形成した後、アニールし
、その後に通常の成長温度にて化合物半導体層を形成す
る技術である。[Prior Art] A light emitting diode in which a compound semiconductor layer is formed on a silicon substrate has been proposed, and this structure is manufactured by a two-step growth method. That is, this is a technique in which an amorphous compound semiconductor layer is formed on a silicon substrate at a relatively low temperature, annealed, and then a compound semiconductor layer is formed at a normal growth temperature.
このような化合物半導体層の膜厚が４μｍ以上になると
、シリコンと前記化合物半導体たとえばＧａＡｓとの熱
膨張係数の相違から、ＧａＡｓ中にクラックが生じると
いう問題点がある。なおシリコンとＧａＡｓの熱膨張係
数はそれぞれ２．５×１０−６および５．８Ｘ１０−’
である。When the thickness of such a compound semiconductor layer exceeds 4 μm, there is a problem that cracks occur in the GaAs due to the difference in coefficient of thermal expansion between silicon and the compound semiconductor, such as GaAs. The thermal expansion coefficients of silicon and GaAs are 2.5 x 10-6 and 5.8 x 10-', respectively.
It is.
このような問題点を解決するためにシリコン基板上にた
とえば５ｉ０２などの電気絶縁性材料から成る被覆層を
所定のパターンに形成し、発光ダイオードアレイを形成
するための所定の部位に透孔を形成し、該透孔内のシリ
コン基板上にＧａＡＳを選択的に成長させる方法が提案
されている。To solve these problems, a coating layer made of an electrically insulating material such as 5i02 is formed on a silicon substrate in a predetermined pattern, and through holes are formed in predetermined locations for forming a light emitting diode array. However, a method has been proposed in which GaAS is selectively grown on the silicon substrate within the through hole.
第５図は、このような方法を説明する断面図である。第
１段階は第５図（１）に示すように、表面処理を行った
シリコン基板１上に５ｉＯｚなどから成る電気絶縁性の
被覆層２を全面に形成する。FIG. 5 is a cross-sectional view illustrating such a method. In the first step, as shown in FIG. 5(1), an electrically insulating coating layer 2 made of 5iOz or the like is formed over the entire surface of a silicon substrate 1 that has undergone surface treatment.
第２段階では第５図（２）に示すように発光ダイオード
アレイの形状に対応して、透孔３を選択的に形成する。In the second step, as shown in FIG. 5(2), the through holes 3 are selectively formed in accordance with the shape of the light emitting diode array.
第３段階では第５図（３）に示すように、透孔３中のシ
リコン基板１上に、ＧａＡｓ膜４を選択的に成長させる
。ＧａＡｓ膜４に熱処理を施した後、Ｐ’Ｎ接合を有す
る半導体素子を形成して半導体アレイが構成される。In the third step, as shown in FIG. 5(3), a GaAs film 4 is selectively grown on the silicon substrate 1 in the through hole 3. After heat-treating the GaAs film 4, semiconductor elements having P'N junctions are formed to construct a semiconductor array.
［発明が解決しようとする課題］
上述した従来例によるＧａＡｓ膜４には、前記熱処理前
の状態では１０”ｃｍ−”程度の密度で貫通転位が存在
することが知られている。これに対して、前記熱処理を
施した場合、ＧａＡｓ膜４が昇温し、該膜４に熱応力が
発生し、これにより、前記貫通転位が減少する。しかし
ながら、シリコン基板１上にＧ ａ Ａ ｓ Ｍ４を被
覆層２を用いることなく全面に形成した場合、熱処理後
のＧａＡｓ膜が貫通転位密度を約３Ｘ１０＠ｃｍ−”程
度にまで減少できたのに対し、上記従来例の場合では貫
通転位密度が１０’ｃｍ−”程度にしか減少できないこ
とが確認された。このような現象は前記被覆層２が、熱
処理によってＧ ａ Ａ ｓ膜４に発生する熱応力を阻
害して貫通転位の削減を制限してしまうからであると考
えられる。[Problems to be Solved by the Invention] It is known that threading dislocations exist in the GaAs film 4 according to the conventional example described above at a density of about 10"cm-" before the heat treatment. On the other hand, when the heat treatment is performed, the temperature of the GaAs film 4 increases and thermal stress is generated in the film 4, thereby reducing the threading dislocations. However, when GaAs M4 was formed on the entire surface of the silicon substrate 1 without using the covering layer 2, the threading dislocation density of the GaAs film after heat treatment could be reduced to about 3X10@cm-''. On the other hand, in the case of the conventional example described above, it was confirmed that the threading dislocation density could be reduced only to about 10'cm-''. This phenomenon is considered to be because the coating layer 2 inhibits the thermal stress generated in the GaAs film 4 by heat treatment, thereby limiting the reduction of threading dislocations.
本発明の目的は上述の技術的課題を解消し、貫通転位が
減少されて品質が向上される半導体装置およびその製造
方法を提供することである。An object of the present invention is to solve the above-mentioned technical problems and provide a semiconductor device and a method for manufacturing the same in which threading dislocations are reduced and quality is improved.
［課題を解決するための手段］
本発明は、シリコン基板上に■−Ｖ族化合物半導体から
成る中間層を介して電気絶縁性被覆層を形成するととも
に、該被覆層が複数個の透孔を有し、さらに該透孔内に
■−Ｖ族化合物半導体層を形成せしめたことを特徴する
半導体装置である。[Means for Solving the Problems] The present invention forms an electrically insulating coating layer on a silicon substrate via an intermediate layer made of a ■-V group compound semiconductor, and the coating layer has a plurality of through holes. 1. A semiconductor device characterized in that the semiconductor device has the following structure and further includes a (1)-V group compound semiconductor layer formed in the through hole.
また本発明は、順次下記Ａ工程〜Ｄ工程によりシリコン
基板上に■−Ｖ族化合物半導体層を形成したことを特徴
とする半導体装置の製造方法である。The present invention also provides a method for manufacturing a semiconductor device, characterized in that a -V group compound semiconductor layer is sequentially formed on a silicon substrate by the following steps A to D.
Ａ：シリコン基板上に■−Ｖ族化合物半導体から成る中
間層を形成する。A: An intermediate layer made of a ■-V group compound semiconductor is formed on a silicon substrate.
Ｂ：上記中間層を熱処理する。B: The intermediate layer is heat treated.
Ｃ：上記中間層の上に複数個を透孔を有する電気絶縁性
被覆層を形成する。C: An electrically insulating coating layer having a plurality of through holes is formed on the intermediate layer.
Ｄ二上記透孔内の中間層上に■−Ｖ族化合物半導体層を
形成する。D2: A -V group compound semiconductor layer is formed on the intermediate layer in the above-mentioned through hole.
［作 用］
本発明に従う半導体装置を製造するには、まずシリコン
基板上に■−Ｖ族化合物半導体から成る中間層を形成す
る。中間層を熱処理し、次に中間層上に複数の透孔を有
する電気絶縁性の被覆層を形成する。各透孔内の中間層
上に、■−Ｖ族化合物半導体層を形成する。[Function] To manufacture the semiconductor device according to the present invention, first, an intermediate layer made of a -V group compound semiconductor is formed on a silicon substrate. The intermediate layer is heat treated, and then an electrically insulating covering layer having a plurality of through holes is formed on the intermediate layer. A -V group compound semiconductor layer is formed on the intermediate layer in each through hole.
ここで前記中間層を熱処理することにより、貫通転位密
度が従来例において説明したように、１０”ｃｍ−”程
度から３×１０６ｃｍ−”程度まで減少できる。一方、
このような中間層上に形成された被覆層の透孔内に形成
された■−Ｖ族化合物半導体層は、同一物質である中間
層上に形成されるため、貫通転位密度は中間層の有する
約３Ｘ１０’ｃｍ−”程度にすることができ、従来例と
比較して貫通転位密度を格段に低減することができ、品
質を向上できる。By heat-treating the intermediate layer, the threading dislocation density can be reduced from about 10 cm to about 3 x 10 cm, as explained in the conventional example. On the other hand,
Since the ■-V group compound semiconductor layer formed in the through hole of the covering layer formed on such an intermediate layer is formed on the intermediate layer of the same material, the threading dislocation density is equal to that of the intermediate layer. It is possible to reduce the threading dislocation density to approximately 3 x 10'cm-'', thereby significantly reducing the threading dislocation density and improving quality compared to the conventional example.
［実施例］
第１図は、本発明半導体装置の一実施例である発光ダイ
オードアレイ（以下、アレイと略称する）１１の断面図
である。第１図を参照して、アレイ１１について説明す
る。アレイ１１はシリコン基板１２上に全面に亘って形
成されるたとえばＧａＡｓなどの■−■族化合物半導体
から成る中間層１３を有する。前記中間層１３の層厚ｔ
は、たとえば１〜３μｍに選ばれる。この中間層１３上
には、製造されるアレイ１１の仕様に従って透孔１４を
有する被覆層１５がパターン形成される。[Embodiment] FIG. 1 is a sectional view of a light emitting diode array (hereinafter abbreviated as array) 11 which is an embodiment of the semiconductor device of the present invention. The array 11 will be explained with reference to FIG. The array 11 has an intermediate layer 13 formed over the entire surface of a silicon substrate 12 and made of a 1-2 group compound semiconductor such as GaAs. Layer thickness t of the intermediate layer 13
is selected, for example, from 1 to 3 μm. A covering layer 15 having through holes 14 is patterned on this intermediate layer 13 according to the specifications of the array 11 to be manufactured.
透孔１４内の中間層１３上にＰＮＮ接金形成するｎＪｉ
ｌ１６およびｐ Ｍ １７がそれぞれ形成される。nJi formed by PNN welding on the intermediate layer 13 in the through hole 14
l16 and pM17 are formed, respectively.
前記０層１６はたとえばｎ−Ａｌｗ Ｇａ＋ −ｘ Ａ
Ｓから成り、９層１７はｐ−Ａ、１ ｘ Ｇａ、 −Ａ
ｓ （０＜ｘ＜１）から成る。ｐ屑１７上にはｐ−Ｇａ
Ａｓから成る接続層１８が形成される。接続１１８の上
面を除く残余の領域に、前記Ｓ ｉ ０２などから成る
被覆層１９が全面に形成される。この被覆層１９上に接
続層１８と電気的に接続される電８ｉ！２０が形成され
る。The 0 layer 16 is, for example, n-Alw Ga+ -x A
S, 9 layers 17 are p-A, 1 x Ga, -A
s (0<x<1). p-Ga on p-waste 17
A connection layer 18 made of As is formed. A covering layer 19 made of the above-mentioned S i 02 or the like is formed entirely on the remaining area except for the upper surface of the connection 118 . An electric wire 8i! electrically connected to the connection layer 18 on this covering layer 19! 20 is formed.
第２図は第１図示のアレイ１１を製造するに用いられる
有機金属を用いて化学的気相成長を行う製造装置（以下
、ＭＯＣＶＤ装置と略す）２１の構成を示す系統図であ
る。第２図を参照して、ＭＯＣＶＤ装置ｆ２装置及２１
２２内にはサセプタ２３が配置され、その上にシリコン
基板１２が乗載される８反応管２２には高周波コイル２
４が巻回されており、図示しない高周波電源から高周波
電力が供給されて、サセプタ２３が誘導加熱される。FIG. 2 is a system diagram showing the configuration of a manufacturing apparatus (hereinafter abbreviated as MOCVD apparatus) 21 that performs chemical vapor phase growth using an organic metal and is used to manufacture the array 11 shown in FIG. Referring to FIG. 2, MOCVD equipment f2 equipment and 21
A susceptor 23 is disposed inside the susceptor 22, and a high frequency coil 2 is installed in the 8 reaction tube 22 on which the silicon substrate 12 is mounted.
4 is wound around the susceptor 23, and high frequency power is supplied from a high frequency power source (not shown) to heat the susceptor 23 by induction.
上記反応管２２に連通される管路２５には、たとえば水
素ガスなどのキャリアガスが供給され、また流量調整弁
２６．２７．２８を介してＴＭＡ（トリメチルアルミニ
ウム）発生装置２９、ＴＭＧ（）リメチルガリウム）発
生装置３０およびＡｓＨ＝発生装置３１がそれぞれ接続
される。A carrier gas such as hydrogen gas is supplied to a pipe line 25 communicating with the reaction tube 22, and a TMA (trimethylaluminum) generator 29 and a TMG () Methyl gallium) generator 30 and AsH= generator 31 are connected, respectively.
第３図はＭＯＣＶＤ装置２１を用いてアレイ１１を製造
する際の製造工程を示す流れ図であり、第４図はこの製
造工程を示す断面図ある。これらの図面を併せて参照し
て、アレイ１１の製造工程について説明する。第３図ス
テップａ１では、シリコン基板１２上にＧａＡｓ１ｌを
全面に亘って成長させる。この段階は第２図のＭＯＣＶ
Ｄ装置２１を用いて行われる。FIG. 3 is a flowchart showing the manufacturing process for manufacturing the array 11 using the MOCVD apparatus 21, and FIG. 4 is a cross-sectional view showing this manufacturing process. The manufacturing process of the array 11 will be described with reference to these drawings. In step a1 of FIG. 3, GaAs 11 is grown over the entire surface of the silicon substrate 12. As shown in FIG. This stage is the MOCV shown in Figure 2.
This is carried out using the D device 21.
すなわち反応管２２内のサセプタ２３上にシリコン基板
１２を乗載し、所定のサーマルクリーニングを施した後
、ＴＭＧとＡｓＨ，とを反応管２２内に所定流量ずつ導
入して、アモルファス状態のＧａＡｓ層を膜厚１〜３μ
ｍ、好適には１．２〜２μｍ、！＆適には１．３〜１．
７μｍの範囲内に成長させる。この状態のＧ ａ Ａ
ｓ層には１０’ｃｔｒｌ”程度の密度で貫通転位が存在
する。ステップａ２で゛はこのアモルファス状態のＧａ
Ａｓ層に熱処理を加え、ＧａＡｓ層に熱応力を発生させ
て貫通転位密度を１０’ｃｍ−”程度にまで減少させ、
第４図（１）に示すように中間層１３を形成する。That is, the silicon substrate 12 is mounted on the susceptor 23 in the reaction tube 22, and after performing a prescribed thermal cleaning, TMG and AsH are introduced into the reaction tube 22 at a prescribed flow rate to form an amorphous GaAs layer. Film thickness 1~3μ
m, preferably 1.2 to 2 μm,! & Suitably 1.3 to 1.
It is grown within a range of 7 μm. G a A in this state
Threading dislocations exist in the s layer at a density of about 10'ctrl''. In step a2,
Heat treatment is applied to the As layer to generate thermal stress in the GaAs layer, reducing the threading dislocation density to about 10'cm-''.
The intermediate layer 13 is formed as shown in FIG. 4(1).
上記熱処理には１回だけ加熱する場合、もしくは複数回
の加熱を行うヒートサイクルの場合がある。前者の場合
であれば、１０００℃以下、好適には７００〜９５０℃
の温度範囲内で加熱すればよい、 ｆ＆者の場合であれ
ば、８５０℃以下の加熱温度で、たとえば２５℃との間
で複数回（一般には２〜５回のヒートサイクル数である
）繰り退し加熱すればよい。The above-mentioned heat treatment may include heating only once or a heat cycle in which heating is performed multiple times. In the former case, the temperature is 1000°C or less, preferably 700 to 950°C.
In the case of f&, it is sufficient to heat within the temperature range of Just let it cool and heat it up.
ステップａ３では、中間層１３上に第４図（２）に示す
被覆層１５を全面に亘って形成し、ステップａ４では、
たとえばエツチング技術などにより第４図（３）に示す
ように被覆層１５をパターン化し、透孔１４を形成する
。ステップａ５では、上記透孔１４内で中間層１３上に
ＧａＡｓから成る結晶層３２を第４図（４）に示すよう
に選択的に成長させる。In step a3, a coating layer 15 shown in FIG. 4(2) is formed over the entire surface of the intermediate layer 13, and in step a4,
For example, the coating layer 15 is patterned using an etching technique as shown in FIG. 4(3) to form through holes 14. In step a5, a crystal layer 32 made of GaAs is selectively grown on the intermediate layer 13 within the through hole 14 as shown in FIG. 4(4).
ステップａ６では、上記結晶層３２を用いてＡ１ ＊
Ｇ ａ ｌ−Ａ ｓから成るＰＮ接合を形成する。In step a6, using the crystal layer 32, A1*
A PN junction consisting of Gal-As is formed.
すなわち第１図の０層１６および９層１７を形成する。That is, the 0 layer 16 and the 9 layer 17 shown in FIG. 1 are formed.
ステップａ７では被覆層１９を形成し、ステップａ８で
は電極２０を形成する。このようにしてアレイ１１が形
成される。In step a7, the covering layer 19 is formed, and in step a8, the electrode 20 is formed. In this way, array 11 is formed.
このようにして形成されたアレイ１１において、結晶層
３２は、貫通転位密度が３Ｘ１０’ ｃｍ２程度まで低
減された中間ＰＭ １３ ａ上に成長するため、貫通転
位密度が１０’ ｃｍ−”のオーダー程度まで低減され
ていることが本件発明者によって確認された。これによ
り製造されるアレイ１１の品質を格段に向上することが
できる。In the array 11 formed in this manner, the crystal layer 32 grows on the intermediate PM 13 a whose threading dislocation density is reduced to about 3×10′ cm2, so that the threading dislocation density is on the order of 10′ cm−”. The inventor of the present invention has confirmed that this has been reduced to 50%.As a result, the quality of the manufactured array 11 can be significantly improved.
［発明の効果］
以上のように本発明に従えば、中間層を熱処理すること
により、貫通転位密度が従来例において説明したように
、１０’ｃｍ〜２程度から３×１０’ ｃｍ−２程度ま
で減少できる。このような中間層上に形成された被覆層
の透孔内に形°成された■−Ｖ族化合物半導体層は、同
一物質である中間層上に形成されるため、貫通転位密度
は中間層の有する約３Ｘ１０’ ｃｒｎ−’程度にする
ことができ、従来例と比較して貫通転位密度を格段に低
減することができ、品質を向上できる。[Effects of the Invention] As described above, according to the present invention, by heat-treating the intermediate layer, the threading dislocation density can be reduced from about 10' cm to about 3 x 10' cm-2, as explained in the conventional example. can be reduced to Since the ■-V group compound semiconductor layer formed in the through hole of the covering layer formed on such an intermediate layer is formed on the intermediate layer of the same material, the threading dislocation density is lower than that of the intermediate layer. It is possible to reduce the threading dislocation density to approximately 3×10'crn-' as compared with the conventional example, and to improve quality.
第１図は本発明のアレイ１１の断面図、第２図はアレイ
１１を製造する際に用いられるＭＯＣＶＤ装置２１の系
統図、第３図は本実施例の製造工程を説明する流れ図、
第４図は製造工程を説明する断面図、第５図は従来例の
製造工程を説明する断面図である。
１１・・・アレイ、１２・・・シリコン基板、１３・・
・中間層、１４・・・透孔、１５・・・被覆層、２１・
・・ＭＯＣＶＤ装置、３２・・・結晶層FIG. 1 is a cross-sectional view of the array 11 of the present invention, FIG. 2 is a system diagram of the MOCVD apparatus 21 used in manufacturing the array 11, and FIG. 3 is a flowchart explaining the manufacturing process of this embodiment.
FIG. 4 is a sectional view illustrating the manufacturing process, and FIG. 5 is a sectional view illustrating the manufacturing process of a conventional example. 11...Array, 12...Silicon substrate, 13...
・Intermediate layer, 14... Through hole, 15... Covering layer, 21.
・・MOCVD apparatus, 32 ・・Crystal layer
Claims (2)
る中間層を介して電気絶縁性被覆層を形成するとともに
、該被覆層が複数個の透孔を有し、さらに該透孔内にI
II−Ｖ族化合物半導体層を形成せしめたことを特徴する
半導体装置。(1) An electrically insulating coating layer is formed on a silicon substrate via an intermediate layer made of a III-V compound semiconductor, and the coating layer has a plurality of through holes, and furthermore, an I
A semiconductor device characterized in that a II-V group compound semiconductor layer is formed.
III−Ｖ族化合物半導体層を形成したことを特徴とする
半導体装置の製造方法。 Ａ：シリコン基板上にIII−Ｖ族化合物半導体から成る
中間層を形成する。 Ｂ：上記中間層を熱処理する。 Ｃ：上記中間層の上に複数個を透孔を有する電気絶縁性
被覆層を形成する。 Ｄ：上記透孔内の中間層上にIII−Ｖ族化合物半導体層
を形成する。(2) On the silicon substrate by sequentially following steps A to D.
A method for manufacturing a semiconductor device, characterized in that a III-V group compound semiconductor layer is formed. A: An intermediate layer made of a III-V compound semiconductor is formed on a silicon substrate. B: The intermediate layer is heat treated. C: An electrically insulating coating layer having a plurality of through holes is formed on the intermediate layer. D: A III-V compound semiconductor layer is formed on the intermediate layer in the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26548189A JP2848866B2 (en) | 1989-10-11 | 1989-10-11 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26548189A JP2848866B2 (en) | 1989-10-11 | 1989-10-11 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03126270A true JPH03126270A (en) | 1991-05-29 |
| JP2848866B2 JP2848866B2 (en) | 1999-01-20 |
Family
ID=17417776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26548189A Expired - Fee Related JP2848866B2 (en) | 1989-10-11 | 1989-10-11 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2848866B2 (en) |
-
1989
- 1989-10-11 JP JP26548189A patent/JP2848866B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2848866B2 (en) | 1999-01-20 |
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