TWI387999B - Compound semiconductor epitaxial wafer and method of manufacturing the same - Google Patents
Compound semiconductor epitaxial wafer and method of manufacturing the same Download PDFInfo
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本發明係關於一種化合物半導體及其製造方法,特別是關於一種成長於一金屬基板上之化合物半導體磊晶片及其製造方法。The present invention relates to a compound semiconductor and a method of fabricating the same, and more particularly to a compound semiconductor epitaxial wafer grown on a metal substrate and a method of fabricating the same.
隨著光電及通訊產業急速發展,化合物半導體如砷化鎵(GaAs)等III-V族化合物憑藉其直接能隙(direct band-gap)、高載子遷移率(carrier mobility)、以及藉由調整III-V族化合物的化學組成可得到不同能隙的材料...等優越特性已成為製作光電及通訊元件的主要基材。With the rapid development of the optoelectronics and communication industries, compound semiconductors such as gallium arsenide (GaAs) and other III-V compounds rely on their direct band-gap, carrier mobility, and by adjustment. The superior chemical properties of III-V compounds, such as materials with different energy gaps, have become the main substrates for the fabrication of optoelectronic and communication components.
III-V族化合物半導體之光電及通訊元件的製作主要是以砷化鎵(GaAs)、磷化鎵(GaP)及磷化銦(InP)等III-V族化合物為基板(substrate),在晶格(lattice)匹配的狀況下進行磊晶成長。目前,III-V族化合物半導體基板的直徑多為四英吋以下的砷化鎵(GaAs)或鍺(Ge)材料基板,或使用單晶矽基板(Si)。The fabrication of optoelectronic and communication components of III-V compound semiconductors is mainly based on III-V compounds such as gallium arsenide (GaAs), gallium phosphide (GaP) and indium phosphide (InP). Epitaxial growth is performed under the condition of lattice matching. At present, a III-V compound semiconductor substrate has a diameter of four or more gallium arsenide (GaAs) or germanium (Ge) material substrates, or a single crystal germanium substrate (Si).
然而,由於緩衝層與III-V族化合物半導體材料之間存在晶格不匹配及熱膨脹係數(thermal expansion coefficient)不同等問題,例如,矽緩衝層與砷化鎵材料的晶格常數在25℃時相差約為4.1%,再者,矽緩衝層與砷化鎵材料的熱膨脹係數在25℃時相差約為62%。因此,將III-V化合物半導體材料磊晶於緩衝層上,會因為晶格不匹配及熱膨脹係數不同等問題,在化合物半導體磊晶層內形成貫穿式差排(threading dlslocation),從而造成結晶品質不佳。However, due to problems such as lattice mismatch and difference in thermal expansion coefficient between the buffer layer and the III-V compound semiconductor material, for example, the lattice constant of the buffer layer and the gallium arsenide material is 25 ° C. The difference is about 4.1%. Furthermore, the thermal expansion coefficient of the buffer layer and the gallium arsenide material differs by about 62% at 25 °C. Therefore, when the III-V compound semiconductor material is epitaxially deposited on the buffer layer, threading dlslocation is formed in the epitaxial layer of the compound semiconductor due to problems such as lattice mismatch and different thermal expansion coefficients, thereby causing crystal quality. Not good.
第一圖為第一習知技術於矽基板上成長化合物半導體磊晶之剖面示意圖。如第一圖所示,一化合物半導體磊晶片20包含:一矽基板21、一砷化鎵第一緩衝層22、一砷化鎵第一磊晶層23、一砷化鎵第二緩衝層24、一砷化鎵第二磊晶層25。該化合物半導體磊晶片20之製備方法係採用有機金屬化學氣相沉積(metal-organic chemical vapor deposition)法,首先對該矽基板21進行一沉積製程,其中該沉積製程之溫度約為450℃,沉積後形成該砷化鎵第一緩衝層22的厚度為5至20μm。接著進行該砷化鎵第一磊晶層的磊晶製程,其中磊晶製程之溫度為650℃,磊晶後形成該砷化鎵第一磊晶層23的厚度為1μm。接著再進行一沉積製程,其中該沉積製程之溫度亦約為450℃,沉積後形成該砷化鎵第二緩衝層24的厚度為5至20nm。接續再進行該砷化鎵第二磊晶層的磊晶製程,其中磊晶製程之溫度亦約為650℃,磊晶後形成該砷化嫁第二磊晶層25的厚度約為2μm。The first figure is a schematic cross-sectional view of a compound semiconductor epitaxial growth on a germanium substrate by a first conventional technique. As shown in the first figure, a compound semiconductor epitaxial wafer 20 includes: a germanium substrate 21, a gallium arsenide first buffer layer 22, a gallium arsenide first epitaxial layer 23, and a gallium arsenide second buffer layer 24. a gallium arsenide second epitaxial layer 25. The compound semiconductor epitaxial wafer 20 is prepared by a metal-organic chemical vapor deposition method, first performing a deposition process on the germanium substrate 21, wherein the deposition process has a temperature of about 450 ° C, and deposition. The gallium arsenide first buffer layer 22 is formed to have a thickness of 5 to 20 μm. Then, an epitaxial process of the first epitaxial layer of the gallium arsenide is performed, wherein the temperature of the epitaxial process is 650 ° C, and the thickness of the first epitaxial layer 23 of the gallium arsenide is 1 μm after epitaxy. Then, a deposition process is performed, wherein the temperature of the deposition process is also about 450 ° C, and the second buffer layer 24 of the gallium arsenide is formed to have a thickness of 5 to 20 nm after deposition. The epitaxial process of the second epitaxial layer of gallium arsenide is further performed, wherein the temperature of the epitaxial process is also about 650 ° C, and the thickness of the second arsenide layer 25 after epitaxial formation is about 2 μm.
前述第一習知技術係利用二層砷化鎵緩衝層(22、24)及二層砷化鎵磊晶層(23,25)來改善砷化鎵在矽基板21上磊晶的品質。但此一製程仍需再加入一溫度循環退火(thermal cycle annealing)的熱處理程序才可進一步有效改善砷化鎵磊晶層的品質。The first prior art technique utilizes a two-layer gallium arsenide buffer layer (22, 24) and a two-layer gallium arsenide epitaxial layer (23, 25) to improve the quality of epitaxial gallium arsenide on the germanium substrate 21. However, this process still needs to add a thermal cycle annealing heat treatment procedure to further improve the quality of the gallium arsenide epitaxial layer.
第二圖為第二習知技術之化合物半導體磊晶片剖面示意圖。如第二圖所示,一化合物半導體磊晶片30包含:一矽基板31、一砷化鎵第一緩衝層32、一砷化鎵第一磊晶層33、一砷化銦鎵第二緩衝層34、一砷化鎵第二磊晶層35。該化合物半導體磊晶片30之製備方法亦係採用有機金屬化學氣相沉積法,首先對該矽基板31進行一沉積製程,其中沉積製程之溫度為430℃,沉積後形成該砷化鎵第一緩衝層32的厚度為50nm。接著進行該砷化鎵第一磊晶層33的磊晶製程,其中磊晶製程之溫度為620℃,磊晶後形成該砷化鎵第一磊晶層33的厚度為2μm。此時,緊接著進行溫度循環退火熱處理程序,首先將有機金屬化學氣相沉積系統內的磊晶片溫度降至300℃,到達此一溫度後,再加熱磊晶片至750℃,並在750℃維特5分鐘,然後再降低溫度至300℃,如此係一個溫度循環。當經過一個或四個溫度循環退火熱處理後接著再進行一沉積製程,其中該沉積製程之溫度為620℃,沉積後形成該砷化銦鎵第二緩衝層34的厚度為200nm。接著再進行該砷化鎵第二磊晶層35的磊晶製程,其中磊晶製程之溫度亦為620℃,磊晶後形成該砷化鎵第二磊晶層35的厚度為1.8μm。The second figure is a schematic cross-sectional view of a compound semiconductor epitaxial wafer of the second prior art. As shown in the second figure, a compound semiconductor epitaxial wafer 30 includes: a germanium substrate 31, a gallium arsenide first buffer layer 32, a gallium arsenide first epitaxial layer 33, and an indium gallium arsenide second buffer layer. 34. A gallium arsenide second epitaxial layer 35. The preparation method of the compound semiconductor epitaxial wafer 30 is also performed by an organometallic chemical vapor deposition method. First, a deposition process is performed on the germanium substrate 31, wherein the deposition process temperature is 430 ° C, and the first buffer of the gallium arsenide is formed after deposition. Layer 32 has a thickness of 50 nm. Then, the epitaxial process of the first epitaxial layer 33 of the gallium arsenide is performed, wherein the temperature of the epitaxial process is 620 ° C, and the thickness of the first epitaxial layer 33 of the gallium arsenide is 2 μm after epitaxy. At this point, the temperature cycle annealing heat treatment procedure is followed by first reducing the temperature of the epitaxial wafer in the organometallic chemical vapor deposition system to 300 ° C. After reaching this temperature, the epitaxial wafer is heated to 750 ° C, and at 750 ° C. 5 minutes, then lower the temperature to 300 ° C, so a temperature cycle. After one or four temperature cycle annealing heat treatments, a deposition process is further performed, wherein the deposition process has a temperature of 620 ° C, and the second indium gallium arsenide buffer layer 34 is formed to have a thickness of 200 nm after deposition. Then, the epitaxial process of the second epitaxial layer 35 of the gallium arsenide is performed, wherein the temperature of the epitaxial process is also 620 ° C, and the thickness of the second epitaxial layer 35 of the gallium arsenide is 1.8 μm after epitaxy.
此第二習知技術係利用一層砷化鎵第一緩衝層32及一層砷化鎵第一磊晶層33,經過溫度循環退火熱處理來降低貫穿式差排產生的機會,進而成長該砷化銦鎵第二緩衝層34、該砷化錄第二磊晶層35,以改善砷化鎵在該矽基板31上的磊晶品質。依據第二習知技術的結果顯示,在經過一次溫度循環退火熱處理狀況下,該砷化鎵第一磊晶層33的雙晶X射線搖擺曲線(double crystal X-ray rocking curve)量測呈現半高波寬(Full Width at Half Maximum,FWHM)值為280arcsec。然而,在經過四次溫度循環退火熱處理狀況下,該砷化鎵第一磊晶層33的雙晶X-射線搖擺曲線量測呈現半高波寬值降為140arcsec。此一現象表示溫度循環退火熱處理對於砷化鎵在矽基板的磊晶品質有顯著的效用。The second conventional technique utilizes a layer of gallium arsenide first buffer layer 32 and a layer of gallium arsenide first epitaxial layer 33, and undergoes temperature cycle annealing heat treatment to reduce the chance of penetrating discontinuity, thereby growing the indium arsenide. The gallium second buffer layer 34 and the arsenic recording second epitaxial layer 35 are used to improve the epitaxial quality of gallium arsenide on the germanium substrate 31. According to the results of the second conventional technique, the double crystal X-ray rocking curve of the gallium arsenide first epitaxial layer 33 is measured half by one temperature cycle annealing heat treatment. The Full Width at Half Maximum (FWHM) value is 280 arcsec. However, under the condition of four temperature cycle annealing heat treatments, the twin-crystal X-ray rocking curve measurement of the gallium arsenide first epitaxial layer 33 exhibits a half-height wave width drop of 140 arcsec. This phenomenon indicates that the temperature cycle annealing heat treatment has a significant effect on the epitaxial quality of gallium arsenide on the germanium substrate.
第三圖為第三習知技術之化合物半導體磊晶片剖面示意圖。如第三圖所示,一化合物半導體磊晶片40包含:一矽基板41、一砷化鎵第一緩衝層42、一砷化鎵第一磊晶層43、一砷化鎵第二磊晶層44。該化合物半導體磊晶片40之製備方法亦係採用有機金屬化學氣相沉積法,首先對該矽基板41進行一沉積製程,其中沉積製程之溫度為400℃,沉積後形成該砷化鎵第一緩衝層42的厚度小於200nm。接著進行該砷化鎵第一磊晶層43的磊晶製程,其中磊晶製程之溫度為700℃,磊晶後形成該砷化鎵第一磊晶層43的厚度為1μm。此時,緊接著進行溫度循環退火熱處理程序,首先將有機金屬化學氣相沉積系統內的磊晶片溫度降至室溫,到達此一溫度後,再加熱磊晶至850℃,並在850℃維持5分鐘,然後再降低溫度至700℃。接著,進行該砷化鎵第二磊晶層44的磊晶成長,如此係一個溫度循環磊晶程序,當經過三個至十三個溫度循環磊晶程序後,同時完成熱處理及該砷化鎵第二磊晶層44的磊晶成長製程,形成該砷化鎵第二磊晶層44的厚度為3~4μm。The third figure is a schematic cross-sectional view of a compound semiconductor epitaxial wafer of the third prior art. As shown in the third figure, a compound semiconductor epitaxial wafer 40 includes: a germanium substrate 41, a gallium arsenide first buffer layer 42, a gallium arsenide first epitaxial layer 43, and a gallium arsenide second epitaxial layer. 44. The preparation method of the compound semiconductor epitaxial wafer 40 is also performed by an organometallic chemical vapor deposition method. First, a deposition process is performed on the germanium substrate 41, wherein the deposition process temperature is 400 ° C, and the first buffer of the gallium arsenide is formed after deposition. Layer 42 has a thickness of less than 200 nm. Then, the epitaxial process of the first epitaxial layer 43 of the gallium arsenide is performed, wherein the temperature of the epitaxial process is 700 ° C, and the thickness of the first epitaxial layer 43 of the gallium arsenide is 1 μm after epitaxy. At this point, the temperature cycle annealing heat treatment procedure is followed by first reducing the temperature of the epitaxial wafer in the organometallic chemical vapor deposition system to room temperature. After reaching this temperature, the epitaxial crystal is heated to 850 ° C and maintained at 850 ° C. 5 minutes, then lower the temperature to 700 °C. Then, the epitaxial growth of the second epitaxial layer 44 of the gallium arsenide is performed, such that a temperature cycle epitaxial process is performed, and after three to thirteen temperature cycle epitaxy processes, the heat treatment and the gallium arsenide are simultaneously completed. The epitaxial growth process of the second epitaxial layer 44 forms a thickness of the GaN gallium second epitaxial layer 44 of 3 to 4 μm.
此第三習知技術係利用一層砷化鎵第一緩衝層42、一層砷化鎵第一磊晶層43及同時進行溫度循環退火熱處理與磊晶製程的方式來降低貫穿式差排的產生,進而得到該砷化鎵第二磊晶層44,以改善砷化鎵在矽基板41上的磊晶品質。依據Itoh等人的實驗結果顯示,在經過三個至十三個溫度循環磊晶程序後,該砷化鎵第二磊晶層44的雙晶X-射線搖擺曲線量測呈現半高波寬值為130arcsec。因此,第三習知技術所採用的方法雖然可改進砷化鎵的磊晶品質,但是由雙晶X-射線搖擺曲線量測結果來看,該砷化鎵第二磊晶層44的品質仍是相當低落。The third conventional technique utilizes a layer of gallium arsenide first buffer layer 42, a layer of gallium arsenide first epitaxial layer 43 and simultaneous temperature cycle annealing heat treatment and epitaxial process to reduce the generation of through-type difference rows. The gallium arsenide second epitaxial layer 44 is further obtained to improve the epitaxial quality of gallium arsenide on the germanium substrate 41. According to the experimental results of Itoh et al., after three to thirteen temperature cycling epitaxial processes, the twin-crystal X-ray rocking curve of the second epitaxial layer 44 of gallium arsenide exhibits a half-height width value. 130arcsec. Therefore, although the method adopted by the third conventional technique can improve the epitaxial quality of gallium arsenide, the quality of the second epitaxial layer 44 of the gallium arsenide is still determined by the measurement result of the twin-crystal X-ray rocking curve. It is quite low.
因此,在化合物半導體磊晶片中,製程步驟、磊晶結構以及溫度循環退火熱處理程序皆攸關著磊晶片的晶體品質。Therefore, in the compound semiconductor epitaxial wafer, the process steps, the epitaxial structure, and the temperature cycle annealing heat treatment process all have the crystal quality of the epitaxial wafer.
本發明之目的在於提供一種具有良好晶體品質及特性之化合物半導體磊晶片及其製造方法,利用金屬基板的基材改良,與磊晶結構及溫度循環退火熱處理程序之製程步驟改進,來達到晶體品質增進、製程簡化與成本降低的優點。The object of the present invention is to provide a compound semiconductor epitaxial wafer with good crystal quality and characteristics and a manufacturing method thereof, which are improved by using a substrate of a metal substrate, and a process step of an epitaxial structure and a temperature cycle annealing heat treatment process to achieve crystal quality. Advantages of enhancement, process simplification and cost reduction.
為達上述目的,本發明之化合物半導體磊晶片之製造方法包含以下步驟:於一金屬基板上沉積一層矽薄膜以形成一矽第一緩衝層;於該矽第一緩衝層上沉積一層化合物半導體薄膜以形成一化合物半導體第二緩衝層;於該化合物半導體第二緩衝層上沉積一層化合物半導體薄膜以形成一化合物半導體第三緩衝層;於該化合物半導體第三緩衝層上磊晶一層化合物半導體薄膜以形成一化合物半導體第一磊晶層;施以一第一次熱處理程序;於該化合物半導體第一磊晶層上磊晶一層化合物半導體薄膜以形成一化合物半導體第二磊晶層;及施以一第二次熱處理程序以完成一化合物半導體磊晶片。To achieve the above object, a method for fabricating a compound semiconductor epitaxial wafer of the present invention comprises the steps of: depositing a tantalum film on a metal substrate to form a first buffer layer; depositing a compound semiconductor film on the first buffer layer of the tantalum Forming a second buffer layer of a compound semiconductor; depositing a compound semiconductor film on the second buffer layer of the compound semiconductor to form a third buffer layer of the compound semiconductor; and epitaxially depositing a compound semiconductor film on the third buffer layer of the compound semiconductor to Forming a first epitaxial layer of a compound semiconductor; applying a first heat treatment process; epitaxially depositing a compound semiconductor film on the first epitaxial layer of the compound semiconductor to form a second epitaxial layer of the compound semiconductor; A second heat treatment procedure is performed to complete a compound semiconductor epitaxial wafer.
為達上述目的,本發明之化合物半導體磊晶片包含:一金屬基板;一矽第一緩衝層,係設置於該金屬基板上;一化合物半導體第二緩衝層,係設置於該矽第一緩衝層上;一化合物半導體第三緩衝層,係設置於該化合物半導體第二緩衝層上,該化合物半導體第三緩衝層並經過一第一次熱處理程序;一化合物半導體第一磊晶層,係設置於該化合物半導體第三緩衝層上;及一化合物半導體第二磊晶層,係設置於該化合物半導體第一磊晶層上,該化合物半導體第二磊晶層並經過一第二次熱處理程序。In order to achieve the above object, the compound semiconductor epitaxial wafer of the present invention comprises: a metal substrate; a first buffer layer disposed on the metal substrate; and a second buffer layer of the compound semiconductor disposed on the first buffer layer of the germanium a third buffer layer of the compound semiconductor is disposed on the second buffer layer of the compound semiconductor, and the third buffer layer of the compound semiconductor is subjected to a first heat treatment process; a first epitaxial layer of the compound semiconductor is disposed on The compound semiconductor is provided on the third buffer layer; and a compound semiconductor second epitaxial layer is disposed on the first epitaxial layer of the compound semiconductor, and the second epitaxial layer of the compound semiconductor is subjected to a second heat treatment process.
於本發明之實施例中,該化合物半導體第二緩衝層、該化合物半導體第三緩衝層、該化合物半導體第一磊晶層及該化合物半導體第二磊晶層之材料可為砷化鎵、砷化鋁、磷化鎵、砷化銦、磷化銦等III-V族化合物半導體二元材料或由其組成之三元或四元材料。In an embodiment of the present invention, the compound semiconductor second buffer layer, the compound semiconductor third buffer layer, the compound semiconductor first epitaxial layer, and the compound semiconductor second epitaxial layer may be made of gallium arsenide or arsenic. A III-V compound semiconductor binary material such as aluminum, gallium phosphide, indium arsenide or indium phosphide or a ternary or quaternary material composed thereof.
於本發明之實施例中,沉積的製程可為一有機金屬化學氣相沉積製程,磊晶的製程可為一分子束磊晶製程。該矽第一緩衝層的沉積製程係在溫度約為580~600℃下進行,沉積厚度約為15~25。該化合物半導體第二緩衝層的沉積製程係在溫度約為380~400℃下進行,沉積厚度約為10至20μm。該化合物半導體第三緩衝層的沉積製程係在溫度約為400~450℃下進行,沉積厚度約為50~200。該化合物半導體第一磊晶層的磊晶製程係在溫度約為650℃下進行,磊晶厚度約為1.5~2μm。該化合物半導體第二磊晶層的磊晶製程係在溫度約為710℃下進行,磊晶厚度約為1.5~2μm。In the embodiment of the present invention, the deposition process may be an organometallic chemical vapor deposition process, and the epitaxial process may be a molecular beam epitaxy process. The deposition process of the first buffer layer of the crucible is performed at a temperature of about 580 to 600 ° C, and the deposition thickness is about 15 to 25 . The deposition process of the second buffer layer of the compound semiconductor is performed at a temperature of about 380 to 400 ° C and a deposition thickness of about 10 to 20 μm. The deposition process of the third buffer layer of the compound semiconductor is performed at a temperature of about 400 to 450 ° C, and the deposition thickness is about 50 to 200. . The epitaxial process of the first epitaxial layer of the compound semiconductor is performed at a temperature of about 650 ° C, and the epitaxial thickness is about 1.5 to 2 μm. The epitaxial process of the second epitaxial layer of the compound semiconductor is performed at a temperature of about 710 ° C, and the epitaxial thickness is about 1.5 to 2 μm.
於本發明之實施例中,該第一次熱處理程序與該第二次熱處理程序皆為一高低溫循環退火熱處理程序,該高低溫循環退火熱處理程序係經過4~8次的高低溫循環。In the embodiment of the present invention, the first heat treatment process and the second heat treatment process are both a high and low temperature cycle annealing heat treatment process, and the high and low temperature cycle annealing heat treatment process is subjected to high and low temperature cycles of 4 to 8 times.
藉此,本發明使用金屬基板而使基板尺寸的應用上更具彈性且具有低成本、高散熱及可彎曲性的優點以及III-V族化合物半導體高載子遷移率的特性,並可廣泛應用於大型建築帷幕、電動車及3C產品,且價格遠低於使用矽基板之III-V族化合物半導體基板,而於製作發光二極體(light emitting diode)、光敏二極體(photodiode)、太陽電池(solar cell)、雷射二極體(laser diode)或高功率電晶體(power transistor)等元件時,更能達到高散熱及降低製作成本的目的。Therefore, the present invention uses a metal substrate to make the substrate size more flexible and has the advantages of low cost, high heat dissipation and bendability, and high carrier mobility of the III-V compound semiconductor, and can be widely applied. For large-scale building curtains, electric vehicles and 3C products, and the price is much lower than the III-V compound semiconductor substrate using the germanium substrate, and the light emitting diode, photodiode, sun When components such as a solar cell, a laser diode, or a high-power transistor are used, the heat dissipation and the manufacturing cost can be achieved.
再者,本發明進行熱處理時,可藉由該矽第一緩衝層、該化合物半導體第二緩衝層及該化合物半導體第三緩衝層共同作用使貫穿式差排的產生機會降低,進而得到更佳品質的化合物半導體磊晶片。Furthermore, in the heat treatment of the present invention, the first buffer layer, the second buffer layer of the compound semiconductor, and the third buffer layer of the compound semiconductor can work together to reduce the chance of generation of the through-type difference, thereby further improving Quality compound semiconductor epitaxial wafer.
為充分瞭解本發明之目的、特徵及功效,茲藉由下述具體之實施例,並配合所附之圖式,對本發明做一詳細說明,說明如後:首先,請參閱第四圖,係本發明實施例中一化合物半導體磊晶片50之構造剖面圖。於本實施例中,長晶製程中的沉積製程可採用有機金屬化學氣相沉積製程,而磊晶製程可採用分子束磊晶製程,所採用的化合物半導體薄膜層係以砷化鎵(GaAs)為示例。首先,於長晶系統內,於一金屬基板51上進行一沉積製程,可用矽烷(SiH4 )為反應氣體,沉積溫度約為580~600℃,在該金屬基板51上沉積一層厚度約為15~25的矽薄膜,可為非晶矽薄膜,以形成一矽第一緩衝層52。接著在該矽第一緩衝層52上進行沉積製程,可採用三甲基鎵(Ga(CH3 )3 )與三氫化砷(AsH3 )反應氣體,在溫度約為380~400℃狀況下沉積一層化合物半導體薄膜以形成一化合物半導體第二緩衝層53,厚度約為10至20μm。接著在該化合物半導體第二緩衝層53上再進行沉積製程,同樣可採用三甲基鎵與三氫化砷為反應氣體,在溫度約為400~450℃狀況下沉積一層化合物半導體薄膜以形成一化合物半導體第三緩衝層54,厚度約為50~200。接著在該化合物半導體第三緩衝層54上進行磊晶製程,同樣可採用三甲基鎵與三氫化砷為反應氣體,在溫度約為650℃狀況下磊晶一層化合物半導體薄膜以形成一化合物半導體第一磊晶層55,厚度約為1.5~2μm。然後在原長晶系統內進行第一次溫度循環退火熱處理。In order to fully understand the object, features and advantages of the present invention, the present invention will be described in detail by the following specific embodiments and the accompanying drawings, which are illustrated as follows: First, please refer to the fourth figure, A cross-sectional view showing the structure of a compound semiconductor epitaxial wafer 50 in the embodiment of the present invention. In this embodiment, the deposition process in the growth process may be performed by an organometallic chemical vapor deposition process, and the epitaxial process may employ a molecular beam epitaxy process using a compound semiconductor thin film layer of gallium arsenide (GaAs). As an example. First, in a crystal growth system, a deposition process is performed on a metal substrate 51, and decane (SiH 4 ) is used as a reaction gas, a deposition temperature is about 580 to 600 ° C, and a thickness of about 15 is deposited on the metal substrate 51. ~25 The tantalum film may be an amorphous tantalum film to form a first buffer layer 52. Then, a deposition process is performed on the first buffer layer 52 of the crucible, and a reaction gas of trimethylgallium (Ga(CH 3 ) 3 ) and arsine (AsH 3 ) may be used to deposit at a temperature of about 380 to 400 ° C. A layer of the compound semiconductor film is formed to form a compound semiconductor second buffer layer 53 having a thickness of about 10 to 20 μm. Then, a deposition process is further performed on the second buffer layer 53 of the compound semiconductor, and a compound semiconductor film is deposited at a temperature of about 400-450 ° C to form a compound by using a reaction gas of trimethylgallium and arsine. The third buffer layer 54 of the semiconductor has a thickness of about 50~200 . Then, an epitaxial process is performed on the third buffer layer 54 of the compound semiconductor. Similarly, trimethylgallium and arsine are used as reaction gases, and a compound semiconductor film is epitaxially formed at a temperature of about 650 ° C to form a compound semiconductor. The first epitaxial layer 55 has a thickness of about 1.5 to 2 μm. The first temperature cycle annealing heat treatment is then performed in the original crystal growth system.
接著請參閱第五圖,係本發明實施例中溫度循環退火熱處理之高低溫加熱示意圖。如第五圖所示,首先將系統溫度降至200℃,維持約7分鐘,接著提高系統溫度至800℃,維持約5分鐘,然後再將系統溫度降至200℃,維持約5分鐘,接著提高系統溫度至800℃,維持約5分鐘,如此經過約4~8次的高低溫循環退火熱處理程序,以降低該些緩衝層與該化合物半導體第一磊晶層55間因晶格常數或熱膨脹係數產生貫穿式差排效應的機會。Next, please refer to the fifth figure, which is a schematic diagram of high and low temperature heating of the temperature cycle annealing heat treatment in the embodiment of the present invention. As shown in Figure 5, first reduce the system temperature to 200 ° C for about 7 minutes, then increase the system temperature to 800 ° C for about 5 minutes, then reduce the system temperature to 200 ° C for about 5 minutes, then Increasing the system temperature to 800 ° C for about 5 minutes, such that after about 4 to 8 cycles of high and low temperature cyclic annealing heat treatment to reduce the lattice constant or thermal expansion between the buffer layer and the first epitaxial layer 55 of the compound semiconductor The coefficient creates an opportunity for a through-displacement effect.
俟完成第一次的溫度循環退火熱處理後,將長晶系統的溫度降至約710℃並進行磊晶製程。磊晶製程可應用三甲基鎵與三氫化砷為反應氣體在該化合物半導體第一磊晶層55上進行,磊晶一層化合物半導體薄膜以形成一化合物半導體第二磊晶層56,厚度約為1.5~2μm。接著在長晶系統內進行第二次的溫度循環退火熱處理,亦如第五圖所示,首先將系統溫度降至200℃,維持約7分鐘,接著提高系統溫度至800℃,維持約5分鐘,然後再將系統溫度降至200℃,維持約5分鐘,接著提高系統溫度至800℃,維持約5分鐘,如此經過約4~8次的高低溫循環退火熱處理程序,以降低該化合物半導體第二磊晶層56的貫穿式差排產生的機會,並可去除該金屬基板51與該化合物半導體第二磊晶層56間的所有應力。After the first temperature cycle annealing heat treatment is completed, the temperature of the crystal growth system is lowered to about 710 ° C and an epitaxial process is performed. The epitaxial process can be performed on the first epitaxial layer 55 of the compound semiconductor by using trimethylgallium and arsine as reaction gases, and a compound semiconductor film is epitaxially formed to form a compound semiconductor second epitaxial layer 56, and the thickness is about 1.5 to 2 μm. Then a second temperature cycle annealing heat treatment is performed in the crystal growth system. As shown in the fifth figure, the system temperature is first lowered to 200 ° C for about 7 minutes, and then the system temperature is increased to 800 ° C for about 5 minutes. Then, the system temperature is lowered to 200 ° C, maintained for about 5 minutes, and then the system temperature is increased to 800 ° C for about 5 minutes, such that after about 4 to 8 times of high and low temperature cycle annealing heat treatment procedures to reduce the compound semiconductor The through-difference of the two epitaxial layers 56 creates an opportunity to remove all stress between the metal substrate 51 and the second epitaxial layer 56 of the compound semiconductor.
前述實施例中,該化合物半導體薄膜層係以砷化鎵(GaAs)為示例,然砷化鋁(AlAs)、磷化鎵(GaP)、砷化銦(InAs)、磷化銦(InP)等III-V族化合物半導體二元材料或由其組成之三元或四元材料皆可實施本發明。In the foregoing embodiment, the compound semiconductor thin film layer is exemplified by gallium arsenide (GaAs), and aluminum arsenide (AlAs), gallium phosphide (GaP), indium arsenide (InAs), indium phosphide (InP), etc. The invention may be practiced with a III-V compound semiconductor binary material or a ternary or quaternary material composed thereof.
本發明之化合物半導體磊晶片之製造方法主要包含:於該金屬基板51上沉積一層矽薄膜以形成該矽第一緩衝層52,接著於該矽第一緩衝層52上沉積一層化合物半導體薄膜以形成該化合物半導體第二緩衝層53,再於該化合物半導體第二緩衝層53上沉積一層化合物半導體薄膜以形成該化合物半導體第三緩衝層54,再於該化合物半導體第三緩衝層54上磊晶一層化合物半導體薄膜以形成該化合物半導體第一磊晶層55,接著施以第一次熱處理程序,再於該化合物半導體第一磊晶層55上磊晶一層化合物半導體薄膜以形成該化合物半導體第二磊晶層56,然後施以第二次熱處理程序,如此即可得到良好晶體品質的該化合物半導體磊晶片50。該長晶製程中的沉積製程為有機金屬氣相沈積製程,該磊晶製程為分子束磊晶製程。The method for fabricating a compound semiconductor epitaxial wafer of the present invention mainly comprises: depositing a germanium film on the metal substrate 51 to form the first buffer layer 52, and then depositing a compound semiconductor film on the first buffer layer 52 to form a thin film. The compound semiconductor second buffer layer 53 is further deposited on the compound semiconductor second buffer layer 53 to form a compound semiconductor thin film 54 to form a compound semiconductor third buffer layer 54 and then epitaxially layered on the compound semiconductor third buffer layer 54. Forming a compound semiconductor film to form the first epitaxial layer 55 of the compound semiconductor, and then applying a first heat treatment process, and then epitaxially depositing a compound semiconductor film on the first epitaxial layer 55 of the compound semiconductor to form the second semiconductor of the compound semiconductor The crystal layer 56 is then subjected to a second heat treatment process, so that the compound semiconductor epitaxial wafer 50 of good crystal quality can be obtained. The deposition process in the crystal growth process is an organometallic vapor deposition process, and the epitaxial process is a molecular beam epitaxy process.
本創作製備金屬基板之化合物半導體磊晶片50包含該金屬基板51、設置於該金屬基板51上之該矽第一緩衝層52、設置於該矽第一緩衝層52上之該化合物半導體第二緩衝層53、設置於該化合物半導體第二緩衝層53上之該化合物半導體第三緩衝層54、設置於該化合物半導體第三緩衝層54上之該化合物半導體第一磊晶層55、以及設置於該化合物半導體第一磊晶層55上之該化合物半導體第二磊晶層56。該矽第一緩衝層52與該化合物半導體第二緩衝層53係用以使貫穿式差排在緩衝層內相互結合,達到降低貫穿式差排密度的目的,而該化合物半導體第三緩衝層54係用以消除剩餘之貫穿式差排在緩衝層的密度。而該化合物半導體第一磊晶層54則用以提供該化合物半導體第二磊晶層55成長所需的單晶結構。The compound semiconductor epitaxial wafer 50 of the present invention comprises a metal substrate 51, the first buffer layer 52 disposed on the metal substrate 51, and a second buffer of the compound semiconductor disposed on the first buffer layer 52. a compound 53, a third buffer layer 54 disposed on the second buffer layer 53 of the compound semiconductor, a first epitaxial layer 55 of the compound semiconductor disposed on the third buffer layer 54 of the compound semiconductor, and a layer The compound semiconductor second epitaxial layer 56 on the first epitaxial layer 55 of the compound semiconductor. The first buffer layer 52 and the second buffer layer 53 of the compound semiconductor are used to combine the through-type difference in the buffer layer to achieve the purpose of reducing the through-difference density, and the compound semiconductor third buffer layer 54 It is used to eliminate the remaining through-type difference in the density of the buffer layer. The first epitaxial layer 54 of the compound semiconductor is used to provide a single crystal structure required for the growth of the second epitaxial layer 55 of the compound semiconductor.
接著請參閱第六圖,係本發明實施例中化合物半導體磊晶片50之變晶X-射線搖擺曲線量測圖,圖中顯示砷化鎵材質的化合物半導體磊晶層之半高波寬值為55arcsec。將此結果與第二習知技術的結果140arcsec、第三習知技術的結果130arcsec相較,可得知本發明在金屬基板上成長的化合物半導體磊晶片之品質確實比矽基板上成長的磊晶品質更佳。Next, referring to the sixth figure, a metamorphic X-ray rocking curve measurement diagram of the compound semiconductor epitaxial wafer 50 in the embodiment of the present invention, wherein the half-height wavelength width of the compound semiconductor epitaxial layer of gallium arsenide material is 55 arcsec. . Comparing this result with the result of the second conventional technique 140arcsec and the result of the third conventional technique 130arcsec, it can be seen that the quality of the compound semiconductor epitaxial wafer grown on the metal substrate of the present invention is indeed higher than that of the epitaxial growth on the germanium substrate. Better quality.
接著請參閱第七圖,係本發明再一實施例中太陽能電池磊晶片60之剖面示意圖。如第七圖所示,一太陽能電池磊晶片60係於本發明之該化合物半導體磊晶片50上磊晶一層背面場(backside field)磊晶層61,接著依序磊晶一基極層(base layer)62、一射極層(emitter layer)63、一光窗層(window layer)64及一接觸層(contact layer)65以形成一太陽能電池結構。Next, please refer to the seventh figure, which is a schematic cross-sectional view of a solar cell epitaxial wafer 60 in still another embodiment of the present invention. As shown in the seventh figure, a solar cell epitaxial wafer 60 is epitaxially epitaxially epitaxially layered on the compound epitaxial wafer 50 of the present invention, followed by epitaxially de-emerging a base layer (base). A layer 62, an emitter layer 63, a window layer 64, and a contact layer 65 form a solar cell structure.
本發明在上文中已以較佳實施例揭露,然熟習本項技術者應理解的是,該實施例僅用於描繪本發明,而不應解讀為限制本發明之範圍。應注意的是,舉凡與該實施例等效之變化與置換,均應設為涵蓋於本發明之範疇內。因此,本發明之保護範圍當以下文之申請專利範圍所界定者為準。The invention has been described above in terms of the preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.
20...化合物半導體磊晶片20. . . Compound semiconductor epitaxial wafer
21...矽基板twenty one. . .矽 substrate
22...砷化鎵第一緩衝層twenty two. . . Gallium arsenide first buffer layer
23...砷化鎵第一磊晶層twenty three. . . Gallium arsenide first epitaxial layer
24...砷化鎵第二緩衝層twenty four. . . Gallium arsenide second buffer layer
25...砷化鎵第二磊晶層25. . . GaAs second epitaxial layer
30...化合物半導體磊晶片30. . . Compound semiconductor epitaxial wafer
31...矽基板31. . .矽 substrate
32...砷化鎵第一緩衝層32. . . Gallium arsenide first buffer layer
33...砷化鎵第一磊晶層33. . . Gallium arsenide first epitaxial layer
34...砷化鎵第二緩衝層34. . . Gallium arsenide second buffer layer
35...砷化鎵第二磊晶層35. . . GaAs second epitaxial layer
40...化合物半導體磊晶片40. . . Compound semiconductor epitaxial wafer
41...矽基板41. . .矽 substrate
42...砷化鎵第一緩衝層42. . . Gallium arsenide first buffer layer
43...砷化鎵第一磊晶層43. . . Gallium arsenide first epitaxial layer
44...砷化鎵第二磊晶層44. . . GaAs second epitaxial layer
50...化合物半導體磊晶片50. . . Compound semiconductor epitaxial wafer
51...金屬基板51. . . Metal substrate
52...矽第一緩衝層52. . .矽first buffer layer
53...化合物半導體第二緩衝層53. . . Compound semiconductor second buffer layer
54...化合物半導體第三緩衝層54. . . Compound semiconductor third buffer layer
55...化合物半導體第一磊晶層55. . . Compound semiconductor first epitaxial layer
56...化合物半導體第二磊晶層56. . . Compound semiconductor second epitaxial layer
60...太陽能電池磊晶片60. . . Solar cell epitaxial wafer
61...背面場磊晶層61. . . Back field epitaxial layer
62...基極層62. . . Base layer
63...射極層63. . . Emitter layer
64...光窗層64. . . Light window layer
65...接觸層65. . . Contact layer
第一圖為第一習知技術之化合物半導體磊晶片之剖面示意圖。The first figure is a schematic cross-sectional view of a compound semiconductor epitaxial wafer of the first prior art.
第二圖為第二習知技術之化合物半導體磊晶片之剖面示意圖。The second figure is a schematic cross-sectional view of a compound semiconductor epitaxial wafer of the second prior art.
第三圖為第三習知技術之化合物半導體磊晶片之剖面示意圖。The third figure is a schematic cross-sectional view of a compound semiconductor epitaxial wafer of the third prior art.
第四圖為本發明實施例中化合物半導體磊晶片之構造剖面圖。The fourth figure is a cross-sectional view showing the structure of a compound semiconductor epitaxial wafer in the embodiment of the present invention.
第五圖為本發明實施例中溫度循環退火熱處理之高低溫加熱示意圖。The fifth figure is a schematic diagram of high and low temperature heating of the temperature cycle annealing heat treatment in the embodiment of the present invention.
第六圖為本發明實施例中化合物半導體磊晶片之變晶X-射線搖擺曲線量測圖。The sixth figure is a measurement diagram of the crystallized X-ray rocking curve of the compound semiconductor epitaxial wafer in the embodiment of the present invention.
第七圖為本發明再一實施例中太陽能電池磊晶片之剖面示意圖。FIG. 7 is a schematic cross-sectional view showing a solar cell epitaxial wafer according to still another embodiment of the present invention.
50...化合物半導體磊晶片50. . . Compound semiconductor epitaxial wafer
51...金屬基板51. . . Metal substrate
52...矽第一緩衝層52. . .矽first buffer layer
53...化合物半導體第二緩衝層53. . . Compound semiconductor second buffer layer
54...化合物半導體第三緩衝層54. . . Compound semiconductor third buffer layer
55...化合物半導體第一磊晶層55. . . Compound semiconductor first epitaxial layer
56...化合物半導體第二磊晶層56. . . Compound semiconductor second epitaxial layer
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