TWI387999B - Compound semiconductor epitaxial wafer and method of manufacturing the same - Google Patents

Description

Compound semiconductor epitaxial wafer and method of manufacturing same

The present invention relates to a compound semiconductor and a method of fabricating the same, and more particularly to a compound semiconductor epitaxial wafer grown on a metal substrate and a method of fabricating the same.

With the rapid development of the optoelectronics and communication industries, compound semiconductors such as gallium arsenide (GaAs) and other III-V compounds rely on their direct band-gap, carrier mobility, and by adjustment. The superior chemical properties of III-V compounds, such as materials with different energy gaps, have become the main substrates for the fabrication of optoelectronic and communication components.

The fabrication of optoelectronic and communication components of III-V compound semiconductors is mainly based on III-V compounds such as gallium arsenide (GaAs), gallium phosphide (GaP) and indium phosphide (InP). Epitaxial growth is performed under the condition of lattice matching. At present, a III-V compound semiconductor substrate has a diameter of four or more gallium arsenide (GaAs) or germanium (Ge) material substrates, or a single crystal germanium substrate (Si).

However, due to problems such as lattice mismatch and difference in thermal expansion coefficient between the buffer layer and the III-V compound semiconductor material, for example, the lattice constant of the buffer layer and the gallium arsenide material is 25 ° C. The difference is about 4.1%. Furthermore, the thermal expansion coefficient of the buffer layer and the gallium arsenide material differs by about 62% at 25 °C. Therefore, when the III-V compound semiconductor material is epitaxially deposited on the buffer layer, threading dlslocation is formed in the epitaxial layer of the compound semiconductor due to problems such as lattice mismatch and different thermal expansion coefficients, thereby causing crystal quality. Not good.

The first figure is a schematic cross-sectional view of a compound semiconductor epitaxial growth on a germanium substrate by a first conventional technique. As shown in the first figure, a compound semiconductor epitaxial wafer 20 includes: a germanium substrate 21, a gallium arsenide first buffer layer 22, a gallium arsenide first epitaxial layer 23, and a gallium arsenide second buffer layer 24. a gallium arsenide second epitaxial layer 25. The compound semiconductor epitaxial wafer 20 is prepared by a metal-organic chemical vapor deposition method, first performing a deposition process on the germanium substrate 21, wherein the deposition process has a temperature of about 450 ° C, and deposition. The gallium arsenide first buffer layer 22 is formed to have a thickness of 5 to 20 μm. Then, an epitaxial process of the first epitaxial layer of the gallium arsenide is performed, wherein the temperature of the epitaxial process is 650 ° C, and the thickness of the first epitaxial layer 23 of the gallium arsenide is 1 μm after epitaxy. Then, a deposition process is performed, wherein the temperature of the deposition process is also about 450 ° C, and the second buffer layer 24 of the gallium arsenide is formed to have a thickness of 5 to 20 nm after deposition. The epitaxial process of the second epitaxial layer of gallium arsenide is further performed, wherein the temperature of the epitaxial process is also about 650 ° C, and the thickness of the second arsenide layer 25 after epitaxial formation is about 2 μm.

The first prior art technique utilizes a two-layer gallium arsenide buffer layer (22, 24) and a two-layer gallium arsenide epitaxial layer (23, 25) to improve the quality of epitaxial gallium arsenide on the germanium substrate 21. However, this process still needs to add a thermal cycle annealing heat treatment procedure to further improve the quality of the gallium arsenide epitaxial layer.

The second figure is a schematic cross-sectional view of a compound semiconductor epitaxial wafer of the second prior art. As shown in the second figure, a compound semiconductor epitaxial wafer 30 includes: a germanium substrate 31, a gallium arsenide first buffer layer 32, a gallium arsenide first epitaxial layer 33, and an indium gallium arsenide second buffer layer. 34. A gallium arsenide second epitaxial layer 35. The preparation method of the compound semiconductor epitaxial wafer 30 is also performed by an organometallic chemical vapor deposition method. First, a deposition process is performed on the germanium substrate 31, wherein the deposition process temperature is 430 ° C, and the first buffer of the gallium arsenide is formed after deposition. Layer 32 has a thickness of 50 nm. Then, the epitaxial process of the first epitaxial layer 33 of the gallium arsenide is performed, wherein the temperature of the epitaxial process is 620 ° C, and the thickness of the first epitaxial layer 33 of the gallium arsenide is 2 μm after epitaxy. At this point, the temperature cycle annealing heat treatment procedure is followed by first reducing the temperature of the epitaxial wafer in the organometallic chemical vapor deposition system to 300 ° C. After reaching this temperature, the epitaxial wafer is heated to 750 ° C, and at 750 ° C. 5 minutes, then lower the temperature to 300 ° C, so a temperature cycle. After one or four temperature cycle annealing heat treatments, a deposition process is further performed, wherein the deposition process has a temperature of 620 ° C, and the second indium gallium arsenide buffer layer 34 is formed to have a thickness of 200 nm after deposition. Then, the epitaxial process of the second epitaxial layer 35 of the gallium arsenide is performed, wherein the temperature of the epitaxial process is also 620 ° C, and the thickness of the second epitaxial layer 35 of the gallium arsenide is 1.8 μm after epitaxy.

The second conventional technique utilizes a layer of gallium arsenide first buffer layer 32 and a layer of gallium arsenide first epitaxial layer 33, and undergoes temperature cycle annealing heat treatment to reduce the chance of penetrating discontinuity, thereby growing the indium arsenide. The gallium second buffer layer 34 and the arsenic recording second epitaxial layer 35 are used to improve the epitaxial quality of gallium arsenide on the germanium substrate 31. According to the results of the second conventional technique, the double crystal X-ray rocking curve of the gallium arsenide first epitaxial layer 33 is measured half by one temperature cycle annealing heat treatment. The Full Width at Half Maximum (FWHM) value is 280 arcsec. However, under the condition of four temperature cycle annealing heat treatments, the twin-crystal X-ray rocking curve measurement of the gallium arsenide first epitaxial layer 33 exhibits a half-height wave width drop of 140 arcsec. This phenomenon indicates that the temperature cycle annealing heat treatment has a significant effect on the epitaxial quality of gallium arsenide on the germanium substrate.

The third figure is a schematic cross-sectional view of a compound semiconductor epitaxial wafer of the third prior art. As shown in the third figure, a compound semiconductor epitaxial wafer 40 includes: a germanium substrate 41, a gallium arsenide first buffer layer 42, a gallium arsenide first epitaxial layer 43, and a gallium arsenide second epitaxial layer. 44. The preparation method of the compound semiconductor epitaxial wafer 40 is also performed by an organometallic chemical vapor deposition method. First, a deposition process is performed on the germanium substrate 41, wherein the deposition process temperature is 400 ° C, and the first buffer of the gallium arsenide is formed after deposition. Layer 42 has a thickness of less than 200 nm. Then, the epitaxial process of the first epitaxial layer 43 of the gallium arsenide is performed, wherein the temperature of the epitaxial process is 700 ° C, and the thickness of the first epitaxial layer 43 of the gallium arsenide is 1 μm after epitaxy. At this point, the temperature cycle annealing heat treatment procedure is followed by first reducing the temperature of the epitaxial wafer in the organometallic chemical vapor deposition system to room temperature. After reaching this temperature, the epitaxial crystal is heated to 850 ° C and maintained at 850 ° C. 5 minutes, then lower the temperature to 700 °C. Then, the epitaxial growth of the second epitaxial layer 44 of the gallium arsenide is performed, such that a temperature cycle epitaxial process is performed, and after three to thirteen temperature cycle epitaxy processes, the heat treatment and the gallium arsenide are simultaneously completed. The epitaxial growth process of the second epitaxial layer 44 forms a thickness of the GaN gallium second epitaxial layer 44 of 3 to 4 μm.

The third conventional technique utilizes a layer of gallium arsenide first buffer layer 42, a layer of gallium arsenide first epitaxial layer 43 and simultaneous temperature cycle annealing heat treatment and epitaxial process to reduce the generation of through-type difference rows. The gallium arsenide second epitaxial layer 44 is further obtained to improve the epitaxial quality of gallium arsenide on the germanium substrate 41. According to the experimental results of Itoh et al., after three to thirteen temperature cycling epitaxial processes, the twin-crystal X-ray rocking curve of the second epitaxial layer 44 of gallium arsenide exhibits a half-height width value. 130arcsec. Therefore, although the method adopted by the third conventional technique can improve the epitaxial quality of gallium arsenide, the quality of the second epitaxial layer 44 of the gallium arsenide is still determined by the measurement result of the twin-crystal X-ray rocking curve. It is quite low.

Therefore, in the compound semiconductor epitaxial wafer, the process steps, the epitaxial structure, and the temperature cycle annealing heat treatment process all have the crystal quality of the epitaxial wafer.

The object of the present invention is to provide a compound semiconductor epitaxial wafer with good crystal quality and characteristics and a manufacturing method thereof, which are improved by using a substrate of a metal substrate, and a process step of an epitaxial structure and a temperature cycle annealing heat treatment process to achieve crystal quality. Advantages of enhancement, process simplification and cost reduction.

To achieve the above object, a method for fabricating a compound semiconductor epitaxial wafer of the present invention comprises the steps of: depositing a tantalum film on a metal substrate to form a first buffer layer; depositing a compound semiconductor film on the first buffer layer of the tantalum Forming a second buffer layer of a compound semiconductor; depositing a compound semiconductor film on the second buffer layer of the compound semiconductor to form a third buffer layer of the compound semiconductor; and epitaxially depositing a compound semiconductor film on the third buffer layer of the compound semiconductor to Forming a first epitaxial layer of a compound semiconductor; applying a first heat treatment process; epitaxially depositing a compound semiconductor film on the first epitaxial layer of the compound semiconductor to form a second epitaxial layer of the compound semiconductor; A second heat treatment procedure is performed to complete a compound semiconductor epitaxial wafer.

In order to achieve the above object, the compound semiconductor epitaxial wafer of the present invention comprises: a metal substrate; a first buffer layer disposed on the metal substrate; and a second buffer layer of the compound semiconductor disposed on the first buffer layer of the germanium a third buffer layer of the compound semiconductor is disposed on the second buffer layer of the compound semiconductor, and the third buffer layer of the compound semiconductor is subjected to a first heat treatment process; a first epitaxial layer of the compound semiconductor is disposed on The compound semiconductor is provided on the third buffer layer; and a compound semiconductor second epitaxial layer is disposed on the first epitaxial layer of the compound semiconductor, and the second epitaxial layer of the compound semiconductor is subjected to a second heat treatment process.

In an embodiment of the present invention, the compound semiconductor second buffer layer, the compound semiconductor third buffer layer, the compound semiconductor first epitaxial layer, and the compound semiconductor second epitaxial layer may be made of gallium arsenide or arsenic. A III-V compound semiconductor binary material such as aluminum, gallium phosphide, indium arsenide or indium phosphide or a ternary or quaternary material composed thereof.

In the embodiment of the present invention, the deposition process may be an organometallic chemical vapor deposition process, and the epitaxial process may be a molecular beam epitaxy process. The deposition process of the first buffer layer of the crucible is performed at a temperature of about 580 to 600 ° C, and the deposition thickness is about 15 to 25 . The deposition process of the second buffer layer of the compound semiconductor is performed at a temperature of about 380 to 400 ° C and a deposition thickness of about 10 to 20 μm. The deposition process of the third buffer layer of the compound semiconductor is performed at a temperature of about 400 to 450 ° C, and the deposition thickness is about 50 to 200. . The epitaxial process of the first epitaxial layer of the compound semiconductor is performed at a temperature of about 650 ° C, and the epitaxial thickness is about 1.5 to 2 μm. The epitaxial process of the second epitaxial layer of the compound semiconductor is performed at a temperature of about 710 ° C, and the epitaxial thickness is about 1.5 to 2 μm.

In the embodiment of the present invention, the first heat treatment process and the second heat treatment process are both a high and low temperature cycle annealing heat treatment process, and the high and low temperature cycle annealing heat treatment process is subjected to high and low temperature cycles of 4 to 8 times.

Therefore, the present invention uses a metal substrate to make the substrate size more flexible and has the advantages of low cost, high heat dissipation and bendability, and high carrier mobility of the III-V compound semiconductor, and can be widely applied. For large-scale building curtains, electric vehicles and 3C products, and the price is much lower than the III-V compound semiconductor substrate using the germanium substrate, and the light emitting diode, photodiode, sun When components such as a solar cell, a laser diode, or a high-power transistor are used, the heat dissipation and the manufacturing cost can be achieved.

Furthermore, in the heat treatment of the present invention, the first buffer layer, the second buffer layer of the compound semiconductor, and the third buffer layer of the compound semiconductor can work together to reduce the chance of generation of the through-type difference, thereby further improving Quality compound semiconductor epitaxial wafer.

In order to fully understand the object, features and advantages of the present invention, the present invention will be described in detail by the following specific embodiments and the accompanying drawings, which are illustrated as follows: First, please refer to the fourth figure, A cross-sectional view showing the structure of a compound semiconductor epitaxial wafer 50 in the embodiment of the present invention. In this embodiment, the deposition process in the growth process may be performed by an organometallic chemical vapor deposition process, and the epitaxial process may employ a molecular beam epitaxy process using a compound semiconductor thin film layer of gallium arsenide (GaAs). As an example. First, in a crystal growth system, a deposition process is performed on a metal substrate 51, and decane (SiH ₄ ) is used as a reaction gas, a deposition temperature is about 580 to 600 ° C, and a thickness of about 15 is deposited on the metal substrate 51. ~25 The tantalum film may be an amorphous tantalum film to form a first buffer layer 52. Then, a deposition process is performed on the first buffer layer 52 of the crucible, and a reaction gas of trimethylgallium (Ga(CH ₃ ) ₃ ) and arsine (AsH ₃ ) may be used to deposit at a temperature of about 380 to 400 ° C. A layer of the compound semiconductor film is formed to form a compound semiconductor second buffer layer 53 having a thickness of about 10 to 20 μm. Then, a deposition process is further performed on the second buffer layer 53 of the compound semiconductor, and a compound semiconductor film is deposited at a temperature of about 400-450 ° C to form a compound by using a reaction gas of trimethylgallium and arsine. The third buffer layer 54 of the semiconductor has a thickness of about 50~200 . Then, an epitaxial process is performed on the third buffer layer 54 of the compound semiconductor. Similarly, trimethylgallium and arsine are used as reaction gases, and a compound semiconductor film is epitaxially formed at a temperature of about 650 ° C to form a compound semiconductor. The first epitaxial layer 55 has a thickness of about 1.5 to 2 μm. The first temperature cycle annealing heat treatment is then performed in the original crystal growth system.

Next, please refer to the fifth figure, which is a schematic diagram of high and low temperature heating of the temperature cycle annealing heat treatment in the embodiment of the present invention. As shown in Figure 5, first reduce the system temperature to 200 ° C for about 7 minutes, then increase the system temperature to 800 ° C for about 5 minutes, then reduce the system temperature to 200 ° C for about 5 minutes, then Increasing the system temperature to 800 ° C for about 5 minutes, such that after about 4 to 8 cycles of high and low temperature cyclic annealing heat treatment to reduce the lattice constant or thermal expansion between the buffer layer and the first epitaxial layer 55 of the compound semiconductor The coefficient creates an opportunity for a through-displacement effect.

After the first temperature cycle annealing heat treatment is completed, the temperature of the crystal growth system is lowered to about 710 ° C and an epitaxial process is performed. The epitaxial process can be performed on the first epitaxial layer 55 of the compound semiconductor by using trimethylgallium and arsine as reaction gases, and a compound semiconductor film is epitaxially formed to form a compound semiconductor second epitaxial layer 56, and the thickness is about 1.5 to 2 μm. Then a second temperature cycle annealing heat treatment is performed in the crystal growth system. As shown in the fifth figure, the system temperature is first lowered to 200 ° C for about 7 minutes, and then the system temperature is increased to 800 ° C for about 5 minutes. Then, the system temperature is lowered to 200 ° C, maintained for about 5 minutes, and then the system temperature is increased to 800 ° C for about 5 minutes, such that after about 4 to 8 times of high and low temperature cycle annealing heat treatment procedures to reduce the compound semiconductor The through-difference of the two epitaxial layers 56 creates an opportunity to remove all stress between the metal substrate 51 and the second epitaxial layer 56 of the compound semiconductor.

In the foregoing embodiment, the compound semiconductor thin film layer is exemplified by gallium arsenide (GaAs), and aluminum arsenide (AlAs), gallium phosphide (GaP), indium arsenide (InAs), indium phosphide (InP), etc. The invention may be practiced with a III-V compound semiconductor binary material or a ternary or quaternary material composed thereof.

The method for fabricating a compound semiconductor epitaxial wafer of the present invention mainly comprises: depositing a germanium film on the metal substrate 51 to form the first buffer layer 52, and then depositing a compound semiconductor film on the first buffer layer 52 to form a thin film. The compound semiconductor second buffer layer 53 is further deposited on the compound semiconductor second buffer layer 53 to form a compound semiconductor thin film 54 to form a compound semiconductor third buffer layer 54 and then epitaxially layered on the compound semiconductor third buffer layer 54. Forming a compound semiconductor film to form the first epitaxial layer 55 of the compound semiconductor, and then applying a first heat treatment process, and then epitaxially depositing a compound semiconductor film on the first epitaxial layer 55 of the compound semiconductor to form the second semiconductor of the compound semiconductor The crystal layer 56 is then subjected to a second heat treatment process, so that the compound semiconductor epitaxial wafer 50 of good crystal quality can be obtained. The deposition process in the crystal growth process is an organometallic vapor deposition process, and the epitaxial process is a molecular beam epitaxy process.

The compound semiconductor epitaxial wafer 50 of the present invention comprises a metal substrate 51, the first buffer layer 52 disposed on the metal substrate 51, and a second buffer of the compound semiconductor disposed on the first buffer layer 52. a compound 53, a third buffer layer 54 disposed on the second buffer layer 53 of the compound semiconductor, a first epitaxial layer 55 of the compound semiconductor disposed on the third buffer layer 54 of the compound semiconductor, and a layer The compound semiconductor second epitaxial layer 56 on the first epitaxial layer 55 of the compound semiconductor. The first buffer layer 52 and the second buffer layer 53 of the compound semiconductor are used to combine the through-type difference in the buffer layer to achieve the purpose of reducing the through-difference density, and the compound semiconductor third buffer layer 54 It is used to eliminate the remaining through-type difference in the density of the buffer layer. The first epitaxial layer 54 of the compound semiconductor is used to provide a single crystal structure required for the growth of the second epitaxial layer 55 of the compound semiconductor.

Next, referring to the sixth figure, a metamorphic X-ray rocking curve measurement diagram of the compound semiconductor epitaxial wafer 50 in the embodiment of the present invention, wherein the half-height wavelength width of the compound semiconductor epitaxial layer of gallium arsenide material is 55 arcsec. . Comparing this result with the result of the second conventional technique 140arcsec and the result of the third conventional technique 130arcsec, it can be seen that the quality of the compound semiconductor epitaxial wafer grown on the metal substrate of the present invention is indeed higher than that of the epitaxial growth on the germanium substrate. Better quality.

Next, please refer to the seventh figure, which is a schematic cross-sectional view of a solar cell epitaxial wafer 60 in still another embodiment of the present invention. As shown in the seventh figure, a solar cell epitaxial wafer 60 is epitaxially epitaxially epitaxially layered on the compound epitaxial wafer 50 of the present invention, followed by epitaxially de-emerging a base layer (base). A layer 62, an emitter layer 63, a window layer 64, and a contact layer 65 form a solar cell structure.

The invention has been described above in terms of the preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.

20. . . Compound semiconductor epitaxial wafer

twenty one. . .矽 substrate

twenty two. . . Gallium arsenide first buffer layer

twenty three. . . Gallium arsenide first epitaxial layer

twenty four. . . Gallium arsenide second buffer layer

25. . . GaAs second epitaxial layer

30. . . Compound semiconductor epitaxial wafer

31. . .矽 substrate

32. . . Gallium arsenide first buffer layer

33. . . Gallium arsenide first epitaxial layer

34. . . Gallium arsenide second buffer layer

35. . . GaAs second epitaxial layer

40. . . Compound semiconductor epitaxial wafer

41. . .矽 substrate

42. . . Gallium arsenide first buffer layer

43. . . Gallium arsenide first epitaxial layer

44. . . GaAs second epitaxial layer

50. . . Compound semiconductor epitaxial wafer

51. . . Metal substrate

52. . .矽first buffer layer

53. . . Compound semiconductor second buffer layer

54. . . Compound semiconductor third buffer layer

55. . . Compound semiconductor first epitaxial layer

56. . . Compound semiconductor second epitaxial layer

60. . . Solar cell epitaxial wafer

61. . . Back field epitaxial layer

62. . . Base layer

63. . . Emitter layer

64. . . Light window layer

65. . . Contact layer

The first figure is a schematic cross-sectional view of a compound semiconductor epitaxial wafer of the first prior art.

The second figure is a schematic cross-sectional view of a compound semiconductor epitaxial wafer of the second prior art.

The third figure is a schematic cross-sectional view of a compound semiconductor epitaxial wafer of the third prior art.

The fourth figure is a cross-sectional view showing the structure of a compound semiconductor epitaxial wafer in the embodiment of the present invention.

The fifth figure is a schematic diagram of high and low temperature heating of the temperature cycle annealing heat treatment in the embodiment of the present invention.

The sixth figure is a measurement diagram of the crystallized X-ray rocking curve of the compound semiconductor epitaxial wafer in the embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view showing a solar cell epitaxial wafer according to still another embodiment of the present invention.

50. . . Compound semiconductor epitaxial wafer

51. . . Metal substrate

52. . .矽first buffer layer

53. . . Compound semiconductor second buffer layer

54. . . Compound semiconductor third buffer layer

55. . . Compound semiconductor first epitaxial layer

56. . . Compound semiconductor second epitaxial layer

Claims (23)

A method for fabricating a compound semiconductor epitaxial wafer, comprising the steps of: depositing a germanium film on a metal substrate to form a first buffer layer; depositing a compound semiconductor film on the first buffer layer to form a compound semiconductor a second buffer layer; a compound semiconductor film is deposited on the second buffer layer of the compound semiconductor to form a third buffer layer of the compound semiconductor; and a compound semiconductor film is epitaxially formed on the third buffer layer of the compound semiconductor to form a compound semiconductor An epitaxial layer; applying a first high-temperature cycle annealing heat treatment process; epitaxially depositing a compound semiconductor film on the first epitaxial layer of the compound semiconductor to form a compound semiconductor second epitaxial layer; A secondary high and low temperature cycle annealing heat treatment procedure is performed to complete a compound semiconductor epitaxial wafer. The manufacturing method according to claim 1, wherein the compound semiconductor film may be a III-V compound semiconductor binary material such as gallium arsenide, aluminum arsenide, gallium phosphide, indium arsenide or indium phosphide. Or a ternary or quaternary material composed of it. The manufacturing method of claim 1, wherein the deposition process is an organometallic chemical vapor deposition process. The manufacturing method according to claim 1, wherein the process of epitaxy is a molecular beam epitaxy process. The manufacturing method of claim 1, wherein the first method The deposition process of the buffer layer is carried out at a temperature of about 580 to 600 °C. The manufacturing method according to claim 1, wherein the first buffer layer has a thickness of about 15 to 25 Å. The manufacturing method according to claim 1, wherein the deposition process of the second buffer layer of the compound semiconductor is performed at a temperature of about 380 to 400 °C. The manufacturing method according to claim 1, wherein the second buffer layer of the compound semiconductor has a thickness of about 10 to 20 μm. The manufacturing method according to claim 1, wherein the deposition process of the third buffer layer of the compound semiconductor is performed at a temperature of about 400 to 450 °C. The manufacturing method according to claim 1, wherein the third buffer layer of the compound semiconductor has a thickness of about 50 to 200 Å. The manufacturing method according to claim 1, wherein the epitaxial process of the first epitaxial layer of the compound semiconductor is performed at a temperature of about 650 °C. The manufacturing method according to claim 1, wherein the epitaxial process of the second epitaxial layer of the compound semiconductor is performed at a temperature of about 710 °C. The manufacturing method according to claim 1, wherein the first epitaxial layer of the compound semiconductor has a thickness of about 1.5 to 2 μm. The manufacturing method according to claim 1, wherein the second epitaxial layer of the compound semiconductor has a thickness of about 1.5 to 2 μm. The manufacturing method described in claim 1, wherein each level is high or low The temperature cycle annealing heat treatment process is followed by 4 to 8 high and low temperature cycles. The high and low temperature cycle includes the following steps: the first high and low temperature cycle step is to first reduce the temperature to 200 ° C, maintain for about 7 minutes, and then increase the temperature to 800. °C, maintained for about 5 minutes; and the second high and low temperature cycle step, first reduce the temperature to 200 ° C, for about 5 minutes, and then increase the temperature to 800 ° C, for about 5 minutes, wherein the first high and low temperature cycle step The first high-low temperature cycle in each high-low temperature cycle annealing heat treatment process, the second high-low temperature cycle step is the second time after each of the high-temperature cycle annealing heat treatment processes The implementation steps of the high and low temperature cycle. A compound semiconductor epitaxial wafer comprising: a metal substrate; a first buffer layer disposed on the metal substrate; a second buffer layer of a compound semiconductor disposed on the first buffer layer; a compound semiconductor a third buffer layer is disposed on the second buffer layer of the compound semiconductor, and the third buffer layer of the compound semiconductor is subjected to a first high-temperature cycle annealing heat treatment process; a first epitaxial layer of the compound semiconductor is disposed on the a second buffer layer of the compound semiconductor; and a second epitaxial layer of the compound semiconductor disposed on the first epitaxial layer of the compound semiconductor, the second epitaxial layer of the compound semiconductor is subjected to a second high-temperature cycle annealing annealing heat treatment program. The compound semiconductor epitaxial wafer according to claim 16, wherein the compound semiconductor second buffer layer, the compound semiconductor third buffer layer, the compound semiconductor first epitaxial layer, and the compound semiconductor second epitaxial layer The material may be a III-V compound semiconductor binary material such as gallium arsenide, aluminum arsenide, gallium phosphide, indium arsenide or indium phosphide or a ternary or quaternary material composed thereof. The compound semiconductor epitaxial wafer according to claim 16, wherein the first buffer layer has a thickness of about 15 to 25 Å. The compound semiconductor epitaxial wafer according to claim 16, wherein the second buffer layer of the compound semiconductor has a thickness of about 10 to 20 μm. The compound semiconductor epitaxial wafer according to claim 16, wherein the third buffer layer of the compound semiconductor has a thickness of about 50 to 200 Å. The compound semiconductor epitaxial wafer according to claim 16, wherein the first epitaxial layer of the compound semiconductor has a thickness of about 1.5 to 2 μm. The compound semiconductor epitaxial wafer according to claim 16, wherein the second epitaxial layer of the compound semiconductor has a thickness of about 1.5 to 2 μm. The compound semiconductor epitaxial wafer according to claim 16, wherein each of the high and low temperature cyclic annealing heat treatment processes is subjected to 4 to 8 high and low temperature cycles, and the high and low temperature cycle comprises the following steps: a first high and low temperature cycle step, First, the temperature is lowered to 200 ° C, maintained for about 7 minutes, and then increased to 800 ° C, for about 5 minutes; and the second high and low temperature cycle step, the temperature is first reduced to 200 ° C, for about 5 minutes, and then improve The temperature is maintained at 800 ° C for about 5 minutes. Wherein, the first high and low temperature cycle step is an implementation step of the first high and low temperature cycle in each high and low temperature cycle annealing heat treatment process, and the second high and low temperature cycle step is in each high and low temperature cycle annealing heat treatment process The implementation step of the high and low temperature cycle for each of the second and subsequent times.