M260000 捌、新型說明： 【新犛所屬之技術領域】 本創作係關於化合物半導體磊晶片，特別係關於一 種利用矽質緩衝層、化合物半導體緩衝層、化合物半導 體蟲晶層與熱處理形成品質良好化合物半導體:晶層晶 體的製備。 【先前技術】 隨著光電及通訊產業急速發展，砷化鎵（GaAs)等 三-五族化合物憑藉其直接能隙（direct band—gap)、高 載子遷移率（carrier m〇biiity)、以及藉由調整三五 族化合物化學組成可得到不同能隙的材料等優越特性， 已經成為製作光電及通訊元件的主要基材。三-五族化合 物半導體光電及通訊元件的製作主要是以砷化鎵、磷化 鎵（GaP)及磷化銦（InP)等三-五族化合物為基板 (substrate),在晶格（lattice)匹配的狀況下進行磊 晶成長。載至目前為止，三-五族化合物半導體基板的直 徑多為四英吋以下，而矽基板之直徑已可作到十二英 忖，並且價格达低於三-五族化合物半導體基板，因此產 業界期望結合矽基板低成本的優點及三—五族化合物半 導體高載子遷移率等特性，將三-五族化合物半導體薄膜 成長於單晶矽基板上，製作成發光二極體（丨ight emitting diode)、光敏二極體（photodiode)、太陽電 M260000 池（solar cel 1)、雷射二極體、（iaser di〇de)或高功 率電晶體（power transistor)等元件，達到降低製作 成本的目的。然而，由於單晶矽與三—五族化合物半導體 材料之間存在晶格不匹配及熱膨脹係數（thermal expansion coefficient)不同等問題，例如，單晶矽與 砷化鎵材料的晶格常數在25°C時相差約為4· 1%，再者， 單晶矽與砷化鎵材料的熱膨脹係數在25°C時相差約為 62%。因此，將三—五族化合物半導體材料磊晶於單晶矽 基板上，會因為晶格不匹配及熱膨脹係數不同等問題在 化合物半導體磊晶層内形成貫穿式差排（让厂的心叫 dislocation)，從而造成結晶品質不佳。 所示，砷化鎵第二磊晶層/砷化M260000 Description of new models: [Technical field to which Xinxun belongs] This creation is about compound semiconductor epitopes, and in particular, a compound semiconductor using silicon buffer layer, compound semiconductor buffer layer, compound semiconductor insect layer, and heat treatment to form a good quality compound semiconductor : Preparation of crystalline layer crystals. [Previous technology] With the rapid development of the optoelectronics and communication industries, Group III-V compounds such as gallium arsenide (GaAs) rely on their direct band gap (gap), high carrier mobility (carrier mObiiity), and By adjusting the chemical composition of the three or five compounds, superior characteristics such as materials with different energy gaps can be obtained, which has become the main substrate for making optoelectronic and communication components. The production of Group III-V compound semiconductor optoelectronics and communication components is mainly based on Group III-V compounds such as gallium arsenide, gallium phosphide (GaP) and indium phosphide (InP), and the substrate is in the lattice. Epitaxial growth is performed under matched conditions. As of now, the diameter of Group III-V compound semiconductor substrates is mostly less than four inches, and the diameter of silicon substrates can be up to 12 inches, and the price is lower than that of Group III-V compound semiconductor substrates. The world expects to combine the advantages of low cost of silicon substrates and the high carrier mobility of Group III-V compound semiconductors to grow Group III-V compound semiconductor thin films on single-crystal silicon substrates to produce light emitting diodes. (diode), photodiode, solar cel 1260 (solar cel 1), laser diode, (iaser diode), or high power transistor (power transistor) to reduce production costs. purpose. However, due to the lattice mismatch and thermal expansion coefficient differences between single crystal silicon and Group III-V compound semiconductor materials, for example, the lattice constant of single crystal silicon and gallium arsenide materials is 25 °. At C, the difference is about 4.1%. Furthermore, the thermal expansion coefficient of single crystal silicon and GaAs material is about 62% at 25 ° C. Therefore, epitaxy of Group III-V compound semiconductor materials on single-crystal silicon substrates will cause penetrating differential rows in compound semiconductor epitaxial layers due to lattice mismatch and different thermal expansion coefficients. ), Resulting in poor crystal quality. As shown, the second epitaxial layer of gallium arsenide / arsenide
11進行一沉積製程， 圖1係習知之砷化鎵第二磊晶層/砷化鎵第二緩衝 層/石申化鎵第-蟲晶層/神化鎵第—緩衝層a基板 之剖面示意圖，揭示於美國專利案第4,876,219 (以 219專利）號。如圖】所 由 鎵第二 /矽基： 一砷化： 化鎵第_ 緩衝層/ 板10之製備方法係採用 (metal-organic chemical 先對矽基板11進行一沉藉制 有機金屬化學氣相沉積 vapor deposition)法，首 程，其中沉積製程之溫度為 M260000 450 C，/儿積後形成呼化錄第 一緩衝層12的厚度為5至 20nm。接績進行砷化鎵第一磊晶層的磊晶製程，其中磊 晶製程曰之溫度為65n日日後形成石申化鎵第一蠢晶層 的子度為l#m。接著再進行一沉積製程，其中沉積製 程之=度亦約為45(Γ(：，沉積後形成神化鎵第二緩衝層 14的厚度為5至2〇nm。接續再進行砷化鎵第二磊晶層的 遙晶製程’其中遙晶製程之溫度亦約為650°C，磊晶後形 成砷化鎵第二磊晶層15的厚度約為2"m。 ’ 219專利係利用兩個砷化鎵緩衝層（12、14)及兩 個坤化錄蠢晶層（13、15)來改善砷化鎵在矽基板丨丨上 遙晶的品質。但此一製程經過後續研究者的改進與驗 迅’發現在此一製程内尚需加入溫度循環退火（thermai cycle annealing)熱處理程序才可進一步有效改善砷化 蘇遙晶層的品質。 圖2係習知之砷化鎵第二磊晶層/砷化銦鎵第二緩 衝層/砷化鎵第一磊晶層/砷化鎵第一緩衝層/矽基板 20之剖面示意圖，揭示於美國期刊γ. Takano et al.， “Reduction of threading dislocations by InGaAs interlayer in GaAs layers grown on Si substrate,” Applied Physics Letters Vol· 73，No. 20，1998 pp. 2917 〜2919·(以下稱Takano等人論文）。如圖2所示，砷化 鎵第二磊晶層/砷化銦鎵第二緩衝層/砷化鎵第一磊晶 層/砷化鎵第一緩衝層/矽基板20包含一矽基板2卜一 M260000 砷化鎵第一緩衝層22、一砷化鎵第一磊晶層23、一砷化 銦鎵第二緩衝層24、一砷化鎵第二磊晶層25。該砷化鎵 第二磊晶層/砷化銦鎵第二緩衝層/砷化鎵第一磊晶層 /砷化鎵第一緩衝層/矽基板2〇之製備方法亦係採用有 機金屬化學氣相沉積法，首先對矽基板21進行一沉積製 程，其中沉積製程之溫度為43〇。匚，沉積後形成砷化鎵第 一緩衝層22的厚度為50nm。接續進行砷化鎵第一磊晶層 23的磊晶製程，其中磊晶製程之溫度為62〇π，磊晶後 形成砷化鎵第一磊晶層23的厚度為2//m。此時，緊接著 進行溫度循環退火熱處理程序，首先將有機金屬化學氣 相/儿積糸統内的蟲晶片溫度降至3 〇 〇 °c，到達此一溫度 後再加熱遙曰曰片至7 5 0 C，並在7 5 0 °C維持5分鐘，然 後再降低溫度至300°C，如此係一個溫度循環，當經過一 個或四個溫度循環退火熱處理後接著再進行一沉積製 程，其中沉積製程之溫度為620°C，沉積後形成砷化銦鎵 第二緩衝層24的厚度為200nm。接續再進行砷化鎵第二 遙晶層25的磊晶製程，其中磊晶製程之溫度亦為62〇°c， 蟲晶後形成砷化鎵第二磊晶層25的厚度為1.8 //m。11 to perform a deposition process, FIG. 1 is a schematic cross-sectional view of a substrate of a conventional gallium arsenide second epitaxial layer / gallium arsenide second buffer layer / shishenhua first-worm crystal layer / amorphous gallium first-buffer layer a substrate, Disclosed in U.S. Patent No. 4,876,219 (patent 219). As shown in the figure, the gallium second / silicon based: a arsenide: gallium sulfide buffer layer / board 10 is prepared by using (metal-organic chemical In the first process, the temperature of the deposition process is M260000 450 C, and the thickness of the first buffer layer 12 is 5 to 20 nm. The epitaxial process of the first epitaxial layer of gallium arsenide was performed successively, and the epitaxial process was performed at a temperature of 65n. In the future, the degree of formation of the first gallium layer of gallium arsenide will be l # m. Next, a deposition process is performed, where the degree of the deposition process is also about 45 ° (Γ (:, the thickness of the second buffer layer 14 formed by the deposition of gallium gallium after deposition is 5 to 20 nm. Then, the second gallium arsenide is formed. The crystal layer's telecrystal process 'temperature is about 650 ° C, and the thickness of the second gallium arsenide layer 15 after epitaxial formation is about 2 " m. The' 219 patent system uses two arsenides. The gallium buffer layer (12, 14) and the two quasi crystal layers (13, 15) improve the quality of gallium arsenide on the silicon substrate. However, this process has been improved and verified by subsequent researchers. Xun's found that in this process, the thermal cycle annealing (thermai cycle annealing) heat treatment program must be added to further effectively improve the quality of the arsenide layer. Figure 2 is the second known epitaxial layer of gallium arsenide / indium arsenide A schematic cross-sectional view of the second gallium buffer layer / gallium arsenide first epitaxial layer / gallium arsenide first buffer layer / silicon substrate 20 is disclosed in the US journal γ. Takano et al., “Reduction of threading dislocations by InGaAs interlayer in GaAs layers grown on Si substrate, "Applied Physics Le tters Vol. 73, No. 20, 1998 pp. 2917 ~ 2919 · (hereinafter referred to as Takano et al. paper). As shown in Figure 2, the second epitaxial layer of gallium arsenide / second buffer layer of indium gallium arsenide / arsenic The first gallium oxide epitaxial layer / the first gallium arsenide buffer layer / the silicon substrate 20 includes a silicon substrate 2 M260000 The first gallium arsenide buffer layer 22, a first gallium arsenide layer 23, and an arsenide Indium gallium second buffer layer 24, a second gallium arsenide epitaxial layer 25. The second gallium arsenide layer / indium gallium arsenide buffer layer / first gallium arsenide layer / gallium arsenide The first buffer layer / silicon substrate 20 is also prepared by using an organometallic chemical vapor deposition method. First, a deposition process is performed on the silicon substrate 21, wherein the deposition process temperature is 43 ° C. After the deposition, gallium arsenide is formed. The thickness of the first buffer layer 22 is 50 nm. The epitaxial process of the first epitaxial layer 23 of gallium arsenide is continued, and the temperature of the epitaxial process is 62 °. The first epitaxial layer 23 of gallium arsenide is formed after the epitaxial process. The thickness is 2 // m. At this time, followed by a temperature cycle annealing heat treatment program, first the temperature of the organometallic chemical vapor phase / earth worm wafer temperature Reduce it to 300 ° C. After reaching this temperature, heat the tablet to 750 ° C, and maintain it at 750 ° C for 5 minutes, and then lower the temperature to 300 ° C. This is a temperature cycle. After one or four temperature cycle annealing heat treatments, a deposition process is performed, wherein the temperature of the deposition process is 620 ° C, and the thickness of the indium gallium arsenide second buffer layer 24 is 200 nm after the deposition. Next, the epitaxial process of the second gallium arsenide layer 25 is performed, and the temperature of the epitaxial process is also 62 ° C. The thickness of the second gallium arsenide layer 25 after the worm crystal is 1.8 // m .
Takano等人論文係利用一個砷化鎵第一緩衝層22及 一個坤化鎵第一磊晶層23，經過溫度循環退火熱處理來 降低貫穿式差排產生的機 會，進而成長一珅化銦鎵第二 緩衝層24、一砷化鎵第二磊晶層25，以改善砷化鎵在矽 基板21上的磊晶品質。依據Takano等人的實驗結果顯 M260000 示，在經過一次溫度循環退火熱處理狀況下，神化鎵第 一蠢晶層23的雙晶X-射線搖擺曲線（double crystal X-ray rocking curve)量測呈現半高波寬（fuu width half maximum)值為280arcsec〇然而在經過四次溫度循 環退火熱處理狀況下，砷化鎵第一磊晶層23的雙晶X-射線搖擺曲線ϊ測呈現半高波寬值降為140arcsec。此一 現象表不溫度循¥退火熱處理對於石申化錄在碎基板的蟲 晶品質有顯著的效用。至於砷化鎵第二磊晶層25的雙晶 X-射線搖擺曲線量測結果在Takano等人論文中並未討 論0 圖3係習知之砷化鎵第二磊晶層/砷化鎵第一磊晶 層/砷化鎵第一缓衝層/矽基板30之剖面示意圖，揭示 於美國期刊 Y. Itoh et al·，“GaAs heteroepitaxial growth on Si for solar cell，” Applied Physics Letters Vol· 52，No· 19，1988 pp· 1617〜1618.(以下 稱Itoh等人論文），而在Itoh等人論文中的部份長晶方 法係參照日本期刊M. Akiyama et al.，“Growth of single domain layer on (100) oriented Si substrate by MOCVD，” Japanese Journal of Applied Physics Vol.23, No.ll，i984 pp.L843 〜L845·之内容。如圖 3 所示’砷化鎵第二磊晶層/砷化鎵第一磊晶層/砷化鎵 第一緩衝層/矽基板30包含一矽基板3卜一砷化鎵第一 緩衝層32、一砷化鎵第一磊晶層33、一砷化鎵第二磊晶 M260000 層34。該砷化鎵第二磊晶層/砷化鎵第一磊晶層/砷化 鎵第一缓衝層/矽基板3.0之製備方法亦係採用有機金屬 化學氣相沉積法，首先對矽基板31進行一沉積製程，其 中沉積製程之溫度為400°C，沉積後形成砷化鎵第一緩衝 層32的厚度小於200nm。接續進行砷化鎵第一磊晶層33 的蟲晶製程’其中蟲晶製程之溫度為700C ’蟲晶後形成 砷化鎵第一磊晶層33的厚度為l#m。此時，緊接著進行 溫度循環退火熱處理程序，首先將有機金屬化學氣相沉 積系統内的磊晶片溫度降至室溫，到達此一溫度後，再 加熱磊晶片至850°C，並在850°C維持5分鐘，然後再降 低溫度至700°C，進行砷化鎵第二磊晶層34的磊晶成長， 如此係一個溫度循環磊晶程序，當經過三個至十三個溫 度循壤蟲晶程序後’同時完成熱處理及神化錄第二蟲晶 層34的磊晶成長製程，形成砷化鎵第二磊晶層34的厚 度為3〜4 // m。The paper by Takano et al. Used a gallium arsenide first buffer layer 22 and a gallium first epitaxial layer 23 to reduce the chance of penetrating differential discharge through temperature cycle annealing heat treatment, thereby growing an indium gallium oxide. Two buffer layers 24 and a second epitaxial layer 25 of gallium arsenide are used to improve the epitaxial quality of gallium arsenide on the silicon substrate 21. According to the experimental results of Takano et al., M260000 shows that the double crystal X-ray rocking curve of the first crystal layer 23 of the deified gallium is half measured under a temperature cycle annealing heat treatment. The Fuu width half maximum value is 280 arcsec. However, under the conditions of four temperature cycle annealing heat treatments, the X-ray rocking curve of the twin crystal of the first epitaxial layer 23 of GaAs is estimated to have a value of half-high wave width. 140arcsec. This phenomenon indicates that the temperature-annealing heat treatment has a significant effect on the quality of the insects recorded by Shi Shenhua on the broken substrate. As for the measurement results of the twin crystal X-ray rocking curve of the second gallium arsenide layer 25, which was not discussed in the paper by Takano et al. Fig. 3 is the second known epitaxial layer of gallium arsenide / gallium arsenide first A schematic cross-sectional view of an epitaxial layer / gallium arsenide first buffer layer / silicon substrate 30 is disclosed in the American journal Y. Itoh et al., "GaAs heteroepitaxial growth on Si for solar cell," Applied Physics Letters Vol. 52, No. · 19, 1988 pp · 1617 ~ 1618. (Hereinafter referred to as the Itoh et al. Paper), and part of the crystal growth method in the Itoh et al. Paper refers to the Japanese journal M. Akiyama et al., "Growth of single domain layer on (100) oriented Si substrate by MOCVD, "Japanese Journal of Applied Physics Vol.23, No.ll, i984 pp.L843 ~ L845 ·. As shown in FIG. 3, the second epitaxial layer of gallium arsenide / the first epitaxial layer of gallium arsenide / the first buffer layer of gallium arsenide / the silicon substrate 30 includes a silicon substrate 3 and a first buffer layer 32 of gallium arsenide. A gallium arsenide first epitaxial layer 33 and a gallium arsenide second epitaxial M260000 layer 34. The preparation method of the second gallium arsenide layer / the first gallium arsenide layer / the first gallium arsenide buffer layer / the silicon substrate 3.0 is also a method of organometallic chemical vapor deposition. A deposition process is performed, wherein the temperature of the deposition process is 400 ° C, and the thickness of the gallium arsenide first buffer layer 32 formed after the deposition is less than 200 nm. The worm crystal manufacturing process of the first gallium arsenide epitaxial layer 33 is continued, wherein the temperature of the worm crystal manufacturing process is 700C, and the thickness of the first gallium arsenide first epitaxial layer 33 is 1 # m. At this time, followed by a temperature cycle annealing heat treatment procedure, the temperature of the epitaxial wafer in the organometallic chemical vapor deposition system is first reduced to room temperature. After reaching this temperature, the epitaxial wafer is heated to 850 ° C, and at 850 ° C is maintained for 5 minutes, and then the temperature is lowered to 700 ° C, and the epitaxial growth of the second epitaxial layer 34 of gallium arsenide is performed. This is a temperature cycle epitaxial process. After the crystal process, the heat treatment and the epitaxial growth process of the second parasitic crystal layer 34 are completed simultaneously, and the thickness of the second epitaxial layer 34 of gallium arsenide is 3 to 4 // m.
Itoh等人論文係利用一個砷化鎵第一緩衝層32、一 個砷化鎵第一磊晶層33及同時進行溫度循環退火熱處理 與磊晶製程的方式來降低貫穿式差排的產生，進而得到 一坤化鎵第二蟲晶層34，以改善石申化錄在石夕基板31上的 磊晶品質。依據Itoh等人的實驗結果顯示，在經過三個 至十三個溫度循環磊晶程序後，砷化鎵第二磊晶層34的 雙晶X-射線搖擺曲線量測呈現半高波寬值為 130arcsec。因此Itoh等人所採用的方法確實可改進石申 M260000 化鎵的磊晶品質，但是此種方法將熱處理與磊晶製程混 合在一起，增加了製程的複雜性，並且由雙晶X-射線搖 擺曲線量測結果來看，砷化鎵第二磊晶層34的品質仍有 相當大的改善空間。 圖4係習知之砷化鎵再成長（re-growth)第二磊晶 層/砷化鎵第一磊晶層/砷化鎵第二緩衝層/矽第一緩 衝層/石夕基板40之剖面示意圖，揭示於日本期刊M· S. Hao et al. , “Photoluminescence spectrum study of the GaAs/Si epilayer grown by using a thin amorphous Si film as buffer layer，’’ Japanese Journal Applied Physics ν〇1·34，Νο·7Β，1995 pp.L900 〜L902.(以下 稱Hao等人論文）。如圖4所示，砷化鎵再成長第二磊晶 層/坤化鎵第一磊晶層/砷化鎵第二緩衝層/矽第一緩 衝層/矽基板40包含一矽基板4卜一矽第一缓衝層42、 —砷化鎵第二緩衝層43、一砷化鎵第一磊晶層44、一砷 化鎵再成長第二磊晶層45。該砷化鎵再成長第二磊晶層 /砷化鎵第一磊晶層/砷化鎵第二緩衝層/矽第一緩衝 層/矽基板40之製備方法亦係採用有機金屬化學氣相沉 積法，首先對矽基板41進行一沉積製程，其中沉積製程 之溫度為600°C，沉積後形成具有非晶系（amorphous) 結構的矽第一緩衝層42，厚度為15A。接續進行砷化鎵 第二緩衝層43的沉積製程，其中沉積製程之溫度為400 °C ’沉積後形成砷化鎵第二緩衝層43的厚度為180A。 M260000 緊接著進仃-蟲晶製程，其中蟲晶製程之溫度為糊。。， 遙晶後形成砷化鎵第一磊晶層44的厚度為2 2//m。此時 將磊晶片取出，應用另一磊晶程序進行再成長製程，將 砷化鎵再成長第二磊晶層45磊晶於砷化鎵第一磊晶層44 上’至於該再磊晶製程所使用的溫度與磊晶層的厚度在 Hao等人論文中均未敘述。The thesis of Itoh et al. Used a gallium arsenide first buffer layer 32, a gallium arsenide first epitaxial layer 33, and simultaneous temperature cycle annealing heat treatment and epitaxial process to reduce the generation of through-difference rows, and further obtained The second parasitic crystal layer 34 of gallium is used to improve the epitaxial quality of Shi Shenhua recorded on Shixi substrate 31. According to the experimental results of Itoh et al., After three to thirteen temperature cycle epitaxy procedures, the twin-crystal X-ray rocking curve measurement of the second epitaxial layer 34 of gallium arsenide shows a half-height wave width of 130 arcsec. . Therefore, the method used by Itoh et al. Can indeed improve the epitaxial quality of Shishen M260000 gallium carbide, but this method mixes heat treatment and epitaxial process, increases the complexity of the process, and is shaken by twin crystal X-rays. From the curve measurement results, there is still considerable room for improvement in the quality of the second epitaxial layer 34 of gallium arsenide. FIG. 4 is a cross-section of a conventional re-growth second epitaxial layer / gallium arsenide first epitaxial layer / gallium arsenide second buffer layer / silicon first buffer layer / shixi substrate 40 Schematic diagram, revealed in Japanese journal M.S. Hao et al., "Photoluminescence spectrum study of the GaAs / Si epilayer grown by using a thin amorphous Si film as buffer layer," Japanese Journal Applied Physics ν〇1 · 34, NO 7B, 1995 pp. L900 to L902. (Hereinafter referred to as the paper by Hao et al.) As shown in Fig. 4, GaAs grows a second epitaxial layer / Kunhua first epitaxial layer / GaAs second The buffer layer / silicon first buffer layer / silicon substrate 40 includes a silicon substrate, a silicon first buffer layer 42, a gallium arsenide second buffer layer 43, a gallium arsenide first epitaxial layer 44, and an arsenic. GaAs grows second epitaxial layer 45. This GaAs grows second epitaxial layer / GaAs first epitaxial layer / GaAs second buffer layer / Si first buffer layer / Si substrate 40 The preparation method also uses an organometallic chemical vapor deposition method. First, a deposition process is performed on the silicon substrate 41, and the temperature of the deposition process is 600 ° C. After deposition, a silicon first buffer layer 42 having an amorphous structure is formed with a thickness of 15 A. The deposition process of the second gallium arsenide buffer layer 43 is continued, wherein the temperature of the deposition process is 400 ° C. The thickness of the second gallium arsenide buffer layer 43 is 180 A. The M260000 is immediately followed by the maggot-worm crystal process, wherein the temperature of the worm crystal process is paste. 2 2 // m. At this time, the epitaxial wafer is taken out, and another epitaxial process is used to perform the re-growth process, and the second epitaxial layer 45 is epitaxially grown on the first epitaxial layer 44 of gallium arsenide. The temperature and thickness of the epitaxial layer used in the re-epitaxial process are not described in the paper by Hao et al.
Hao等人論文係利用一個矽第一緩衝層42、一個砷 化鎵第二緩衝層43、一個砷化鎵第一磊晶層44及一個再 磊晶製程的砷化鎵再成長第二磊晶層45來降低貫穿式差 排的產生，以改善砷化鎵在矽基板41上的磊晶品質。依 據Hao等人的實驗結果顯示，砷化鎵第一磊晶層44的雙 晶X-射線搖擺曲線量測呈現半高波寬值為160arcsec， 而再蠢晶製程坤化錄再成長第二蟲晶層45的半高波寬值 為118arcsec。因此Hao等人論文中所揭示的磊晶品質較 11oh等人的實驗結果為佳。但是此種方法需進行一次再 磊晶製程，同樣亦增加了整個製程的複雜性，並且磊晶 鲁 片易於受到污染，從而影響整個製程的良品率（yield)。 【新型内容】 本創作之主要目的係提供化合物半導體磊晶片。為 達到上述的目的，本創作提供之化合物半導體磊晶片架 構包含一矽基板、一設置於該矽基板上之矽第一緩衝 層、一設置於該矽第一缓衝層上之化合物半導體第二緩 12 M260000 衝=U設置於該化合物半導體第二緩衝層上之化合物 半‘體第-磊晶層、以及一設置於該化合物半導體第一 磊晶層上之化合物半導體第二磊晶層。 本創作之在石夕基板上形成化合物半導體蟲晶片首先 於-石夕基板上進行-沉積製程，將—層非㈣薄膜沉積 於该矽基板上形成矽第一緩衝層’接著在矽第一緩衝層 上採=較低的長晶溫度進行沉積製程，將—層化合物半 導體薄膜沉積於該咬第—緩衝層上，形成化合物半導體 第二緩衝層’接著在化合物半導體第二緩衝層上採用一 般的長晶溫度進㈣晶製程，將—層化合物半導體薄膜 蟲晶於該化合物半導體第二緩衝層上，形成化合物半導 晶層’緊接著於長晶系統内直接進行溫度循環 以火…處理程序，以降低貫穿式差排的產生 晶 f物半導趙第-蟲晶層上採用-般的長晶溫度進行蟲 指，將―層化合物半導體薄麻晶於該化合物半導體 第-蟲晶層上，形成化合物半導體第二^層，然後再 =行:次溫度循環退火熱處理程序，以消”基板與化 δ物半導體第二磊晶層之間的應力。 相較於習知技藝本創作具有以下的優點： 晶 1. 本創作的整個蟲晶與熱處理製程是在同一個長 晶系統内完成，無須移出原先系統再進行一欠石、 製程，降低製程的繁複性，並減少遭受污染的: 2. 本創作應时第-緩衝層及化合 曰_ 13 M260000 緩衝層共同做為矽基板與化合物半導體磊晶層之間 的緩衝物，如此在進行熱處理時，可藉由矽第一緩 衝層及化合物半導體第二緩衝層共同作用使貫穿式 差排的產生機會降低，進而得到較佳品質的化合物 半導體蠢晶層。 3.本創作採用兩次溫度循環退火熱處理程序，如此 可更有效的發揮矽第一緩衝層及化合物半導體第二 緩衝層之功能，達到改善化合物半導體磊晶層品質 的目的。 本創作所製作的化合物半導體磊晶層經過雙晶X-射 線搖擺曲線量測後，其半高波寬值可降至105arcsec，相 較於Takano等人的實驗結果140arcsec、Itoh等人的實 驗結果130arcsec及Hao等人的實驗結果118arcsec等， 本創作所製作的化合物半導體磊晶層具有較佳的晶體品 質。 ， 【實施方式】 圖5至圖7係本創作實施例化合物半導體磊晶片50 之製備示意圖。如圖5所示，本實施例採用有機金屬化 學氣相沉積法首先在一矽基板51上進行一沉積製程，以 矽烷（SiH4)為反應氣體，沉積溫度為580°C，在矽基板 51上形成一層厚度為10〜25A的非晶砍薄膜，以做為矽 第一緩衝層52。然後在矽第一緩衝層52上進行沉積製 14 M260000 長’，用三甲基鎵（Ga (CH3) 3)與三氫化神（AsH3)為 反應氣體在/Jtt度3 9 0 C狀況下沉積一層砂化鎵材質的化 合物半導體第二緩衝層53,厚度約為〗〇〇A。接續在化合 物半導體第二緩衝層53上進行蟲晶製程，同樣採用三τ 基鎵與三氫化砷為反應氣體，在溫度71〇艽狀況下磊晶一 層坤化鎵材質的化合物半導體第—蟲晶層54，厚度約為 1. 8# in。然後在長晶系統内進行第一次的溫度循環退火 熱處理，如圖6所示，首先將系統溫度降至鮮c，維持 約7分鐘’接著提高系統溫度至，維持約5分鐘， 如此經過4〜8次高低溫循環退火程序，降低化合物半導 體第-蠢晶層54内的貫穿式⑽產生的機會。 俟完成第一次的溫度循環退火熱處理後，將長晶系 統的溫度降至7HTC並進行蟲晶製程。.如圖7所示，應用 二甲基鎵與三氫化砷為反應氣體在化合物半導體第一磊 曰曰層54上進仃蠢晶製作’羞晶一層石申化錄材質的化合物 半導體第二蟲晶層55,厚度約為丨.^。然後在長晶系 統内進行第二次的溫度循環退火熱處理，亦如圖6所示， 百先將系統溫度降至200t：，維持約7分鐘， 統溫度至刚。〇;’維持約5分鐘，如此經過4〜8次：;手氏 溫循環退火程序’再次藉由熱處理來降低化合物^體 苐二磊晶層55内的貫穿式差排產生的機會。 請參考圖7，本_切基板51上成長—層一 緩衝層52，接續㈣第—緩衝層51上成長—層化合物半 15 M260000 導體第二緩衝層53,再於化合物半導體第二緩衝層53上 成長一層化合物半導體第一磊晶層54,然後施以熱處 理，接著於化合物半導體第一磊晶層54上成長一層化合 物半導體第二磊晶層55，然後再施以一次熱處理，由此 可以得到良好晶體品質的化合物半導體磊晶片50。該長 晶製程為一有機金屬氣相沈積製程。而形成之化合物半 導體第二緩衝層53、化合物半導體第一磊晶層54及化合 物半導體第二磊晶層55亦可為砷化鋁（AlAs)、磷化鎵、 砷化銦（InAs)、磷化銦等三-五族化合物半導體二元材 料或由其組成之三元或四元材料。 本創作製備之化合物半導體磊晶片50包含一矽基板 51、一設置於該矽基板51上之矽第一緩衝層52、一設置 於該矽第一緩衝層52上之化合物半導體第二緩衝層53、 一設置於該化合物半導體第二緩衝層53上之化合物半導 體第一磊晶層54、以及一設置於該化合物半導體第一磊 晶層54上之化合物半導體第二磊晶層55。該矽第一缓衝 鲁 層52、化合物半導體第二緩衝層53係用以使貫穿式差排 在緩衝層内相互結合，達到降低貫穿式差排密度的目 的。而化合物半導體第一磊晶層54則是用以提供化合物 半導體第二磊晶層55成長所需的單晶結構。 圖8係本創作化合物半導體磊晶片50之雙晶X-射線 搖擺曲線量測圖，圖中顯示砷化鎵材質的化合物半導體 磊晶層之半高波寬值為105arcsec。將此結果與Takano 16 M260000 等人的實驗結果140arcsec、Itoh等人的實驗結果 130arcsec及Hao等人的實驗結果i18arcsec比較，可證 明本創作確實可以改善化合物半導體在矽基板上的磊晶 品質。 圖9係本創作第一實施例之太陽電池磊晶片6〇之剖 面示意圖，如圖9所示，太陽電池磊晶片6〇係於本創作 化5物半導體蟲晶片50上蠢晶一層背面場（back side f i e 1 d )從日日層61，然後依序遙晶一層基極層（base 1 ayer ) 62層射極層（emi tter layer)63、一層光窗層（window鲁 layer) 64及一層接觸層（contact layer) 65形成太陽 電池結構。 惟以上所述者’僅為本創作之較佳實施例而已，當 不能以此限定本創作實施之範圍；故，凡依本創作申請 專利範圍及創作說明書内容所作之簡單的等效變化與修 飾’皆應仍屬本創作專利涵蓋之範圍内。 【圖式簡單說明】 圖1係習知之化合物半導體磊晶片（’219專利）之剖面 示意圖。 圖2係習知之化合物半導體磊晶片（Takan〇等人論文） 之剖面示意圖。 圖3係習知之化合物半導體磊晶片（It〇h等人論文）之 剖面示意圖。 17 M260000 圖4係習知之化合物半導體磊晶片（Ha〇等人論文）之剖 面示意圖。 圖5至圖7係本創作化合物半導體磊晶片之製備示意圖。 圖8係本創作化合物半導體磊晶片5〇之雙晶χ—射線搖擺 曲線量測圖。 圖9係本創作第一實施例之太陽電池磊晶片剖面示意圖。 【元件標號對照】 10化合物半導體磊晶片 11矽基板 12砷化鎵第一緩衝層 13砷化鎵第一磊晶層 14砷化鎵第二緩衝層 15砷化鎵第二磊晶層 20化合物半導體磊晶片 21發基板 2 2珅化鎵第一緩衝層 23砷化鎵第一磊晶層 24砷化銦鎵第二緩衝層 25砷化鎵第二磊晶層 30化合物半導體磊晶片 31妙基板 32砷化鎵第一緩衝層 33砷化鎵第一磊晶層 34坤化鎵第二磊晶層 40化合物半導體磊晶片 41矽基板 4 2碎第一緩衝層 43砷化鎵第二緩衝層 44 珅化鎵第一磊晶層 45钟化鎵再成長第二磊 晶層 51矽基板 50化合物半導體磊晶片 M260000 52矽第一缓衝層 54化合物半導體第一磊晶 層 6 0太陽電池 62基極層 64光窗層 53化合物半導體第一緩 衝層 55化合物半導體第二磊晶 層 61背面場層 6 3射極層 65接觸層The paper by Hao et al. Used a silicon first buffer layer 42, a gallium arsenide second buffer layer 43, a gallium arsenide first epitaxial layer 44 and a re-epitaxial gallium arsenide to grow a second epitaxial layer. Layer 45 to reduce the generation of through-difference rows to improve the epitaxial quality of gallium arsenide on the silicon substrate 41. According to the experimental results of Hao et al., The measurement of the twin-crystal X-ray rocking curve of the first epitaxial layer 44 of gallium arsenide shows a half-height wave width of 160 arccsec. The full width at half maximum of layer 45 is 118 arcsec. Therefore, the epitaxial quality revealed in the paper by Hao et al. Is better than the experimental results of 11oh et al. However, this method requires a re-epitaxial process, which also increases the complexity of the entire process, and the epitaxial wafers are easily contaminated, which affects the yield of the entire process. [New content] The main purpose of this creation is to provide compound semiconductor wafers. In order to achieve the above-mentioned object, the compound semiconductor chip structure provided by this creation includes a silicon substrate, a silicon first buffer layer disposed on the silicon substrate, and a compound semiconductor second layer disposed on the silicon first buffer layer. 12 M260000 Impact = U A compound semi- 'epitaxial layer disposed on the second buffer layer of the compound semiconductor, and a second epitaxial layer of the compound semiconductor disposed on the first epitaxial layer of the compound semiconductor. In this creation, a compound semiconductor worm wafer is formed on a Shi Xi substrate. First, a -deposition process is performed on the Shi Xi substrate. A non-thin film is deposited on the silicon substrate to form a silicon first buffer layer. Then, a silicon first buffer layer is formed. The layer is deposited at a lower growth temperature to deposit a layer of compound semiconductor thin film on the first buffer layer to form a second compound semiconductor buffer layer. Then the general buffer layer is used on the second buffer semiconductor layer. The crystal growth temperature enters the crystal process, and a layer of compound semiconductor thin film worm crystals is formed on the second buffer layer of the compound semiconductor to form a compound semiconducting crystal layer. Then, a temperature cycle is directly performed in the crystal growth system. In order to reduce the formation of the through-differential row, the semiconducting Zhao Di-worm crystal layer uses a normal crystal growth temperature for the insect fingers, and a thin layer of compound semiconductor thin hemp crystals is deposited on the compound semiconductor first insect layer. Form a second semiconductor compound layer, and then again: Row: sub-temperature cycle annealing heat treatment process to eliminate the "between the substrate and the second epitaxial layer of the chemical semiconductor" Compared with the known techniques, this creation has the following advantages: Crystal 1. The entire worm crystal and heat treatment process of this creation is completed in the same crystal growth system, there is no need to remove the original system and perform an under-stone, manufacturing process to reduce the manufacturing process. Complexity and reduce pollution: 2. This creation should be the first buffer layer and chemical compound _ 13 M260000 The buffer layer is used as a buffer between the silicon substrate and the epitaxial layer of the compound semiconductor. The first buffer layer of silicon and the second buffer layer of compound semiconductor can work together to reduce the chance of generating the through-difference row, and then obtain a better-quality compound semiconductor stupid crystal layer. 3. This creation uses two temperature cycle annealing Heat treatment process, so that the functions of the first buffer layer of silicon and the second buffer layer of compound semiconductor can be more effectively used, and the purpose of improving the quality of the compound semiconductor epitaxial layer is achieved. The compound semiconductor epitaxial layer produced by this creation undergoes twin X- After the measurement of the ray rocking curve, its half-height wave width value can be reduced to 105 arcsec, compared with the experimental results of Takano et al. 140 arccsec, I The experimental results of 130hcsec by Toh et al. and 118arcsec by Hao et al. The compound semiconductor epitaxial layer produced in this work has better crystal quality. [Embodiments] Figures 5 to 7 are compounds of the present creative example. A schematic diagram of the preparation of a semiconductor wafer 50. As shown in FIG. 5, in this embodiment, an organic metal chemical vapor deposition method is used to first perform a deposition process on a silicon substrate 51, using silane (SiH4) as a reaction gas, and a deposition temperature of 580. ° C, an amorphous thin film with a thickness of 10 ~ 25A is formed on the silicon substrate 51 as the first silicon buffer layer 52. Then, a 14 M260000 long film is deposited on the first silicon buffer layer 52. Methyl gallium (Ga (CH3) 3) and trihydrogen (AsH3) are reacted gases to deposit a layer of a sanded gallium-based compound semiconductor buffer layer 53 at a temperature of / Jtt degree 3 9 0 C, and the thickness is about 〖〇. 〇A. Subsequent to the worm crystal process on the second buffer layer 53 of the compound semiconductor, tri-tallium-based gallium and arsenic trihydrogen are also used as the reaction gas, and a layer of gallium-based compound semiconductor first worm crystal is epitaxially formed at a temperature of 71 ° C. 8 # in。 Layer 54, a thickness of about 1. 8 # in. Then the first temperature cycle annealing heat treatment is performed in the crystal growth system. As shown in FIG. 6, the system temperature is first reduced to fresh c and maintained for about 7 minutes. Then the system temperature is increased to and maintained for about 5 minutes. ~ 8 high and low temperature cycle annealing procedures to reduce the chance of the generation of the piercing thallium in the compound semiconductor first-crystallized layer 54.俟 After the first temperature cycle annealing heat treatment is completed, the temperature of the growth system is reduced to 7HTC and the worm crystal process is performed. As shown in Fig. 7, using dimethylgallium and arsenic trihydride as reaction gases, the first semiconductor layer 54 on the compound semiconductor is made of stupid crystals to produce a second layer of compound semiconductor that is made of stone. The crystal layer 55 has a thickness of about 丨. ^. Then, a second temperature cycle annealing heat treatment is performed in the crystal growth system. As shown in FIG. 6, Baixian reduced the temperature of the system to 200t :, and maintained it for about 7 minutes, and the system temperature was as high as just. 〇 ', maintained for about 5 minutes, so 4 to 8 times :; the hand temperature cycle annealing process' once again to reduce the chance of the generation of the through-difference in the compound 体 bulk epitaxial layer 55 by heat treatment. Please refer to FIG. 7, a layer-buffer layer 52 is grown on the substrate 51, and a layer-compound layer 15 is grown on the first-buffer layer 51-a compound half 15 M260000 is a conductor second buffer layer 53, and then a compound semiconductor second buffer layer 53 A layer of the first compound semiconductor epitaxial layer 54 is grown thereon, and then subjected to heat treatment, and then a layer of the second compound semiconductor epitaxial layer 55 is grown on the first compound semiconductor epitaxial layer 54 and then subjected to a heat treatment, thereby obtaining Compound semiconductor epitaxial wafer 50 with good crystal quality. The crystal growth process is an organic metal vapor deposition process. The formed compound semiconductor second buffer layer 53, the compound semiconductor first epitaxial layer 54 and the compound semiconductor second epitaxial layer 55 may also be aluminum arsenide (AlAs), gallium phosphide, indium arsenide (InAs), phosphorus Group III-V compound semiconductor binary materials such as indium halide or ternary or quaternary materials composed of them. The compound semiconductor wafer 50 prepared in this work includes a silicon substrate 51, a silicon first buffer layer 52 disposed on the silicon substrate 51, and a compound semiconductor second buffer layer 53 disposed on the silicon first buffer layer 52. A compound semiconductor first epitaxial layer 54 disposed on the compound semiconductor second buffer layer 53 and a compound semiconductor second epitaxial layer 55 disposed on the compound semiconductor first epitaxial layer 54. The silicon first buffer layer 52 and the compound semiconductor second buffer layer 53 are used to combine the through-difference row in the buffer layer to achieve the purpose of reducing the through-difference row density. The first compound semiconductor epitaxial layer 54 is used to provide a single crystal structure required for the growth of the second compound semiconductor epitaxial layer 55. Fig. 8 is a measurement chart of the twin crystal X-ray rocking curve of the original compound semiconductor epitaxial wafer 50. The figure shows that the gallium arsenide compound semiconductor epitaxial layer has a half-height wave width of 105 arcsec. Comparing this result with the experimental result of 140 arccsec by Takano 16 M260000 et al., 130arcsec by Itoh et al., And i18arcsec by Hao et al., It can be proved that this creation can indeed improve the epitaxial quality of compound semiconductors on silicon substrates. FIG. 9 is a schematic cross-sectional view of a solar cell epitaxial wafer 60 according to the first embodiment of the present invention. As shown in FIG. back side fie 1 d) from the day-to-day layer 61, and then remotely crystallize a base 1 ayer 62 base emi tter layer 63, a window layer 64 and a layer A contact layer 65 forms a solar cell structure. However, the above-mentioned one is only a preferred embodiment of this creation, and it cannot be used to limit the scope of implementation of this creation; therefore, any simple equivalent changes and modifications made in accordance with the scope of the patent application for this creation and the content of the creation manual 'All should still fall within the scope of this creation patent. [Brief Description of the Drawings] FIG. 1 is a schematic cross-sectional view of a conventional compound semiconductor epitaxial wafer (the '219 patent). FIG. 2 is a schematic cross-sectional view of a conventional compound semiconductor epitaxial wafer (Takan0 et al. Paper). FIG. 3 is a schematic cross-sectional view of a conventional compound semiconductor wafer (Itoh et al. Paper). 17 M260000 Figure 4 is a schematic cross-sectional view of a conventional compound semiconductor epitaxial wafer (Hao et al.). FIG. 5 to FIG. 7 are schematic diagrams of the preparation of the inventive compound semiconductor epitaxial wafer. Fig. 8 is a measurement chart of the twin χ-ray swing curve of the original compound semiconductor epitaxial wafer 50. 9 is a schematic cross-sectional view of a solar cell wafer according to the first embodiment of the present invention. [Element number comparison] 10 Compound semiconductor epitaxial wafer 11 Silicon substrate 12 GaAs first buffer layer 13 GaAs first epitaxial layer 14 GaAs second buffer layer 15 GaAs second epitaxial layer 20 Compound semiconductor Epitaxial wafer 21 hair substrate 2 2 GaAs first buffer layer 23 GaAs first epitaxial layer 24 Indium gallium arsenide second buffer layer 25 GaAs second epitaxial layer 30 Compound semiconductor epitaxial wafer 31 Substrate 32 The first gallium arsenide buffer layer 33 The first gallium arsenide layer 34 The second gallium oxide layer 40 The compound semiconductor epitaxial wafer 41 The silicon substrate 4 The first buffer layer 43 The second gallium arsenide buffer layer 44 珅The first epitaxial layer of gallium 45 The second epitaxial layer of gallium is grown 51 The silicon substrate 50 The compound semiconductor epitaxial wafer M260000 52 The first buffer layer of silicon 54 The first epitaxial layer of compound 60 60 The base layer of solar cell 62 64 light window layer 53 compound semiconductor first buffer layer 55 compound semiconductor second epitaxial layer 61 back field layer 6 3 emitter layer 65 contact layer
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