JPH0760790B2 - Compound semiconductor substrate - Google Patents
Compound semiconductor substrateInfo
- Publication number
- JPH0760790B2 JPH0760790B2 JP62169162A JP16916287A JPH0760790B2 JP H0760790 B2 JPH0760790 B2 JP H0760790B2 JP 62169162 A JP62169162 A JP 62169162A JP 16916287 A JP16916287 A JP 16916287A JP H0760790 B2 JPH0760790 B2 JP H0760790B2
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- JP
- Japan
- Prior art keywords
- layer
- inp
- gaas
- substrate
- compound semiconductor
- Prior art date
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Description
【発明の詳細な説明】 ＜産業上の利用分野＞ 本発明はSiやGeのようなIV族半導体基板上にIII−Ｖ族
化合物半導体層を形成してなる化合物半導体基板の改良
に関するものである。The present invention relates to an improvement of a compound semiconductor substrate formed by forming a III-V group compound semiconductor layer on a IV group semiconductor substrate such as Si or Ge. .
＜従来の技術＞ 近年、化合物半導体の薄膜結晶成長技術の発展は著し
く、半導体レーザー、太陽電池や２次元電子ガスを利用
した超高速デバイスなど様々な特徴デバイスが作製され
ている。しかしながら、これらのデバイスは基板にIII
−Ｖ族半導体基板を用いているため、非常に高価なもの
となり、また結晶成長の困難さから大面積化を狙うこと
も困難である。そこで、安価で結晶性が良く、大面積の
基板が得られるIV族半導体基板上にIII−Ｖ族化合物半
導体を形成する技術が注目され、特にSi基板上へのGaAs
の薄膜結晶成長技術に関する研究が盛んに行れるように
なった。<Prior Art> In recent years, the thin film crystal growth technology for compound semiconductors has made remarkable progress, and various characteristic devices such as semiconductor lasers, solar cells, and ultra-high speed devices using two-dimensional electron gas have been manufactured. However, these devices are
Since the -V semiconductor substrate is used, it becomes very expensive, and it is difficult to increase the area due to the difficulty of crystal growth. Therefore, a technique for forming a group III-V compound semiconductor on a group IV semiconductor substrate, which is inexpensive, has good crystallinity, and has a large area, has attracted attention.
The research on the thin film crystal growth technology has been actively conducted.
Si基板上にGaAs薄膜を成長させる従来技術としては、Ga
Asを最初低温で薄く成長させ、更に昇温してGaAsを厚く
成長させる２段階成長法（特公昭61−70715）、Si基板
とGaAsの中間層にGeを用いる方法（IEEEElectron devic
e Lett.EDL−2,169（1981））、GaAsと格子定数の近い
他のIII−Ｖ族系化合物半導体との交互層を中間層に用
いる方法（特公昭60−12724）中間層に歪超格子を用い
る方法（J.App.Phys.57,4578（1985））等が提案され、
FETや発光ダイオード、半導体レーザー等が試作されて
いる。A conventional technique for growing a GaAs thin film on a Si substrate is Ga.
A two-step growth method in which As is first grown thin at low temperature and then GaAs is grown thicker by further heating (Japanese Patent Publication No. 61-70715), and a method of using Ge for the Si substrate and the intermediate layer of GaAs (IEEEElectron devic
E Lett.EDL-2,169 (1981)), a method of using an alternating layer of GaAs and another III-V group compound semiconductor having a close lattice constant as an intermediate layer (Japanese Patent Publication No. 60-12724). The method to be used (J.App.Phys. 57 , 4578 (1985)) etc. was proposed,
FETs, light emitting diodes, semiconductor lasers, etc. have been prototyped.
一方、GaAsに比べて電子のピーク速度及び飽和速度が大
きく、また熱伝導率も大きいIII−Ｖ族化合物半導体にI
nPがあり、GaAsより高い周波数で動作し、かつより高出
力のマイクロ波電力増幅素子が得られる可能性があると
して有望視されている。On the other hand, in III-V group compound semiconductors, which have a higher electron peak velocity and saturation velocity than GaAs, and a high thermal conductivity,
It has nP, operates at a higher frequency than GaAs, and is considered to be promising as a possibility to obtain a higher power microwave power amplification device.
＜発明が解決しようとする問題点＞ しかしながらInP基板は、GaAsより一層高価であるとと
もに大口径のものが得られず、市販の基板の結晶品質と
しても欠陥密度が104cm2程度のものしか得られていな
い。これらの欠点を克服するために、InPについてもSi
基板上に結晶成長させる研究が進展しつゝある。しかし
ながら数件の報告があるのものの結晶品質はまだ十分な
ものとは言えず、これをデバイスにまで応用した例は少
ない。SiとInPとの格子定数差は8.1％と、SiとGaAsの格
子定数差の約２倍程度あること及びInPの解離圧が高い
ことから成長中にＰの離脱が起き易く表面モフォロジー
を悪化させるという問題があり、結晶品質向上を困難に
していた。特に上記した数件の報告は、所謂２段階成長
法により、InPをSi基板上に直接成長させたものなどが
含まれているが、いずれも大きな格子不整や応力の影響
を緩和することが出来ず、結晶品質の低下を招いてい
た。<Problems to be Solved by the Invention> However, InP substrates are more expensive than GaAs, and large-diameter substrates cannot be obtained, and the crystal density of commercially available substrates is only 10 4 cm 2. Not obtained. To overcome these drawbacks, InP is also used for Si.
Research on crystal growth on a substrate is progressing. However, although several reports have been made, the crystal quality is not yet sufficient, and there are few examples in which it was applied to devices. The lattice constant difference between Si and InP is 8.1%, which is about twice as large as the lattice constant difference between Si and GaAs, and the dissociation pressure of InP is high, so that P release easily occurs during growth and the surface morphology is deteriorated. Therefore, it has been difficult to improve the crystal quality. In particular, the above-mentioned several reports include those in which InP is directly grown on a Si substrate by the so-called two-step growth method, but all of them can alleviate the effects of large lattice imperfections and stress. However, the crystal quality was deteriorated.
本発明は上記の点に鑑みて創案されたものであり、IV族
半導体基板（特にSi等）上にInPのようなVI族半導体と
格子不整の大きいIII−Ｖ族化合物半導体を形成した基
板において、表面モフォロジーや結晶性の優れたシング
ルドメインなIII−Ｖ族化合物半導体層が得られる構造
の化合物半導体基板を提供することを目的としている。The present invention has been made in view of the above points, and in a substrate in which a group VI semiconductor such as InP and a group III-V compound semiconductor having a large lattice mismatch are formed on a group IV semiconductor substrate (particularly Si). An object of the present invention is to provide a compound semiconductor substrate having a structure in which a single domain III-V group compound semiconductor layer having excellent surface morphology and crystallinity can be obtained.
＜問題点を解決するための手段及び作用＞ 上記の目的を達成するため、本発明の化合物半導体基板
は、Si基板と、 該Si基板上に形成された中間層としてのGaAs層と、 該中間層に形成されたシングルドメインなInP単結晶層
と、 を備え、 上記Si、GaAs及びInPのそれぞれの熱膨張係数の関係
が、 GaAs＞InP＞Siとなるように構成している。この場合、S
i基板上のGaAsは従来技術により成長されるが、SiとGaA
sの熱膨張係数差（Si＜GaAs）の関係から、GsAs層は引
っ張り熱圧力を受けている。更にGaAs層上のInP層は、S
i,GaAs,InPの熱膨張係数の大小関係がGaAs＞InP＞Siな
ので、Si基板からは引っ張り熱応力を受けるが、GaAs層
からは逆に圧縮熱圧力を受けることになる。従って、適
当なGaAs中間層厚さや成長条件を選ぶことによって成長
を目的とするIII−Ｖ族化合物半導体層の熱圧力を緩和
することができる。このようにSi基板上にInPを形成さ
せる場合、中間層にGaAsを用いることにより、格子不整
を緩和できるとともに熱圧力も緩和できるという２つの
効果があり、平坦性、結晶性の優れたInP基板が得られ
る。また、この化合物半導体基板はSiを基体として用い
ているため大口径のものが安価で得られると共に、機械
的強度、熱伝導率などにおいも従来のInP基板を大幅に
しのぐ、高品質基板が得られることになる。<Means and Actions for Solving Problems> In order to achieve the above object, a compound semiconductor substrate of the present invention includes a Si substrate, a GaAs layer as an intermediate layer formed on the Si substrate, and the intermediate layer. And a single-domain InP single crystal layer formed in the layer, and the thermal expansion coefficients of Si, GaAs, and InP are set to be GaAs>InP> Si. In this case, S
GaAs on i substrate is grown by conventional technology, but Si and GaA
Due to the difference in the coefficient of thermal expansion of s (Si <GaAs), the GsAs layer is subjected to tensile thermal pressure. Furthermore, the InP layer on the GaAs layer is S
Since the magnitude relationship of the thermal expansion coefficients of i, GaAs, and InP is GaAs>InP> Si, tensile thermal stress is applied from the Si substrate, but compressive thermal pressure is applied from the GaAs layer. Therefore, the thermal pressure of the III-V group compound semiconductor layer for growth can be relaxed by selecting an appropriate GaAs intermediate layer thickness and growth conditions. In this way, when InP is formed on the Si substrate, the use of GaAs for the intermediate layer has two effects that the lattice misalignment can be relaxed and the thermal pressure can be relaxed, and the InP substrate has excellent flatness and crystallinity. Is obtained. In addition, since this compound semiconductor substrate uses Si as the base material, a large diameter one can be obtained at low cost, and a high-quality substrate that has mechanical strength and thermal conductivity that far surpass the conventional InP substrate can be obtained. Will be done.
＜実施例＞ 以下、図面を参照しながら、本発明に係る実施例を詳細
に説明する。<Example> Hereinafter, an example according to the present invention will be described in detail with reference to the drawings.
第１図は本発明に係る化合物半導体基板の構造断面図で
ある。第１図において、１はIV族半導体基板、２は中間
層としての第１のIII−Ｖ族化合物半導体層、３は成長
を目的とする第２のIII−Ｖ族化合物半導体層であり、I
V族半導体基板１にSi、中間層のIII−Ｖ族化合物半導体
層２にGaAs、IV族半導体基板１と格子不整の大きい成長
を目的とするIII−Ｖ族化合物半導体層３にInPを用いた
例を示している。本発明に係る一実施例としての化合物
半導体基板は、まず最初にSi基板１上にMOCVD法やMBE
法、クロライド−ハライド系VPE法等により、単一ドメ
インのGaAs層２を0.02〜1.0μｍの範囲の膜厚で形成
し、しかる後に同一チャンバー内で連続的に目的とする
InP層３を0.5〜10μｍの範囲の膜厚で形成してなる。よ
り具体的には、MOCVD装置により減圧成長（例えば75Tor
r）で各化合物半導体層を形成した。FIG. 1 is a structural sectional view of a compound semiconductor substrate according to the present invention. In FIG. 1, 1 is a IV group semiconductor substrate, 2 is a first III-V group compound semiconductor layer as an intermediate layer, 3 is a second III-V group compound semiconductor layer for the purpose of growth, and I
Si was used for the group V semiconductor substrate 1, GaAs was used for the intermediate III-V compound semiconductor layer 2, and InP was used for the group IV semiconductor substrate 1 and the group III-V compound semiconductor layer 3 for the purpose of growth with large lattice mismatch. An example is shown. A compound semiconductor substrate according to an embodiment of the present invention is formed on a Si substrate 1 by MOCVD or MBE.
Method, chloride-halide-based VPE method, etc., to form a single domain GaAs layer 2 with a film thickness in the range of 0.02 to 1.0 μm, and then successively aim in the same chamber.
The InP layer 3 is formed with a film thickness in the range of 0.5 to 10 μm. More specifically, MOCVD equipment is used to grow under reduced pressure (for example, 75 Tor
Each compound semiconductor layer was formed in step r).
まず、（100）Si基板１の表面にHFエッチング処理を行
なった後、成長炉内でAsH3雰囲気下にて1000℃で10分間
の熱処理を行なった。次にトリエチルガリウム（TEG）
とアルシン（AsH3）（V/III比＝100）を用いて基板温度
400〜700℃の成長条件で中間層２としてGaAsを0.02〜1.
0μｍ成長させ、次いでトリメチルインジウム（TMI）と
ホスフィン（PH3）（V/IV比＝70〜200）を用いて基板温
度400〜650℃の成長条件でInP層３を0.5〜10μｍの範囲
の膜厚で成長させた。First, HF etching treatment was performed on the surface of the (100) Si substrate 1, and then heat treatment was performed at 1000 ° C. for 10 minutes in an AsH 3 atmosphere in a growth furnace. Then triethylgallium (TEG)
And arsine (AsH 3 ) (V / III ratio = 100)
Under the growth conditions of 400 to 700 ° C, 0.02 to 1.
0 μm growth, then trimethylindium (TMI) and phosphine (PH 3 ) (V / IV ratio = 70-200) were used to grow the InP layer 3 in the range of 0.5-10 μm under the growth conditions of substrate temperature 400-650 ° C. Grown thick.
この第１図に示した実施例の構造における各層材料の格
子定数はSiが5.431Å,GaAsが5.642Å,InPが5.868Åであ
り、基体であるSiと成長を目的とするIII−Ｖ族化合物
半導体であるInPとの格子定数のミスフィットが8.1％あ
る。従ってSi上に直接InPを成長させると表面が平坦な
膜が得られなかったり、転位が多数成長膜中に存在し結
晶性の良好なものが得られなかったりする。一方、GaAs
の格子定数はSiとInPの格子定数のほぼ中間にあり、Si
と4.1％InPと4.0％の格子定数差となる。また、SiとGaA
sならびにGaAsとInPは互いになじみが良く、GaAs層を中
間層に用いた場合、平坦性及び結晶性の優れたInP層が
得られた。The lattice constant of each layer material in the structure of the embodiment shown in FIG. 1 is 5.431Å for Si, 5.642Å for GaAs, and 5.868Å for InP, and the substrate is Si and a III-V group compound for growth. Misfit of lattice constant with InP which is a semiconductor is 8.1%. Therefore, when InP is grown directly on Si, a film having a flat surface cannot be obtained, or dislocations are present in a large number of grown films and a crystal having good crystallinity cannot be obtained. On the other hand, GaAs
Has a lattice constant approximately in the middle of the lattice constants of Si and InP.
And 4.1% InP and 4.0% lattice constant difference. Also, Si and GaA
s and GaAs and InP were well compatible with each other, and when the GaAs layer was used as the intermediate layer, an InP layer with excellent flatness and crystallinity was obtained.
第１表は各種ヘテロエピタキシャル成長膜のフォトルミ
ネッセンススペクトルにおけるInPからのバンド間遷移
発光ピークのInP基板のピーク値からのシフトを示した
ものである。Table 1 shows the shift of the band-to-band transition emission peak from InP in the photoluminescence spectra of various heteroepitaxial growth films from the peak value of the InP substrate.
本実施例に係るIII−Ｖ族化合物半導体基板の構造
（ａ）はSi基板上にGaAsを形成し、その上にInPを形成
しており、第１表に示した様に、Si基板上に直接成長さ
せたGaAs（ｂ）やInP膜（ｃ）は引っ張り応力を受けて
いるが、GaAs基板上のInP膜（ｄ）は逆に圧縮応力を受
けている。これらの膜の歪は主に熱的な応力によるもの
である。すなわちSi,GaAs,InPの熱膨張係数がそれぞれ
2.6×10-6/deg,4.5×10-6/degであり、Si上のGaAs
（ｂ）やInP（ｃ）膜は、GaAsやInPの熱膨張係数がSiの
熱膨張係数より大きいため引っ張り応力を受け、GaAs上
のInP膜（ｄ）は、InPの熱膨張係数がGaAsの熱膨張係数
より小さいため、圧縮応力を受けていると説明できる。
本実施例において、目的とするInP層３はSi基板１から
は引っ張り応力を受けているがGaAsの中間層２からは逆
に圧縮応力を受けており、中間層２のGaAsを0.1μｍ成
長させたとき、InP層３の引っ張り応力は、Si上に直接
成長したときの値σ＝1.8×109dyn/cm2より、半分以下
の値σ＝0.8×109dyn/cm2まで減少できた。従って、成
長条件や中間層厚の最適化を計ることにより、さらに応
力緩和することができる。また、本実施例に係る化合物
半導体基板は、Siを基体として用いているため大口径の
ものが安価で得られ、さらに化合物半導体基板はもろく
半導体装置製造プロセス中に割れるという問題も解決で
きる。 In the structure (a) of the III-V compound semiconductor substrate according to this example, GaAs is formed on the Si substrate and InP is formed on the GaAs, and as shown in Table 1, the Si substrate is formed on the Si substrate. The directly grown GaAs (b) and InP film (c) receive tensile stress, while the InP film (d) on the GaAs substrate receives compressive stress. The strain of these films is mainly due to thermal stress. That is, the thermal expansion coefficients of Si, GaAs, and InP are
2.6 × a 10 -6 /deg,4.5×10 -6 / deg, GaAs on Si
The (b) and InP (c) films are subjected to tensile stress because the thermal expansion coefficient of GaAs and InP is larger than that of Si, and the InP film (d) on GaAs has the InP thermal expansion coefficient of GaAs Since it is smaller than the coefficient of thermal expansion, it can be explained that it receives compressive stress.
In the present embodiment, the target InP layer 3 is subjected to tensile stress from the Si substrate 1 but is subjected to compressive stress from the intermediate layer 2 of GaAs, and GaAs of the intermediate layer 2 is grown to a thickness of 0.1 μm. At that time, the tensile stress of the InP layer 3 could be reduced from a value of σ = 1.8 × 10 9 dyn / cm 2 when directly grown on Si to a value of σ = 0.8 × 10 9 dyn / cm 2 or less. . Therefore, the stress can be further relaxed by optimizing the growth conditions and the thickness of the intermediate layer. Further, since the compound semiconductor substrate according to the present embodiment uses Si as a base, a large-diameter compound semiconductor substrate can be obtained at low cost, and the problem that the compound semiconductor substrate is fragile and cracks during the semiconductor device manufacturing process can be solved.
第２図は本発明の他の実施例における化合物半導体基板
の構造断面図を示す図であり、同図において１はSi基
板、４は中間層としての低温形成GaAs層、５は中間層と
してのGaAs層、６は低温形成InP層、７はInP層である。FIG. 2 is a diagram showing a structural cross-sectional view of a compound semiconductor substrate in another embodiment of the present invention. In FIG. 2, 1 is a Si substrate, 4 is a low temperature formed GaAs layer as an intermediate layer, and 5 is an intermediate layer. A GaAs layer, 6 is a low-temperature formed InP layer, and 7 is an InP layer.
上記第２図に示す構造を実現する一方向として減圧MOCV
D法を用いた。ここでは反応管内圧は100〜25Torrに減圧
して用いているが、大気圧においても形成は可能であ
る。Decompression MOCV is one way to realize the structure shown in Fig. 2 above.
The D method was used. Here, the pressure inside the reaction tube is reduced to 100 to 25 Torr, but it can be formed even at atmospheric pressure.
第３図は、上記第２図に示した構造の基板の形成手順を
成長温度の時間依存性により表わしたものである。FIG. 3 shows the procedure for forming the substrate having the structure shown in FIG. 2 by the time dependence of the growth temperature.
下地基板１としては、結晶成長に先立ちHF溶液中で洗浄
された４インチ形状のSi基板を用い、1000℃にて10分程
度AsH3雰囲気にて熱処理８を行なう。続いて、400℃に
降温し、低温形成GaAs中間層４を1000Å以下の層厚（10
0〜1000Å）にて形成後、600℃まで昇温し、GaAs中間層
５を500〜10000Åの層厚にて形成した。更に引き続き、
目的とするInP層の形成に於いても400℃にて1000Å以下
の層厚の低温形成InP層６の形成後、600℃にて必要とす
る層厚（0.5〜10μｍ）のInP層７の形成を行った。As the base substrate 1, a 4-inch Si substrate cleaned in an HF solution prior to crystal growth is used, and a heat treatment 8 is performed at 1000 ° C. for about 10 minutes in an AsH 3 atmosphere. Then, the temperature is lowered to 400 ° C., and the low temperature formed GaAs intermediate layer 4 is formed with a layer thickness (10
Then, the temperature was raised to 600 ° C. to form the GaAs intermediate layer 5 with a layer thickness of 500 to 10000Å. Further on,
Also in the formation of the target InP layer, the low-temperature formation of the InP layer 6 having a layer thickness of 1000 Å or less at 400 ° C. is followed by the formation of the InP layer 7 having the required layer thickness (0.5 to 10 μm) at 600 ° C. I went.
ここで用いた原料ガスの供給条件としてはGaAs層２形成
時には、トリエチルガリウム（TEG）とアルシン（As
H3）を用い、又、InP層３形成時には、トリメチルイン
ジウム（TMI）とホスフィン（PH3）を用いた。夫々の供
給量は、TEGでは2.5×10-5（モル分率）、TMIでは5.6×
10-5（モル分率）であり、AsH3とTEGの供給比は100,PH3
とTMIでは70〜200であり、本原料ガスをH2にて稀釈する
ことにより、反応管内総流量として、15/minとした。The source gas supply conditions used here are triethylgallium (TEG) and arsine (As) when the GaAs layer 2 is formed.
H 3 ) was used, and trimethylindium (TMI) and phosphine (PH 3 ) were used when the InP layer 3 was formed. The supply amount of each is 2.5 × 10 -5 (molar fraction) for TEG and 5.6 × for TMI.
10 -5 (molar fraction), and the supply ratio of AsH 3 and TEG is 100, PH 3
And TMI were 70 to 200, and the total flow rate in the reaction tube was set to 15 / min by diluting this raw material gas with H 2 .
結果として、本実施例に於ける全条件に於いて、４イン
チSin基板全面に亘り、鏡面な（平坦性の良好な）InP層
が得られ、その層厚分布としては、±10％以下という良
好な均一性を有したInP層７が得られた。又、光学顕微
鏡による観察より、約８μｍ層厚のInP層に於いてもク
ラックの発生は認められない。このことは、InP層の残
留応力が少ない結果に対応するものであり、比較的厚い
層厚を必要とするデバイス（例えばLED等）を形成する
には非常に有用である。更に、HBr＋H3PO4（臭化水素＋
リン酸）溶液によるエッチングパターン形状により、シ
ングルドメインなInP単結晶層が４インチSi基板全面に
於いて得られていることを確認した。As a result, under all the conditions in this example, a mirror-finished (good flatness) InP layer was obtained over the entire surface of the 4-inch Sin substrate, and the layer thickness distribution was ± 10% or less. The InP layer 7 having good uniformity was obtained. Further, the observation by an optical microscope shows that no crack is generated even in the InP layer having a thickness of about 8 μm. This corresponds to the result that the residual stress of the InP layer is small, and is very useful for forming a device (such as an LED) that requires a relatively large layer thickness. Furthermore, HBr + H 3 PO 4 (hydrogen bromide +
It was confirmed that a single domain InP single crystal layer was obtained on the entire surface of the 4-inch Si substrate by the etching pattern shape with the phosphoric acid) solution.
このように本実施例により、前述の低応力化に加え、平
坦性に優れた化合物半導体基板が４インチSi基板上に形
成が可能となった。As described above, according to the present embodiment, it is possible to form a compound semiconductor substrate having excellent flatness on a 4-inch Si substrate in addition to the above-described stress reduction.
なお、本発明は上記実施例に限定されるものではなく、
例えばIV族半導体基板としてGeを用いても良く、また中
間層としてGaPを用い、その上にInP層を形成した構造と
なす等の種々の変形、拡張が可能であることは言うまで
もない。The present invention is not limited to the above embodiment,
Needless to say, various modifications and expansions are possible, for example, Ge may be used as the group IV semiconductor substrate, GaP may be used as the intermediate layer, and an InP layer may be formed thereon.
＜発明の効果＞ 本発明により、平坦性及び結晶性の良いシングルドメイ
ンなInP単結晶基板が安価でしかも大口径で得られる。
また、Siを基体として用いているため、ハンドリング性
も良く、取り扱いが容易となる。<Effect of the Invention> According to the present invention, a single-domain InP single crystal substrate having good flatness and crystallinity can be obtained at a low cost and with a large diameter.
Further, since Si is used as the substrate, it has good handleability and is easy to handle.
第１図は本発明に係る一実施例の模式的な断面図、第２
図は本発明に係る他の実施例の模式的な断面を示す図、
第３図は第２図に示す構造の化合物半導体基板を形成す
る場合の成長温度の時間依存性を示す図である。 １……Si基板、２……GaAs中間層、３……目的とするIn
P層、４……低温形成GaAs層（中間層）、５……GaAs層
（中間層）、６……低温形成InP層、７……InP層。FIG. 1 is a schematic sectional view of an embodiment according to the present invention, FIG.
The figure shows a schematic cross section of another embodiment according to the present invention,
FIG. 3 is a diagram showing the time dependence of the growth temperature when the compound semiconductor substrate having the structure shown in FIG. 2 is formed. 1 ... Si substrate, 2 ... GaAs intermediate layer, 3 ... target In
P layer, 4 ... Low temperature formed GaAs layer (intermediate layer), 5 ... GaAs layer (intermediate layer), 6 ... Low temperature formed InP layer, 7 ... InP layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 木場 正義 大阪府大阪市阿倍野区長池町22番22号 シ ャープ株式会社内 (56)参考文献 特開 昭62−1225（ＪＰ，Ａ) Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．Ｖｏ ｌ．48 Ｎｏ．18（1986年）ＰＰ．1223〜 1225 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masayoshi Kiba 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Within Sharp Co., Ltd. (56) References JP-A-62-1225 (JP, A) Appl. Phys. Lett. Vol. 48 No. 18 (1986) PP. 1223 ~ 1225
Claims (2)
層と、 を備え、 上記Si、GaAs及びInPのそれぞれの熱膨張係数の関係
が、 GaAs＞InP＞Siとなるように構成してなることを特徴と
する化合物半導体基板。1. A Si substrate, a GaAs layer as an intermediate layer formed on the Si substrate, and a single-domain InP single crystal layer formed on the intermediate layer, the Si, GaAs, and A compound semiconductor substrate characterized in that the relationship of the thermal expansion coefficients of InP is such that GaAs>InP> Si.
上に形成されたシングルドメインなInP単結晶層の各々
の化合物半導体層が300〜450℃の低温で形成した1000Å
以下の膜厚の低温形成薄膜層を含んでなることを特徴と
する特許請求の範囲第１項記載の化合物半導体基板。2. The compound semiconductor layer of each of the GaAs layer as the intermediate layer and the single domain InP single crystal layer formed on the intermediate layer is formed at a low temperature of 300 to 450 ° C. 1000Å
The compound semiconductor substrate according to claim 1, comprising a low-temperature formed thin film layer having the following film thickness.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62169162A JPH0760790B2 (en) | 1987-05-13 | 1987-07-06 | Compound semiconductor substrate |
| US07/193,400 US5011550A (en) | 1987-05-13 | 1988-05-12 | Laminated structure of compound semiconductors |
| EP88304383A EP0291346B1 (en) | 1987-05-13 | 1988-05-13 | A laminated structure of compound semiconductors |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-117575 | 1987-05-13 | ||
| JP11757587 | 1987-05-13 | ||
| JP62169162A JPH0760790B2 (en) | 1987-05-13 | 1987-07-06 | Compound semiconductor substrate |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25664097A Division JP2880984B2 (en) | 1987-05-13 | 1997-09-22 | Compound semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6453407A JPS6453407A (en) | 1989-03-01 |
| JPH0760790B2 true JPH0760790B2 (en) | 1995-06-28 |
Family
ID=26455666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62169162A Expired - Fee Related JPH0760790B2 (en) | 1987-05-13 | 1987-07-06 | Compound semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0760790B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0775222B2 (en) * | 1987-11-02 | 1995-08-09 | 沖電気工業株式会社 | Method for manufacturing InP semiconductor thin film |
| JPH01189909A (en) * | 1988-01-26 | 1989-07-31 | Nippon Telegr & Teleph Corp <Ntt> | Composite semiconductor substrate |
| JPH0760791B2 (en) * | 1988-11-04 | 1995-06-28 | シャープ株式会社 | Compound semiconductor substrate |
| DE10042947A1 (en) * | 2000-08-31 | 2002-03-21 | Osram Opto Semiconductors Gmbh | Radiation-emitting semiconductor component based on GaN |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0236059B2 (en) * | 1984-07-16 | 1990-08-15 | Kogyo Gijutsuin | KAGOBUTSU HANDOTAINOSEICHOHOHO |
| JPH0799733B2 (en) * | 1986-10-27 | 1995-10-25 | 日本電信電話株式会社 | Semiconductor substrate |
-
1987
- 1987-07-06 JP JP62169162A patent/JPH0760790B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．Ｖｏｌ．４８Ｎｏ．１８（１９８６年）ＰＰ．１２２３〜１２２５ |
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| Publication number | Publication date |
|---|---|
| JPS6453407A (en) | 1989-03-01 |
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