JP2880984B2 - Compound semiconductor substrate - Google Patents

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention
The present invention relates to an improvement of a compound semiconductor substrate having a group III compound semiconductor layer formed thereon. 2. Description of the Related Art In recent years, the technology for growing a thin film crystal of a compound semiconductor has been remarkably developed, and various characteristic devices such as a semiconductor laser, a solar cell, and an ultra-high-speed device using a two-dimensional electron gas have been manufactured. However, since these devices use a III-V semiconductor substrate as a substrate, they are very expensive, and it is difficult to increase the area due to the difficulty of crystal growth. Therefore, on a group IV semiconductor substrate which is inexpensive, has good crystallinity, and has a large area,
Attention has been paid to a technique for forming a II-V compound semiconductor, and in particular, research on a technique for growing a GaAs thin film crystal on a Si substrate has been actively conducted. As a conventional technique for growing a GaAs thin film on a Si substrate, GaAs is first grown thinly at a low temperature.
A two-step growth method for growing GaAs thicker by further raising the temperature (Japanese Patent Publication No. 61-70715), a method using Ge for the intermediate layer between the Si substrate and GaAs (IEEE Electron)
Device Lett. EDL-2, 169 (19
81)), a method using an alternating layer of GaAs and another III-V compound semiconductor having a similar lattice constant as the intermediate layer (Japanese Patent Publication No. 60-12724), a method using a strained superlattice in the intermediate layer (J. App. Phys. 57, 4578 (198
5)) and the like have been proposed, and FETs, light-emitting diodes, semiconductor lasers, and the like have been prototyped. On the other hand, compared with GaAs, the peak speed and saturation speed of electrons are higher and the thermal conductivity is higher.
It is promising that InP is a group V compound semiconductor, operates at a higher frequency than GaAs, and may provide a higher power microwave power amplifier. [0005] However, when a group III-V compound semiconductor is formed on a substrate, the influence of large lattice irregularities and stress cannot be reduced, and the II is grown.
This has led to a decrease in the crystal quality of the IV group compound semiconductor.
For example, when an InP layer is formed on a Si substrate, an InP layer having excellent surface morphology and crystallinity cannot be obtained because of a large lattice constant difference of 8.1%. Accordingly, the present invention provides a compound semiconductor having a structure in which a group III-V compound semiconductor layer having excellent surface morphology and crystal quality can be obtained on a substrate having a large lattice irregularity formed on the substrate. It is intended to provide a substrate. In order to achieve the above object, a compound semiconductor substrate according to the present invention comprises a substrate and a first III-V compound as an intermediate layer formed on the substrate. A semiconductor layer; and a second III- layer formed on the intermediate layer.
A first group III-V compound semiconductor layer formed at a temperature lower than a growth temperature of the first group III-V compound semiconductor between the substrate and the intermediate layer; A second low-temperature formation I formed between the intermediate layer and the second III-V compound semiconductor layer at a temperature lower than the growth temperature of the second III-V compound semiconductor layer.
And a group II-V compound semiconductor layer. FIG. 1 is a sectional view showing the structure of a compound semiconductor substrate according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a Si substrate, and 4 denotes GaAs formed at a low temperature as an intermediate layer.
s layer, 5 a GaAs layer as an intermediate layer, 6 a low temperature formation I
An nP layer 7 is an InP layer. As one method for realizing the structure shown in FIG. 1, a reduced pressure MOCVD method was used. Here, the internal pressure of the reaction tube is 1
Although the pressure is reduced to 00 to 25 Torr, it can be formed even at atmospheric pressure. FIG. 2 shows the procedure for forming the substrate having the structure shown in FIG. 1 described above in terms of the time dependence of the growth temperature. As the base substrate 1, H
Using a 4-inch Si substrate washed in an F solution,
Heat treatment at 1000 ° C for about 10 minutes in an AsH ₃ atmosphere 8
I do. Subsequently, the temperature is lowered to 400 ° C.
The intermediate layer 4 has a thickness of 1000 ° or less (100 to 1000
After the formation in Å), the temperature was raised to 600 ° C., and the GaAs intermediate layer 5 was formed with a thickness of 500 to 10000Å. Further, the formation of the target InP layer was continued at 400 ° C.
After forming the low-temperature formed InP layer 6 having a thickness of 1000 ° or less, the required layer thickness (0.5 to 10 μm) at 600 ° C.
Was formed. The source gas used here is supplied under the conditions of triethylgallium (TE) when forming the GaAs layer 2.
G) and arsine (AsH ₃ ), and when forming the InP layer 3, trimethylindium (TMI) and phosphine (PH ₃ ) were used. Each supply amount is 2.
5 × 10 ⁻⁵ (molar fraction), 5.6 × 10 ⁵ in TMI
^-5 (molar fraction), and the supply ratio of AsH ₃ and TEG is 1
00, a PH ₃ and 70 to 200 in TMI, by diluting the source gas with H _2, as a reaction tube total flow rate was set to 15l / min. In the embodiment shown in FIG. 1, the lattice constant of each layer material is 5.431 ° for Si and 5.64 for GaAs.
2Å and InP are 5.868Å, and the lattice constant misfit between Si as the base and InP as the III-V compound semiconductor is 8.1%. Therefore, In directly on Si
When P is grown, a film with a flat surface cannot be obtained,
Many dislocations are present in the grown film, and a crystal having good crystallinity cannot be obtained. On the other hand, the lattice constant of GaAs is approximately halfway between the lattice constants of Si and InP, and is 4.1%
A lattice constant difference of 4.0% from InP is obtained. Also, Si and G
aAs and GaAs and InP are well compatible with each other. As a result, under all the conditions in this embodiment, a mirror-finished (good flatness) InP layer was obtained over the entire surface of the 4-inch Si substrate, and the thickness distribution of the InP layer was ±
The InP layer 7 having a good uniformity of 10% or less was obtained. From the observation with an optical microscope, no cracks were observed in the InP layer having a thickness of about 8 μm.
This corresponds to the result that the residual stress of the InP layer is small, and is very advantageous for forming a device (for example, an LED or the like) requiring a relatively large layer thickness.
Further, it was confirmed that a single-domain InP single crystal layer was obtained over the entire surface of the 4-inch Si substrate by the etching pattern shape using the HBr + H ₃ PO ₄ (hydrogen bromide + phosphoric acid) solution. As described above, according to the present embodiment, a compound semiconductor substrate having excellent flatness can be formed on a 4-inch Si substrate in addition to the aforementioned reduction in stress. The present invention is not limited to the above embodiment. For example, Ge may be used as a group IV semiconductor substrate, GaP may be used as an intermediate layer, and
It goes without saying that various modifications and expansions such as a structure having an nP layer are possible. As described above, according to the present invention, I
When forming the II-V compound semiconductor layer, an intermediate layer having a different composition is provided, and the intermediate layer and the III-V compound semiconductor layer are disposed between the intermediate layer and the intermediate layer and the III-V compound semiconductor layer. Also, by providing a low-temperature formation layer formed at each low temperature, lattice distortion due to lattice irregularity is reduced,
In addition, a group III-V compound semiconductor layer having small residual stress can be formed. Thus, a group III-V compound semiconductor substrate having good surface morphology and crystallinity can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a schematic cross section of an embodiment according to the present invention. FIG. 2 is a diagram showing time dependence of a growth temperature when a compound semiconductor substrate having the structure shown in FIG. 1 is formed. [Description of Signs] 1 Si substrate 2 GaAs intermediate layer 3 Target InP layer 4 Low-temperature formed GaAs layer (intermediate layer) 5 GaAs layer (intermediate layer) 6 Low-temperature formed InP layer 7 InP layer

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Masayoshi Kiba 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (56) References JP-A-63-108707 (JP, A) JP-A-61- 26216 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) C30B 28/00-35/00 H01L 21/205

Claims (1)

(57) [Claims] A substrate, and a first III- as an intermediate layer formed on the substrate.
A group III-V compound semiconductor layer; a second group III-V compound semiconductor layer formed on the intermediate layer; and a first group III-V between the substrate and the intermediate layer.
A first low-temperature-formed III-V compound semiconductor layer formed at a temperature lower than the growth temperature of the group-III compound semiconductor layer, and the second layer formed between the intermediate layer and the second III-V compound semiconductor layer. A second III-V compound semiconductor layer formed at a lower temperature than the growth temperature of the III-V compound semiconductor layer.