JPS6398120A - Crystal growth method - Google Patents
Crystal growth methodInfo
- Publication number
- JPS6398120A JPS6398120A JP24450786A JP24450786A JPS6398120A JP S6398120 A JPS6398120 A JP S6398120A JP 24450786 A JP24450786 A JP 24450786A JP 24450786 A JP24450786 A JP 24450786A JP S6398120 A JPS6398120 A JP S6398120A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- insulating film
- gaas
- layer
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002109 crystal growth method Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000013078 crystal Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims description 16
- 150000001875 compounds Chemical class 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 22
- 238000000034 method Methods 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 15
- 241000238557 Decapoda Species 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Recrystallisation Techniques (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はSi単結晶等の半導体基板上に熱膨張係数の異
なるGaAs 、 InP等の1[−V族化合物半導体
やZnS、 Zn5e等のU −■族化合物半導体単結
晶をエピタキシャル成長させる際の結晶成長方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention applies to semiconductor substrates such as Si single crystals, which are coated with 1[-V group compound semiconductors such as GaAs and InP, etc., which have different coefficients of thermal expansion, and U-■ such as ZnS and Zn5e. The present invention relates to a crystal growth method for epitaxially growing a group compound semiconductor single crystal.
従来の技術
近年、SL単結晶上にG a A s等のI[−V族化
合物半導体をエピタキシャル成長させる技術が盛んに研
究開発されている。というのは、SiはIC。BACKGROUND OF THE INVENTION In recent years, research and development have been actively conducted on techniques for epitaxially growing I[-V group compound semiconductors such as GaAs on SL single crystals. This is because Si is an IC.
LSI等の電気素子の基板材料として、G a A s
等の化合物半導体は発光ダイオードや半導体レーザ等の
光源材料として用いられているが、IC等を組み込んだ
Si基板上に光源をモノリシックに集積してやれば、光
電子集積回路(○EIC)として非常に有望となってく
る。一方、半導体レーザは高電流注入で動作させるため
発熱量は大きいので通常半導体レーザの冷却マウントに
熱伝導の良いSt ウェハー等が用いられており、半導
体し〜ザの結晶基板にStを用いれば、レーザの温度特
性の改善も期待できる。゛また、基板コストもStO方
が廉価である。As a substrate material for electric devices such as LSI, GaAs
Compound semiconductors such as these are used as light source materials for light emitting diodes, semiconductor lasers, etc., but if a light source is monolithically integrated on a Si substrate incorporating an IC, it is very promising as an optoelectronic integrated circuit (○EIC). It's coming. On the other hand, since semiconductor lasers are operated by high current injection and generate a large amount of heat, St wafers with good thermal conductivity are normally used as cooling mounts for semiconductor lasers. Improvements in the temperature characteristics of the laser can also be expected.゛Also, the substrate cost is cheaper for StO.
通常、例えばSi基板上にG a A s結晶をエピタ
キシャル成長する方法として、分子線エビタキシー法(
MBE)や有機金属気相成長法(MOVPE)等がある
。成長温度はだいたい500°C前後で行なっている。Usually, the molecular beam epitaxy method (
MBE) and metal organic vapor phase epitaxy (MOVPE). The growth temperature is approximately 500°C.
しかしながら、エピタキシャル成長後室塩まで冷却する
とG a A sエビ層にスリップ転位が走りクラック
や剥れが生じてエビ層の品質に悪影響を及ぼしている。However, when cooled to room salt after epitaxial growth, slip dislocation occurs in the Ga As shrimp layer, causing cracks and peeling, which adversely affects the quality of the shrimp layer.
その理由は主に、Si とG a A sとの熱膨張率
が大きく異なるため(線膨張率St : 2.5X10
−6/K 、 GaAs: 6.0X10−6/K )
、成長時にSi ウェハーとG a A sエピ層が平
坦に成長しても、室温時にはその熱膨張率の違いにより
ウェハーのソリが生じてエビ層に歪が加わり欠陥が生じ
てしまう。第5図、第6図に成長時のウェハーの状態と
成長後の室温におけるウェハーの模式的な概略図を示す
。1はSi基板、2はGaAsエピタキシャル層を示す
。The reason is mainly that the thermal expansion coefficients of Si and Ga As are significantly different (linear expansion coefficient St: 2.5X10
-6/K, GaAs: 6.0X10-6/K)
Even if the Si wafer and GaAs epitaxial layer grow flat during growth, the wafer warps due to the difference in their thermal expansion coefficients at room temperature, adding strain to the shrimp layer and causing defects. FIGS. 5 and 6 show the state of the wafer during growth and the schematic diagram of the wafer at room temperature after growth. 1 indicates a Si substrate, and 2 indicates a GaAs epitaxial layer.
発明が解決しようとする問題点
上述のように従来のSi基板上のGaAsのエピタキシ
ャル成長においては、SL とG a A sの熱膨張
係数の違いにより基板ウェハーにソリが生じてGaAs
エピ層に歪が加わってスリップ転位が走り、またクラッ
クや剥れ等の欠陥が生じるという問題が生じている。そ
こで本発明では、基板ウェハーのソリの緩和を目的とし
た成長方法を提供するものである。Problems to be Solved by the Invention As mentioned above, in the conventional epitaxial growth of GaAs on a Si substrate, warpage occurs in the substrate wafer due to the difference in thermal expansion coefficient between SL and GaAs, resulting in GaAs
Problems have arisen in that strain is applied to the epitaxial layer, causing slip dislocations to occur and defects such as cracks and peeling to occur. Therefore, the present invention provides a growth method for the purpose of alleviating warpage of a substrate wafer.
問題点を解決するための手段
本発明は、前述の問題点であるウェハーのソリを緩和す
るため、基板上にストライプ状の絶縁膜を形成し、前記
絶縁膜形成領域外の露出した基板表面に選択的にエピタ
キシャル層を形成するものである。Means for Solving the Problems In order to alleviate the above-mentioned problem of wafer warpage, the present invention forms a striped insulating film on a substrate, and forms a striped insulating film on the exposed substrate surface outside the insulating film forming area. This method selectively forms an epitaxial layer.
作 用
以上のように基板上に選択的にエピタキシャル層を形成
してやれば、熱膨張係数の差による基板とエピタキシャ
ル層の間に生じる熱応力が前記絶縁膜で途切れて断続的
になり、ウェハー全域に連続的に熱応力が加わらない。Function: If an epitaxial layer is selectively formed on a substrate as described above, the thermal stress generated between the substrate and the epitaxial layer due to the difference in thermal expansion coefficients is interrupted by the insulating film and becomes intermittent, spreading over the entire wafer. No continuous thermal stress is applied.
したがって、成長後のウェハーのソリは緩和され、エピ
タキシャル層に発生する欠陥は減少する。Therefore, warpage of the wafer after growth is alleviated, and defects occurring in the epitaxial layer are reduced.
実施例
以下、本発明の実施例を示す。第1図は本発明のストラ
イプ状絶縁膜を形成したSi(シリコン)ウェハーを示
す。1は3インチ−Siウェハー、2は格子状ストライ
プのS i02熱酸化膜を示す。第2図は、第1図のウ
ェハーにG a A sエピタキシャル層成長後のウェ
ハー断面を示す。3はG a A sエピタキシャル層
、4はSio2膜上に堆積しG a A sポリ結晶層
である。ここでS i O2膜2のストライプ幅は5■
、厚みは1μm、GaAgエピタキシャル層の厚みは1
μmである。G a A s層の成長方法はMBEまた
はMOVPE法等の気相成長法で行なった。したがって
、S 102膜2上にはG a A sポリ結晶4が堆
積した。その時、基板のソリはほとんど緩和され、良好
な結晶が形成されている。Examples Examples of the present invention will be shown below. FIG. 1 shows a Si (silicon) wafer on which a striped insulating film of the present invention is formed. 1 shows a 3-inch Si wafer, and 2 shows a Si02 thermal oxide film with lattice-like stripes. FIG. 2 shows a wafer cross-section after a GaAs epitaxial layer has been grown on the wafer of FIG. 3 is a GaAs epitaxial layer, and 4 is a GaAs polycrystalline layer deposited on the Sio2 film. Here, the stripe width of the SiO2 film 2 is 5■
, the thickness is 1 μm, and the thickness of the GaAg epitaxial layer is 1 μm.
It is μm. The GaAs layer was grown using a vapor phase growth method such as MBE or MOVPE. Therefore, GaAs polycrystal 4 was deposited on S 102 film 2. At that time, the warpage of the substrate is almost alleviated and good crystals are formed.
次に、フォトリングラフイー法により、フォトレジスト
6をG a A 8工ピタキシヤル層3上に第3図のよ
うに選択的に塗布し、G a A sポリ結晶4および
S 102酸化膜2をエツチングして、第4図のごとり
、Si基板1上にG a A tsエピタキシャル層3
を残し、プロセスを完了する。ここで、絶縁膜にS i
O2を用いたが、Sl 3N4膜、カーボン膜等地の
絶縁膜でも良いことは言うまでもない。またG a A
sの他InP系等の他の■−■族化合物半導体や■−
■族化合物半導体にも本発明は適用可能である。Next, as shown in FIG. 3, a photoresist 6 is selectively coated on the GaAs 8-layer pittaxial layer 3 by the photophosphorography method, and the GaAs polycrystal 4 and the S102 oxide film 2 are coated. As shown in FIG. 4, a Ga Ats epitaxial layer 3 is formed on the Si substrate 1 by etching.
and complete the process. Here, the insulating film is Si
Although O2 was used, it goes without saying that an insulating film such as a Sl 3 N 4 film or a carbon film may also be used. Also, G a A
In addition to s, other ■-■ group compound semiconductors such as InP and ■-
The present invention is also applicable to group (2) compound semiconductors.
発明の効果
以上のように、Si基板上にストライプ状の絶縁膜を形
成し、前記絶縁膜領域以外の領域にG a A sエピ
タキシャル層を形成すれば、基板のソリはほとんど無く
良好な結晶が得られる。また、前記絶縁膜を選択的に除
去してやれば、より一層の効果が得られる。さらに本発
明を用いればG a A s基板では困難な大口径ウェ
ハー(6インチ、8インチ・・・・・・)上にも薄膜の
エビ層が得られる。Effects of the Invention As described above, if a striped insulating film is formed on a Si substrate and a GaAs epitaxial layer is formed in a region other than the insulating film region, there is almost no warping of the substrate and good crystals are formed. can get. Further, if the insulating film is selectively removed, even more effects can be obtained. Furthermore, by using the present invention, a thin shrimp layer can be obtained even on large diameter wafers (6 inches, 8 inches, etc.), which is difficult to achieve with GaAs substrates.
第1図は本発明の一実施例の結晶成長方法におけるSi
基板上の3102絶縁膜パターンを示す平面図、第2図
は前記基板上に堆積したGa A s層の断面図、第3
図はG a A sポリ結晶およびS 102絶縁膜除
去工程を説明する断面図、第4図はSi基板上のG a
A s単結晶膜成長の最終工程を示す断面図、第S図
、第6図は従来の結晶成長方法を説明するための断面図
である。
1・・・・・・Si基板、2・・・・・・絶縁膜、3・
・・・・・G a A s単結晶膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名y−
3を基板
2−−−5LOz膿
第1図
f −、St、、N@
4− とそし4sオマリ力予1K
f−、Sム基板
第5図
第6図FIG. 1 shows Si in a crystal growth method according to an embodiment of the present invention.
FIG. 2 is a plan view showing the 3102 insulating film pattern on the substrate; FIG. 2 is a cross-sectional view of the GaAs layer deposited on the substrate;
The figure is a cross-sectional view explaining the process of removing the GaAs polycrystal and the S102 insulating film, and FIG.
A cross-sectional view showing the final step of growing an As single crystal film, FIG. S, and FIG. 6 are cross-sectional views for explaining a conventional crystal growth method. 1... Si substrate, 2... Insulating film, 3...
...G a As single crystal film. Name of agent: Patent attorney Toshio Nakao and one other person
3 to the board 2---5LOz pus Fig. 1 f -, St,, N@ 4- and 4s Omari force 1K f-, SM board Fig. 5 Fig. 6
Claims (2)
半導体単結晶をエピタキシャル成長するに際し、前記基
体上にストライプ状の絶縁膜を形成し、前記絶縁膜の形
成領域の露出した前記基体表面上に前記半導体単結晶を
エピタキシャル成長させるようにした結晶成長方法。(1) When epitaxially growing a semiconductor single crystal having a coefficient of thermal expansion different from that of the substrate on a semiconductor substrate, a striped insulating film is formed on the substrate, and a striped insulating film is formed on the exposed surface of the substrate in the region where the insulating film is formed. A crystal growth method comprising epitaxially growing the semiconductor single crystal.
体よりなる特許請求の範囲第1項記載の結晶成長方法。(2) The crystal growth method according to claim 1, wherein the semiconductor substrate is silicon and the semiconductor crystal is a compound semiconductor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24450786A JPS6398120A (en) | 1986-10-15 | 1986-10-15 | Crystal growth method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24450786A JPS6398120A (en) | 1986-10-15 | 1986-10-15 | Crystal growth method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6398120A true JPS6398120A (en) | 1988-04-28 |
Family
ID=17119703
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24450786A Pending JPS6398120A (en) | 1986-10-15 | 1986-10-15 | Crystal growth method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6398120A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02150020A (en) * | 1988-11-30 | 1990-06-08 | Kyocera Corp | Semiconductor element and manufacture thereof |
US5403751A (en) * | 1990-11-29 | 1995-04-04 | Canon Kabushiki Kaisha | Process for producing a thin silicon solar cell |
CN109119329A (en) * | 2018-07-16 | 2019-01-01 | 华天慧创科技(西安)有限公司 | A kind of film plating process reducing silicon wafer warpage degree |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60210832A (en) * | 1984-04-04 | 1985-10-23 | Agency Of Ind Science & Technol | Manufacture of compound semiconductor crystal substrate |
JPS61198713A (en) * | 1985-02-28 | 1986-09-03 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1986
- 1986-10-15 JP JP24450786A patent/JPS6398120A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60210832A (en) * | 1984-04-04 | 1985-10-23 | Agency Of Ind Science & Technol | Manufacture of compound semiconductor crystal substrate |
JPS61198713A (en) * | 1985-02-28 | 1986-09-03 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02150020A (en) * | 1988-11-30 | 1990-06-08 | Kyocera Corp | Semiconductor element and manufacture thereof |
US5403751A (en) * | 1990-11-29 | 1995-04-04 | Canon Kabushiki Kaisha | Process for producing a thin silicon solar cell |
CN109119329A (en) * | 2018-07-16 | 2019-01-01 | 华天慧创科技(西安)有限公司 | A kind of film plating process reducing silicon wafer warpage degree |
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