JPH02150020A - Semiconductor element and manufacture thereof - Google Patents

Abstract

PURPOSE:To inhibit an adverse phenomenon such as the warpage of a silicon substrate due to thermal stress as much as possible by limiting the sum of the length of two adjacent edges to a specific value in the size of a III-V compound semiconductor. CONSTITUTION:In a semiconductor element 31, a coating layer 33, in which a large number of through-holes 32 are formed partially onto a rectangular plate-shaped silicon substrate 3 and which is composed of silicon nitride SiNx, is shaped. Length L1 in the left and the right direction and length L2 in the vertical direction of the through-hole 32 are equalized respectively, and brought to L1=L2=70mum. GaAs crystal layers 26 are shaped onto the silicon substrate 3 facing the through-holes 32. The size of the GaAs crystal layer 26 formed in this manner is regulated so that the sum of the length of two adjacent edges in a plan view is brought to approximately 150mum or more. Thermal stress based on the difference of thermal expansion coefficients among said GaAs crystal layers 26 and the silicon substrate 3 is brought to magnitude regulated by each occupying area of the GaAs crystal layers 26, and an adverse effect on the silicon substrate 3 is inhibited as much as possible, thus preventing the warpage of the silicon substrate 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a heterostructure semiconductor element formed by forming a ■-■ group compound semiconductor layer on a silicon substrate, and a method for manufacturing the same.

Conventional technology G Ei A S and A l! on a silicon substrate. y G
Heterostructure semiconductor devices in which a ■-■ group chemical conductor such as a + -y AS or a mixed crystal semiconductor are epitaxially grown are widely used as high-speed PET (field effect transistor) devices, light-emitting devices, and light-receiving devices.

Conventionally, in forming such a heterostructure semiconductor device, an amorphous GaAs layer is first formed on a silicon substrate, and then G is converted by heating.
A technique is used to form an a As crystal layer.

In such a first conventional technique, dislocations occur at the interface between the two due to the difference in lattice constant between the two. Additionally, the silicon substrate warps due to the difference in thermal expansion coefficient between the two.Therefore, a second conventional technique has been proposed that introduces a strained superlattice layer at the interface between the silicon substrate and the monster conductor layer. However, when such a strained superlattice layer is introduced, the heptane semiconductor layer on the silicon substrate becomes thicker, which often causes cracks.

In addition, a third coating is formed on the back surface of the silicon substrate on which the chemical semiconductor layer is formed, and the coefficient of thermal expansion is lower than that of silicon.
However, in such a third conventional example, although the warping of the silicon substrate due to the difference in thermal expansion coefficient between the silicon substrate and the monster conductor layer is eliminated, the thermal expansion coefficient of both This does not eliminate the difference between the two, but thermal stress is generated at these interfaces, resulting in the generation of dislocations. Such an increase in dislocations unnecessarily increases the value of etch pitch density (EPD).

Problems to be Solved by the Invention An object of the present invention is to solve the above-mentioned technical problems, to suppress as much as possible phenomena such as warping of silicon substrates due to differences in thermal expansion coefficients, and to significantly improve the EPD. An object of the present invention is to provide an improved semiconductor device and a method for manufacturing the same.

Means for Solving the Problems The present invention comprises a silicon substrate, and an electrically insulating material formed on the silicon substrate and having a rectangular through hole having a size in which the sum of the lengths of two adjacent edges is about 150 μrn or less. A semiconductor element comprising: a covering layer made of a material; and a -V group hexagonal semiconductor layer formed on a silicon substrate facing the through hole.

Further, the present invention provides a method of forming a coating layer made of an electrically insulating material on a silicon substrate, and having a rectangular through hole having a size in which the sum of the lengths of two adjacent edges is about 150 μrΩ or less, and forming the covering layer in the through hole. This is a method for manufacturing a semiconductor device characterized by epitaxially growing a -V group compound semiconductor layer on a facing silicon substrate.

Function: In manufacturing the semiconductor device according to the present invention, the sum of the lengths of two adjacent edges on the silicon substrate is approximately 150 μm.
A covering layer made of an electrically insulating material is formed having rectangular through holes with a size of m or less.

A ■-■ group compound semiconductor is epitaxially grown on the silicon substrate facing this through hole.

In the semiconductor device thus manufactured, the size of the Group V compound semiconductor is limited to a sum of the lengths of two adjacent edges of approximately 150 μm or less, as described above. As a result, even if the thermal expansion coefficients of silicon and the ■-■ group monster conductor are different, the magnitude of the stress between the monster conductor and the silicon substrate for each through hole and the range in which this stress acts can be determined. limited to as small as possible. This suppresses phenomena such as warping of the silicon substrate due to thermal stress as much as possible, and by suppressing the occurrence of such thermal stress, dislocations associated with thermal stress are also suppressed, improving the crystallinity of semiconductor devices. (EPD) is significantly improved.

Embodiment FIG. 1 is a sectional view of a semiconductor element 31 according to an embodiment of the present invention, and FIG. 2 is a plan view of the semiconductor element 31. Referring to these drawings, a semiconductor element 31 of this embodiment has a covering layer 3 made of silicon nitride SiNx, for example, in which a large number of through holes 32 are locally formed on a rectangular plate-shaped silicon substrate 3.
3 is formed. The length Ll of the through hole 32 in the horizontal direction in FIG. 2 and the length L2 in the vertical direction are, for example, equal to each other, L1=L2=70 μrn
- (1) is selected. On the silicon substrate 3 facing this through hole 32, Ga
An As crystal layer 26 is formed. Such a semiconductor element 31 can constitute a light emitting diode array by forming each GεiAs crystal N26 as a part of a light emitting diode (LED).

FIG. 3 is a cross-sectional view illustrating the manufacturing process of this semiconductor element 31.
The epitaxial growth layer is manufactured using a manufacturing apparatus based on the OCVD method.

Prior to manufacturing such an epitaxial growth layer, a covering layer 33 consisting of a silicon nitride film and a silicon oxide SiO□ film is formed on the silicon substrate 3 as shown in FIG. 3(1). The coating layer 33 is made of GaAs, which will be described later.
It functions as a mask when forming the crystal layer 26, and further functions as a protective film for semiconductor circuits and the like monolithically formed in other locations on the silicon substrate 3.

After that, a photoresist 34 is applied on the coating layer 33,
After exposure, the pattern formed by the photoresist 34 is
Form as shown in Figure (2).

After this, the photoresist 3 is etched.
The wave 7171133 immediately below 4 remains, and the remaining portion of the covering layer 33 is removed. As a result, a coating 7133 having through holes 32 is formed as shown in FIG. 3(3).

For such a silicon substrate 3, M as described later is applied.
An epitaxial layer is grown using an OCVD apparatus, and Ga is formed in the through hole 32 portion as shown in Figure 3121(4)
A S crystal 8i26 is formed.

The size of the GaAs crystal layer 26 formed in this way is regulated to be approximately 150 μm or less, as shown in the first equation above, in which the sum of the lengths of two adjacent edges in plan view is . By forming the GaAs crystal N 26 in such a size, the thermal stress due to the difference in thermal expansion coefficient between the GaAs crystal layer 26 and the silicon substrate 3 can be reduced by each individual of the GaAs crystal layer 26. The size is determined by the occupied area, and the influence on the silicon substrate 3 is suppressed as much as possible. That is, warping of the silicon substrate 3 is prevented. In addition, thermal stress is applied to individual GaAs crystal layers 2.
6, the occurrence of dislocations caused by thermal stress is also suppressed, and the crystallinity, that is, the EPD, of the entire semiconductor element 31 is significantly improved.

FIG. 4 is a graph showing the results of measuring changes in stress in the semiconductor element 31 of this embodiment and in a conventional example in which a GaAs crystal layer was formed over the entire surface of a silicon substrate. This measurement was carried out using a so-called photoluminescence measuring device, and was performed using an argon laser beam having a wavelength of 514.5r+r. According to this, the measurement result for the semiconductor device 31 of the present embodiment shown by line 11 and the measurement result for the conventional semiconductor device shown by line 12 have a wavelength λ indicating the peak value.
A difference Δε was measured between 1°λ2 and 1°λ2.

According to this measurement result, regarding the magnitude of stress, conventional semiconductor device-2, OX 10' d yn / cm
2 semiconductor devices = 1, 4 x 10' d
A result of y n /c rn'' was obtained. According to this, the stress was reduced by about 30%.

FIG. 5 is a system diagram showing the configuration of an MOCVD apparatus used to form the GaAs crystal layer 26. As shown in FIG. Referring to FIG. 5, the MOCVD apparatus is provided with a reaction tube 1 made of, for example, quartz, in which a susceptor 2 coated with graphite with silicon carbide SiC is disposed, and a silicon substrate 3 is placed on top of the susceptor 2. will be boarded. A high frequency coil 4 is wound around the reaction tube 1, and high frequency power is supplied from a high frequency power source (not shown) to heat the susceptor 2 by induction.

A first tank 5 communicating with the reaction tube 1 is filled with a carrier gas such as hydrogen gas H1 or argon gas Ar, and a second tank 6 and a third tank 7 are filled with PH and AsH, respectively. be done. The hydrogen gas in the first tank 5 is highly purified through a purifier 8, and its flow rate is controlled by a mass flow controller (hereinafter abbreviated as MFC) 9.
Adjusted by 10. Also, the second and third tanks6.
The gas flow rates from 7 are also adjusted by MFCII and 12, respectively.

Further, in the present invention, TMG (trimethyl gallium) is used as the organic metal, which is liquid at room temperature and is homogenized in the bubbler 13 installed in the thermostatic chamber 14.

The carrier gas from the purifier 8 is introduced into the bubbler 13 by the MFC 10 to perform bubbling, whereby TMG in the bubbler 13 is gasified and introduced into the reaction tube 1 . This carrier gas is also used as a carrier gas for the gas from the second and third tanks 6.7 via the MFC 9. The piping system connecting the components constituting such MOCVD equipment includes gas regulating valves 17, 18.
9 and valves 20-25 are provided.

An ultra-high vacuum evacuation device 15 and an exhaust gas treatment device 16 are connected to the reaction tube 1, and the ultra-high vacuum evacuation device 15
is used to remove the residual gas in the reaction tube 1 prior to film formation, and the exhaust gas treatment device 16 is used to remove toxic arsenides, etc. from the exhaust gas during and after the film formation process. Remove.

FIG. 6 shows GaAs crystal Ji obtained by using the MOCVDgA apparatus shown in FIG.
226 is a cross-sectional view of a semiconductor element 28 including 226. FIG.

In this embodiment, a GaAs crystal layer 2 is formed on a silicon substrate 3.
6, the semiconductor element 28 of this embodiment provides a semiconductor element 28 in which the generation of dislocations as pointed out in the prior art section is suppressed based on the difference in lattice constant between the two. An intervening layer 27 is provided between the silicon substrate 3 and the GaAs crystal layer 26. The intervening layer 27 is made of Ga
AsxP.

It is a semiconductor, and has a structure in which the variable 't&x changes from 0 to 1 as it goes from the silicon substrate 3 to the GrtAs crystal layer 26.

That is, the silicon substrate 3r of the intervening layer 27! I! The near end is G;iP, and the vicinity of the end on the GaAs crystal layer 26 side is GaAs. That is, G
The lattice constant d of EtP is 5450, and the difference between it and the lattice constant d of silicon is (5,450-5,430)X10015.430=
0.368%...There is only the difference in (2).

This means that the degree of difference in lattice constant is approximately 1/10 compared to the difference in lattice constant between GElAs and silicon (4%) explained in the prior art, and it is possible for dislocations to occur at this interface. is being restrained. Further, the intervening layer 27 is a graded layer, and the occurrence of dislocations in the intervening layer 27 is prevented as much as possible. In this manner, in the semiconductor element 28 of this embodiment, the occurrence of dislocations in the heterostructure can be suppressed as much as possible.

7 and 8 [21] are graphs for explaining the manufacturing process of the semiconductor element 28 of this example, and FIG. 9 is a cross-sectional view for explaining each manufacturing step. The ilJ manufacturing process of the semiconductor element 28 will be explained with reference to these drawings.

A silicon substrate 3 cleaned according to a conventional method is mounted on a susceptor 2 in a reaction tube l.

Next, the inside of the reaction tube 1 is evacuated to, for example, about 10-'Torr by the ultra-high vacuum evacuation device 15, and from time t1 in FIG.
is heated by induction to a predetermined temperature T13 (for example, 900 to 9
Raise the temperature to 50°C. At this time, the gas 'vJn valve 17 of the first tank 5 is opened, and the valves 21, 22, 23 are opened.
is fully opened and carrier gas is introduced into the reaction tube 1 at a predetermined flow rate using the MFC 9. As a result, oxides and the like on the silicon substrate 3 are removed, and the period p until time t2 in FIG.
Cleaning is performed over H.

Next, the temperature of the silicon substrate 3 is set to T1, which is a second temperature range.
1 (e.g. 400-450°C, preferably 420°C)
After closing the valve 20, the valves 24 and 25 are fully opened, and a predetermined flow rate is introduced into the reaction tube 3 by the MFC 10. This allows T to be transported by the carrier gas.
MG can be introduced into the reaction tube 1 at a rate of, for example, 30 to 80 seconds. The supply amount of this TMG gas is
4 and the pressure inside the bubbler 13 set by the flow rate of carrier gas by MPCIO. In addition, the valve 18 is fully opened, and the MFC 11 adjusts the P Hz
A gas (preheated, for example, to 600 DEG C.) is fed into the reaction tube 1 at, for example, 500 to 7 DEG Os cm. This manufacturing step is carried out over a period PL2 up to time t3 in FIG. As a result, as shown in No. 911W(1), amorphous G is formed on the silicon substrate 3.
an initial film 29 made of P is formed by 100 to 400 people (preferably 200 people).

Following time t3 in FIG. 7 (in period P13 until t4, the valves 24 and 25 are shut off to shut off the supply of TMG gas,
and the temperature is changed from the temperature Tll to a temperature T12 (for example, 620" to 750"C, preferably 750"C to 750"C, which is the first temperature reaction).
temperature rises to 20°C).

At this time, the initial film 29 in an amorphous state crystallizes and becomes G
A P crystal layer 30 is obtained.

Next, in a period P14 after the time t4, the valve 20 is shut off, one valve is fully opened, and the MFC9.10, 11
．． TMG carried by carrier gas by 12
In addition to the gas, P H, , A s H3 are respectively flowed, 13
0-80 s c crn, 500-700 s c rn
crn and supplied into the reaction tube 1 at a total flow rate of 1200 scCm. Further, at this time, the susceptor 2 is heated to a temperature T12 (6
20 to 750°C, preferably 720°C).

Here, the flow rates of PH, gas and A S H3 gas are the 8th
I2! As shown in , at the beginning of period P14, the streams MP2. Fl (F2>Fl), but A
s H! The gas flow rate is controlled so as to gradually increase, and the Pll gas flow rate to gradually decrease. That is, as shown in FIG. 9(2), the thickness of the intervening layer 27 formed on the GaP crystal layer 30 is, for example, 0.
．． At time t5 when the thickness reaches 5 to 2.0 μrn (preferably 1.0 μm), the GaAsxP+ constituting the intervening layer 27
The variable X of −m is controlled to be 1. At this time, as shown in FIG. 8, the flow rates of the A s Hs gas and PH gas are respectively F3. F4 (F3>F4) is selected.

After the time t5, the valve 18 is shut off and the reaction tube 1 is closed.
TMG gas carried by carrier gas and A s H
Supply only 3 gases. At this time, the temperature of the susceptor 2 is selected to be 620°C to 750°C (preferably 720°C). In this way, as shown in FIG. 9(3), a GaAs crystal layer 26 is formed on the intervening layer 27 with a desired thickness.

In this way, G is applied on the silicon substrate 3 as described above.
In forming the aAs compound semiconductor crystal layer 26, it is possible to form a semiconductor element in which dislocations due to differences in lattice constants are significantly suppressed.

As another embodiment of the present invention, as the material forming the intervening layer, at least a portion of A 1 y Ga 1-y As is used instead of Ga As x P l-w,
It may be formed so that the variable y changes from 1 to 0. In this case, AlAs is formed on the initial film 29, and GaAs is formed on the film when the growth is completed.

In this way, a high quality semiconductor element 31 in which dislocations are significantly suppressed can be obtained. That is, the lifetime of minority carriers in a PN junction is positively correlated with the magnitude of internal stress.

The size of the GaAs crystal layer 26 is selected so that the sum of the lengths of two adjacent edges in plan view is about 150 μm or less, and the lower limit is selected so that the sum of the lengths is about 1 μm or more, for example. It was confirmed that the crystallinity (EDP) of the GaAs crystal layer 26 in the through hole 32 was poor at the periphery and improved as it approached the center. Therefore, through hole 3
If the size of 2 is too small, the influence of the inner wall of the coating layer 33 forming the through hole 32 will spread to the entire GaAs crystal layer 26,
This is because it deteriorates the overall crystallinity.

The covering layer 33 may be made of other electrically insulating materials such as Sin or IN, and the through hole 32 may have any type of rectangular shape in plan view.

Furthermore, the variation range of the variables x and y is not limited to 0 to 1, but 0 to 1.
It can be varied between any number between 1 and 1.

As described above, according to the present invention, the size of the ■-V group compound semiconductor is such that the sum of the lengths of two adjacent edges is approximately 150 μm.
m or less. As a result, even if silicon and the ■-■ group compound semiconductor have different coefficients of thermal expansion, the magnitude of the stress between the compound semiconductor and the silicon substrate for each through hole and the range in which this stress acts can be minimized. is limited to a small amount. As a result, phenomena such as warping of the silicon substrate due to thermal stress are suppressed as much as possible, and by suppressing such thermal stress, dislocations associated with thermal stress are also suppressed, and the crystallinity (EPD) of semiconductor devices is significantly improved. will be improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor element 31 according to an embodiment of the present invention;
FIG. 2 is a plan view of the semiconductor element 31, FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor element 31, FIG. 4 is a graph explaining the effects of this embodiment, and FIG. 5 shows the configuration of the MOCVD apparatus. A block diagram, FIG. 6 is a cross-sectional view of the semiconductor element 28, FIGS. 7 and 8 are graphs explaining the process of manufacturing the semiconductor element 28, and FIG. 9 is a cross-sectional view explaining the process of manufacturing the semiconductor element 28. It is. 3... Silicon substrate, 16... GaAs crystal layer, 2
7... Intervening layer, 28.31... Semiconductor element, 32.
...Through hole, 33...Covering layer

Claims (2)

[Claims] (1) a silicon substrate; a coating layer made of an electrically insulating material formed on the silicon substrate and having a rectangular through hole having a size in which the sum of the lengths of two adjacent edges is about 150 μm or less; 1. A semiconductor device comprising: a III-V compound semiconductor layer formed on a silicon substrate facing the through hole. (2) A silicon substrate formed with a covering layer made of an electrically insulating material having a rectangular through hole whose sum of lengths of two adjacent edges is approximately 150 μm or less on the silicon substrate, and facing the through hole. 1. A method for manufacturing a semiconductor device, comprising epitaxially growing a III-V compound semiconductor layer thereon.