JPH0258322A - Manufacture of semiconductor wafer - Google Patents
Manufacture of semiconductor waferInfo
- Publication number
- JPH0258322A JPH0258322A JP20842888A JP20842888A JPH0258322A JP H0258322 A JPH0258322 A JP H0258322A JP 20842888 A JP20842888 A JP 20842888A JP 20842888 A JP20842888 A JP 20842888A JP H0258322 A JPH0258322 A JP H0258322A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- gaas
- wafer
- layer
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000013078 crystal Substances 0.000 claims description 32
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 230000001788 irregular Effects 0.000 abstract 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 50
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 49
- 239000010410 layer Substances 0.000 description 43
- 230000000694 effects Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 231100000241 scar Toxicity 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体ウェハの製造方法、特にシリコン基板
の主面にＧａＡｓ結晶層が設けられた半導体ウェハの製
造技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor wafer, and particularly to a technology for manufacturing a semiconductor wafer in which a GaAs crystal layer is provided on the main surface of a silicon substrate.
半導体装置の製造には、シリコンやＧａＡｓ等の化合物
半導体からなるウェハ（半導体薄板）が用いられている
。Wafers (semiconductor thin plates) made of compound semiconductors such as silicon and GaAs are used in the manufacture of semiconductor devices.
ＧａＡｓ （ガリウム−砒素）の結晶は、半導体レーザ
素子の製造や、シリコン（Ｓｉ）に比較して電子移動度
が高い故に高性能デバイスの製造に多用されている。GaAs (gallium-arsenide) crystals are frequently used in the manufacture of semiconductor laser devices and high-performance devices because of their higher electron mobility than silicon (Si).
一方、Ｓｉ基板主面にＧａＡｓ結晶を成長させる技術が
開発されている。たとえば、電子情報通信学会発行「電
子情報通信学会誌Ｊ １９８７年２月号、昭和６２年２
月２５日発行、Ｐ１６９〜Ｐ１７３には、ｒｓｉ基板上
へのＧａＡｓ結晶基板成長と光素子への応用」について
記載されている。On the other hand, a technique for growing a GaAs crystal on the main surface of a Si substrate has been developed. For example, published by the Institute of Electronics, Information and Communication Engineers, “Journal of the Institute of Electronics, Information and Communication Engineers, February 1987 issue, February 1987.
Published on May 25th, pages 169 to 173, there is a description of ``Growth of GaAs crystal substrate on RSI substrate and application to optical devices''.
この文献には、Ｓｉ基板上にＣｙａＡｓを成長させる意
義を下記のように３つに分類している。In this document, the significance of growing CyaAs on a Si substrate is classified into three categories as follows.
（１）Ｓｉでは不可能なデバイスをＳｉ基板上に作成す
る。(1) Creating a device on a Si substrate that is impossible with Si.
（２）Ｓｉの基板としての良さを生かしてその上に高性
能デバイスを作る。(2) Taking advantage of the advantages of Si as a substrate to create high-performance devices on it.
（３）ＳｉとＧａＡｓを組み合わせた新しいデバイスを
開発する。(3) Develop a new device that combines Si and GaAs.
また、この文献には、ＭＯＣＶＤ （有機金属気相成長
）法やＭＢＥ（分子線エピタキシー）法でＳｉ上にＧａ
Ａｓを成長させる方法や光素子への応用について記載さ
れている。This document also describes how to deposit Ga on Si using MOCVD (metal-organic chemical vapor deposition) or MBE (molecular beam epitaxy).
The method for growing As and its application to optical devices are described.
上記のように、ＧａＡｓ結晶はＳｉに比較してより脆弱
である。また、ＧａＡｓによるデバイスおよびＳｉによ
るデバイスを組み合わせる等の目的で、Ｓｉ結晶基板（
単にＳｉ基板とも称する。As mentioned above, GaAs crystals are more brittle compared to Si. In addition, for the purpose of combining GaAs devices and Si devices, Si crystal substrates (
It is also simply referred to as a Si substrate.
）の主面にＧａＡｓ結晶層（単にＧａＡｓ層とも称する
。）を設ける技術が開発されている。) A technique has been developed in which a GaAs crystal layer (also simply referred to as a GaAs layer) is provided on the main surface of the substrate.
従来、ＧａＡｓ結晶層はＳｉ基板の主面全域にエピタキ
シャル成長によって設けられている。しかし、Ｓｉの格
子定数は５．４３１人、ＧａＡｓの格子定数は５．６５
３人と異なるため、３１基板とＧａＡｓＪｉは約４％の
格子不整合を生じ、界面には応力が作用する。Conventionally, a GaAs crystal layer is provided over the entire main surface of a Si substrate by epitaxial growth. However, the lattice constant of Si is 5.431, and the lattice constant of GaAs is 5.65.
Since the three are different, a lattice mismatch of about 4% occurs between the 31 substrate and GaAsJi, and stress acts on the interface.
ところで、生産性向上、製造コスト低減のためには、ウ
ェハの口径は大きければ大きい程良い。Incidentally, in order to improve productivity and reduce manufacturing costs, the larger the diameter of the wafer, the better.
しかし、前述のように、Ｓｉ基板とＧ ａ Ａ ｓ層の
格子不整合からウェハ径が大きくなるにつれて歪みも大
きくなり、この結果として、ウェハが反り返ったりある
いは脆弱なＧａＡｓ層部分にクラックが発生してしまう
、ＧａＡｓ層部分のクラックの発生はＧａＡｓ層部分に
設けられるデバイスの特性の変動や歩留りの低下を来た
すことになる。However, as mentioned above, due to the lattice mismatch between the Si substrate and the GaAs layer, as the wafer diameter increases, the strain increases, and as a result, the wafer may warp or cracks may occur in the weak GaAs layer. The occurrence of cracks in the GaAs layer portion causes variations in the characteristics of devices provided in the GaAs layer portion and a decrease in yield.
また、ウェハの反りは、回路パターンの高精度化。Additionally, wafer warping is due to higher precision circuit patterns.
微細化を妨げかつ歩留りの低下を来すことになる。This impedes miniaturization and causes a decrease in yield.
本発明の目的は、クランクがなくかつ反りのない多層構
造型半導体ウェハの製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a multilayer semiconductor wafer that is crank-free and warp-free.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明の半導体ウェハの製造方法にあっては
、Ｓｉ基板主面にＧａＡｓ結晶層をエピタキシャル成長
法で形成する際、前記Ｓｉ基板の主面に格子状にＳｉＯ
□膜からなるマスクを形成した後、ＭＢＥ法あるいはＭ
ＯＣＶＤ法によって、露出したＳｉ基板主面部分に所望
厚さのＧａＡｓ結晶層を形成する。その後、前記マスク
は除去される。これによって、Ｓｉ゛基板の主面に数十
μｍｍ口数数百μｍ口ＧａＡｓ結晶層を縦横に配列した
多層構造型の半導体ウェハを製造することができる。That is, in the method for manufacturing a semiconductor wafer of the present invention, when forming a GaAs crystal layer on the main surface of a Si substrate by epitaxial growth, SiO2 is formed in a lattice pattern on the main surface of the Si substrate.
□After forming a film mask, MBE method or M
A GaAs crystal layer of a desired thickness is formed on the exposed main surface of the Si substrate by OCVD. The mask is then removed. As a result, it is possible to manufacture a multilayer structure type semiconductor wafer in which GaAs crystal layers of several tens of micrometers and several hundreds of micrometers are arranged vertically and horizontally on the main surface of a Si substrate.
上記した手段によれば、本発明の半導体ウェハの製造方
法にあっては、Ｓｉ基板の主面にマスクを設けた後、マ
スクで被われないＳｉ基板主面領域にＧａＡｓ結晶層を
設けることから、製造されたウェハは板状の厚いＳｉ基
板と、このＳｉ基板主面に点在的に設けられた数十μｍ
ｍ口数数百μｍ口複数のＧａＡｓ１ｌとで構成されるた
め、ＳｉとＧａＡｓの格子定数が約４％程度異なっても
、Ｓｉ基板に接触する各ＧａＡｓ層の界面の長さ（面積
）は小さく、界面には格子不整合による大きな応力は発
生しなくなり、脆弱なＧａＡｓ１にデバイス特性を変動
させるような歪みやクランクが発生しなくなる。また、
ＧａＡｓ層とＳｉ５板との接触は、点在的であるため、
ＧａＡｓ層とＳｉ基板との格子不整合による応力発生部
も局所的となり、Ｓｉ基板全体に一定の方向性を有する
応力（歪み）が発生するようなこともなくなるため、ウ
ェハの反りという現象も発生しなくなる。According to the above means, in the semiconductor wafer manufacturing method of the present invention, after providing a mask on the main surface of the Si substrate, a GaAs crystal layer is provided in the region of the main surface of the Si substrate that is not covered with the mask. The manufactured wafer consists of a plate-shaped thick Si substrate and a few tens of micrometers of wafers dotted on the main surface of the Si substrate.
Since it is composed of multiple GaAs layers with a diameter of several hundred micrometers, even if the lattice constants of Si and GaAs differ by about 4%, the length (area) of the interface of each GaAs layer in contact with the Si substrate is small; Large stress due to lattice mismatch no longer occurs at the interface, and strain or crank that would change device characteristics no longer occurs in the fragile GaAs1. Also,
Since the contact between the GaAs layer and the Si5 plate is scattered,
Stress generation due to lattice mismatch between the GaAs layer and the Si substrate becomes localized, and stress (strain) with a certain direction does not occur across the entire Si substrate, resulting in the phenomenon of wafer warping. I won't.
以下図面を参照して本発明の一実施例について説明する
。An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による半導体ウェハの製造方
法によって製造されたウェハを示す斜視図、第２図は同
しく前記単位のデバイスが形成されるウェハにおけるチ
ンプ部分を示す斜視図、第３図は半導体ウェハの製造方
法においてマスクが形成されたウェハの斜視図、第４図
は同じ＜ＧａＡｓ結晶層が形成されたウェハの断面図、
第５図は同じくマスクが除去されたウェハを示す断面図
である。FIG. 1 is a perspective view showing a wafer manufactured by a semiconductor wafer manufacturing method according to an embodiment of the present invention, FIG. 3 is a perspective view of a wafer on which a mask is formed in a semiconductor wafer manufacturing method, and FIG. 4 is a cross-sectional view of a wafer on which a GaAs crystal layer is formed.
FIG. 5 is a cross-sectional view of the wafer from which the mask has been removed.
この実施例では、Ｓｉ結晶基板の主面に点在状態でＧａ
Ａｓ結晶層を形成した多層構造型の半導体ウェハ（単に
ウェハとも称する。）の製造について説明する。In this example, Ga is scattered on the main surface of the Si crystal substrate.
Manufacturing of a multilayer structure type semiconductor wafer (also simply referred to as a wafer) in which an As crystal layer is formed will be described.
本発明によって製造された多層構造型のウェハ１は、た
とえば、第１図に示されるような構造となっている。す
なわち、ウェハ１は単結晶シリコンによって形成された
Ｓｉ結晶基板（ＳｉＷ板）２と、このＳｉ基板２の主面
にピッチ見１ｍで縦横に規則正しく形成された矩形のＧ
ａＡｓ結晶層（Ｇ ａ Ａ ｓ層）３とからなっている
。前記Ｓｉ基）反２は、たとえば、その厚さが３５０μ
ｍ〜４００ｇｍ、直径が５インチとなっている。また、
矩形状の前記ｃａＡｓＦｉ３は、数十μｍ口〜数百μｍ
口となっている。このＧａＡｓ層３の主面表層部には、
たとえば、高性能電界効果トランジスタ（ＦＥＴ）等が
製造される。なお、単位のデバイスは、後２図に示され
るように、ａ、ｂなる辺を有する矩形体からなるチップ
部分に形成される。A multilayer structure type wafer 1 manufactured according to the present invention has a structure as shown in FIG. 1, for example. That is, the wafer 1 includes a Si crystal substrate (SiW plate) 2 made of single crystal silicon, and rectangular Gs regularly formed vertically and horizontally at a pitch of 1 m on the main surface of the Si substrate 2.
It consists of an aAs crystal layer (GaAs layer) 3. For example, the thickness of the Si-based film 2 is 350 μm.
m~400gm, diameter is 5 inches. Also,
The rectangular caAsFi3 has an opening of several tens of μm to several hundred μm.
It has become a mouth. In the surface layer of the main surface of this GaAs layer 3,
For example, high performance field effect transistors (FETs) and the like are manufactured. Note that the unit device is formed in a chip portion consisting of a rectangular body having sides a and b, as shown in the second figure.
この例ではａおよびｂは同一寸法となっていて、ＧａＡ
ｓ層３は数十μｍ口〜数百μｍ口の正方形となっている
。またチップ部分４の寸法は数百μｍ−数ｍｍとなって
いる。このＳｉ結晶基板２およびＧａＡｓ層３の厚さお
よび外形寸法は、製造するデバイスに対応して適宜選択
される。In this example, a and b have the same dimensions, and GaA
The S layer 3 has a square shape with an opening of several tens of μm to several hundreds of μm. Further, the dimensions of the chip portion 4 are several hundred μm to several mm. The thickness and external dimensions of the Si crystal substrate 2 and the GaAs layer 3 are appropriately selected depending on the device to be manufactured.
つぎにこのような構造のウェハｌの製造方法について説
明する。Next, a method for manufacturing a wafer I having such a structure will be explained.
痕初に第３図に示されるように、厚さが３５０μｍ〜４
００μｍとなりか？直径が５インチとなるＳｉ結晶基板
２が用意される。As shown in Figure 3, the thickness of the scar is 350 μm to 4
Is it 00μm? A Si crystal substrate 2 having a diameter of 5 inches is prepared.
前記Ｓｉ基板２の主面全域にはＳｉｎ、膜が、たとえば
ｌｌＩｍ〜数μｍの厚さに設けられるとともに、この５
ｉＯｚ膜は常用のホトリソグラフィによって部分的に除
去され、同図のように数十μｍ口〜数百μｍ口の窪み６
が設けられる。この窪み６は縦横に一定間隔（ｐ）に設
けられている。A Sin film is provided on the entire main surface of the Si substrate 2 to a thickness of, for example, llIm to several μm, and this 5
The iOz film is partially removed by conventional photolithography, and as shown in the figure, a depression 6 of several tens of μm to several hundred μm is formed.
will be provided. The depressions 6 are provided at regular intervals (p) in the vertical and horizontal directions.
この間隔ρは、製造する半導体デバイスによって異なり
、たとえば数百μｍ−数ｍｍの長さが選択される。なお
、前記Ｓｉ基板２の一縁は直線状に切り欠かれ、結晶の
方向性認識のためのオリエンテーション・フラット７と
なっている。This interval ρ varies depending on the semiconductor device to be manufactured, and is selected to have a length of several hundred μm to several mm, for example. Incidentally, one edge of the Si substrate 2 is cut out in a straight line to form an orientation flat 7 for recognizing the orientation of the crystal.
つぎに、第４図に示されるように、前記Ｓｉ基板２の主
面にはＭＢＥ法あるいはＭＯＣＶＤ法によってＧａＡｓ
からなるエピタキシャル成長層が形成される。このエピ
タキシャル成長法にあっては、ＧａＡｓの結晶はＳｉｎ
、膜からなるマスク５の上には堆積しないため、ＧａＡ
ｓ結晶層３は、Ｓｉ結晶基板２が直接露出する窪み６の
底上に堆積（成長）することになる。このエピタキシャ
ル成長は、たとえば、ＧａＡｓ層３の厚さが１１Ｉｍ〜
数μｍとなる程度行われる。Next, as shown in FIG. 4, GaAs is deposited on the main surface of the Si substrate 2 by MBE or MOCVD.
An epitaxial growth layer consisting of is formed. In this epitaxial growth method, the GaAs crystal is
, GaA is not deposited on the mask 5 consisting of a film.
The s-crystal layer 3 will be deposited (grown) on the bottom of the depression 6 where the Si crystal substrate 2 is directly exposed. In this epitaxial growth, for example, the thickness of the GaAs layer 3 is 11 Im~
This is done to the extent that the thickness is several μm.
つぎに前記Ｓｉ基板２の主面に設けられたマスク５はぶ
つ酸素エッチャントを用いてエツチング除去され、第１
図および第５図に示されるようなウェハ１、すなわち、
多層構造型のウェハが製造される。Next, the mask 5 provided on the main surface of the Si substrate 2 is removed by etching using an oxygen etchant.
A wafer 1 as shown in FIG.
A multilayer structure type wafer is manufactured.
このような実施例によれば、つぎのような効果が得られ
る。According to such an embodiment, the following effects can be obtained.
（１）本発明の多層構造型ウェハは、ＧａＡｓ結晶層は
厚いＳｉ結晶基板上に点在的に設けられている。この結
果、ＳｉとＧａＡｓの格子定数が約４％程度異なっても
、Ｓｉ基板に接触する各ＧａＡｓ層の界面の長さは小さ
いため、界面には格子不整合による大きな応力は発生し
なくなり、脆弱なＧａＡｓ層にデバイス特性を変動させ
るような歪みやクランクが発生しなくなるという効果が
得られる。(1) In the multilayer structure wafer of the present invention, GaAs crystal layers are provided in spots on a thick Si crystal substrate. As a result, even though the lattice constants of Si and GaAs differ by approximately 4%, the length of the interface between each GaAs layer in contact with the Si substrate is small, so large stress due to lattice mismatch is no longer generated at the interface, making it brittle. The effect is that distortion and cranks that would cause variations in device characteristics do not occur in the GaAs layer.
（２）上記（１）により、本発明の多層構造型ウェハは
、Ｓｉ結晶基板上のＧＪＡｓ層は数十μｍ口〜数百μｍ
口と小さくかつ点在的に設けられていることから、Ｇａ
Ａｓ層とＳｉ基板との格子不整合による応力発生部もそ
れぞれ局所的となり、Ｓｉ基板全体に一定の方向性を有
する応力（歪み）が発生するようなこともなくなるため
、ウェハの反りは発生しなくなるという効果が得られる
。(2) According to (1) above, in the multilayer structure wafer of the present invention, the GJAs layer on the Si crystal substrate has a thickness of several tens of μm to several hundred μm.
Ga
Stress generation areas due to lattice mismatch between the As layer and the Si substrate are localized, and stress (strain) with a certain direction does not occur in the entire Si substrate, so wafer warping does not occur. The effect is that it disappears.
（３）本発明の多層構造型ウェハは、ＧａＡｓ層はＳｉ
基板２の主面に点在的に設けられ、かつウェハはチップ
化する際、ＧａＡｓ程脆弱でないＳｉ部分で切断（ダイ
シング）できるため、ダイシングによるチップ化が採用
できるという効果が得られる。(3) In the multilayer structure wafer of the present invention, the GaAs layer is made of Si.
They are provided scattered on the main surface of the substrate 2, and when the wafer is made into chips, it can be cut (diced) at the Si portion, which is not as fragile as GaAs, so that it is possible to use dicing to make chips.
（４）上記（１）〜（３）により、本発明によれば、ウ
ェハの反り、ウェハ主面の化合物半導体結晶層の損傷が
発生しないことによる品質の高い製品を高歩留りで製造
できることと、ウェハのチップ化の際の歩留り向上によ
り、化合物半導体あるいは化合物半導体を含むＩＣの製
造コストの低減が達成できるという相乗効果が得られる
。(4) According to the above (1) to (3), according to the present invention, high quality products can be manufactured at a high yield because warping of the wafer and damage to the compound semiconductor crystal layer on the main surface of the wafer does not occur; By improving the yield when converting wafers into chips, a synergistic effect can be obtained in that the manufacturing cost of compound semiconductors or ICs containing compound semiconductors can be reduced.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない、たとえば、シリコン基板
およびＧａＡｓ層の厚さ、外形寸法は、必要に応じて決
定すればよい。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, the thickness and external dimensions of the silicon substrate and GaAs layer may be determined as necessary.
結晶層３を設けても良い、この例ではチップ部分４の各
部にそれぞれＧａＡｓを基体とした半導体素子や半導体
レーザ素子を形成することができるので、ＩＣ化あるい
は０ＥＩＣ化に適したウェハを製造することができると
いう効果を奏する。A crystal layer 3 may be provided. In this example, a GaAs-based semiconductor element or a semiconductor laser element can be formed in each part of the chip portion 4, so a wafer suitable for IC or 0EIC is manufactured. It has the effect of being able to
以上の説明では、主として本発明者によってなされた発
明を、その背景となった利用分野であるＧａＡｓ系化合
物半導体を部分的に設けた複合型ウェハの製造技術に適
応した場合について説明したが、それに限定されるもの
ではない。In the above explanation, the invention made by the present inventor was mainly applied to the manufacturing technology of composite wafers partially provided with GaAs-based compound semiconductors, which is the field of application that formed the background of the invention. It is not limited.
本発明は少なくともＩｎＰ系等他等信合物半導体とシリ
コン等の半導体とを複合化したウェハの製造技術には適
用できる。The present invention is applicable to at least a technology for manufacturing wafers in which other composite semiconductors such as InP and semiconductors such as silicon are combined.
［発明の効果〕
本願において開示される発明のうら代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。[Effects of the Invention] The effects obtained by the representative invention disclosed in this application are briefly explained below.
本発明による半導体ウェハは、３１基板の主面に数十μ
ｍｍ口数数百ｍ口のＧａＡｓ層が点在状態で設けられる
構造となっていることから、ＳｉとＧａＡｓの格子定数
が約４％異なっても、３１基板に接触する各ＧａＡｓ層
の界面の長さは小さく、界面には格子不整合による大き
な応力は発生しなくなり、脆弱なＧａＡｓ層にデバイス
特性を変動させるような歪みやクラックが発生しなくな
る。また、ＧａＡｓ層とＳｉ基板との接触は、点在的で
あるため、ＧａＡｓ層とＳｉ基板との格子不整合による
応力発生部も局所的となり、３１基板全体に一定の方向
性を有する応力（歪み）が発生するようなこともなくな
るため、ウェハの反りの発生もなくなる。したがって、
このようなウェハを使用した場合、ウェハの反りがない
ことから高精度のパターン形成が可能となり、半導体素
子の高密度化、高歩留り化が達成できるとともに、Ｇａ
Ａｓ層におけるクランクの発生も抑止できるため、デバ
イス特性が安定しかつ歩留りも向上する。この結果、半
導体デバイスの製造コストの低減が達成できる。The semiconductor wafer according to the present invention has a thickness of several tens of μm on the main surface of the 31 substrate.
Since the structure is such that GaAs layers with several hundred mm diameter are provided in a scattered manner, even if the lattice constants of Si and GaAs differ by approximately 4%, the length of the interface of each GaAs layer in contact with the 31 substrate is Therefore, large stress due to lattice mismatch will not be generated at the interface, and distortions and cracks that would change device characteristics will not occur in the fragile GaAs layer. Furthermore, since the contact between the GaAs layer and the Si substrate is scattered, the stress generation area due to the lattice mismatch between the GaAs layer and the Si substrate is also localized, and the stress having a constant directionality is distributed over the entire substrate (31). This also eliminates the occurrence of warping of the wafer. therefore,
When such a wafer is used, high-precision pattern formation is possible because there is no warping of the wafer, and it is possible to achieve high density and high yield of semiconductor devices.
Since the occurrence of cranks in the As layer can also be suppressed, device characteristics are stabilized and yields are improved. As a result, it is possible to reduce the manufacturing cost of semiconductor devices.
第１図は本発明の一実施例による半導体ウエノ＼の製造
方法によって製造されたウェハを示す斜視図、
第２図は同じく単位のデバイスが形成されるウェハにお
けるチップ部分を示す斜視図、第３図は半導体ウェハの
製造方法においてマスクが形成されたウェハの斜視図、
第４図は同じ（ＧａＡｓ結晶層が形成されたウェハの断
面図、
第５図は同じくマスクが除去されたウェハを示す断面図
、
第６図は本発明の他の実施例による半導体ウェハの製造
方法によって形成されたウェハにおける単一のチップ部
分を示す斜視図である。
１・・・ウェハ、２・・・Ｓｉ基板、３・・・ＧａＡｓ
層、４・・・チップ部分、５・・・マスク、６・・・窪
み、７・・・オリエンテーション第
図
３−−− ＧｃＬＡｓ層
第
図
第
図
第
図FIG. 1 is a perspective view showing a wafer manufactured by a semiconductor wafer manufacturing method according to an embodiment of the present invention, FIG. 2 is a perspective view showing a chip portion of the wafer on which unit devices are similarly formed, and FIG. The figure is a perspective view of a wafer on which a mask has been formed in the semiconductor wafer manufacturing method. 6 is a perspective view showing a single chip portion in a wafer formed by a method for manufacturing a semiconductor wafer according to another embodiment of the present invention. 1... Wafer, 2... Si substrate, 3...GaAs
Layer, 4... Chip portion, 5... Mask, 6... Recess, 7... Orientation Figure 3 --- GcLAs layer Figure Figure Figure
Claims (1)
結晶層をエピタキシャル成長によって形成するウェハの
製造方法であって、前記基板主面の半導体結晶層は基板
主面に選択的に設けられることを特徴とする半導体ウェ
ハの製造方法。 ２、シリコン単結晶からなる基板の主面に部分的にマス
クを形成する工程と、エピタキシャル成長によって前記
基板の主面のマスクに被われていない領域にＧａＡｓ結
晶層を形成する工程とを有することを特徴とする特許請
求の範囲第１項記載のウェハの製造方法。[Claims] 1. A wafer manufacturing method in which a semiconductor crystal layer on the main surface of the substrate is formed by epitaxial growth with a semiconductor crystal layer different from the material constituting the substrate, the semiconductor crystal layer on the main surface of the substrate is formed on the main surface of the substrate. A method for manufacturing a semiconductor wafer, characterized in that it is selectively provided. 2. A step of forming a mask partially on the main surface of a substrate made of single crystal silicon, and a step of forming a GaAs crystal layer in a region of the main surface of the substrate not covered by the mask by epitaxial growth. A method for manufacturing a wafer according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20842888A JPH0258322A (en) | 1988-08-24 | 1988-08-24 | Manufacture of semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20842888A JPH0258322A (en) | 1988-08-24 | 1988-08-24 | Manufacture of semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0258322A true JPH0258322A (en) | 1990-02-27 |
Family
ID=16556054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20842888A Pending JPH0258322A (en) | 1988-08-24 | 1988-08-24 | Manufacture of semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0258322A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02150020A (en) * | 1988-11-30 | 1990-06-08 | Kyocera Corp | Semiconductor element and manufacture thereof |
| JP2007081255A (en) * | 2005-09-16 | 2007-03-29 | Toyota Central Res & Dev Lab Inc | Method for manufacturing semiconductor lamination |
| CN100461466C (en) * | 2006-02-21 | 2009-02-11 | 台湾积体电路制造股份有限公司 | Method for avoiding aggradation thick film delamination and its manufactured solar battery |
| JP2009177168A (en) * | 2007-12-28 | 2009-08-06 | Sumitomo Chemical Co Ltd | Semiconductor substrate and method of manufacturing the same, and electronic device |
-
1988
- 1988-08-24 JP JP20842888A patent/JPH0258322A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02150020A (en) * | 1988-11-30 | 1990-06-08 | Kyocera Corp | Semiconductor element and manufacture thereof |
| JP2007081255A (en) * | 2005-09-16 | 2007-03-29 | Toyota Central Res & Dev Lab Inc | Method for manufacturing semiconductor lamination |
| CN100461466C (en) * | 2006-02-21 | 2009-02-11 | 台湾积体电路制造股份有限公司 | Method for avoiding aggradation thick film delamination and its manufactured solar battery |
| US8846149B2 (en) | 2006-02-21 | 2014-09-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Delamination resistant semiconductor film and method for forming the same |
| JP2009177168A (en) * | 2007-12-28 | 2009-08-06 | Sumitomo Chemical Co Ltd | Semiconductor substrate and method of manufacturing the same, and electronic device |
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