JPH0752713B2 - Method for growing compound semiconductor - Google Patents

Method for growing compound semiconductor

Info

Publication number
JPH0752713B2
JPH0752713B2 JP3746686A JP3746686A JPH0752713B2 JP H0752713 B2 JPH0752713 B2 JP H0752713B2 JP 3746686 A JP3746686 A JP 3746686A JP 3746686 A JP3746686 A JP 3746686A JP H0752713 B2 JPH0752713 B2 JP H0752713B2
Authority
JP
Japan
Prior art keywords
substrate
compound semiconductor
temperature
growing
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3746686A
Other languages
Japanese (ja)
Other versions
JPS62196813A (en
Inventor
正博 秋山
孝 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP3746686A priority Critical patent/JPH0752713B2/en
Publication of JPS62196813A publication Critical patent/JPS62196813A/en
Publication of JPH0752713B2 publication Critical patent/JPH0752713B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、化合物半導体の成長方法に関し、特にシリコ
ン(以下Siという)の半導体基板上に化合物半導体層を
エピタキシャル成長させる方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method for growing a compound semiconductor, and more particularly to a method for epitaxially growing a compound semiconductor layer on a semiconductor substrate of silicon (hereinafter referred to as Si).

(従来の技術) 一般に、Si等の半導体基板上に砒化ガリウム(以下GaAs
という)等の化合物半導体を成長させる場合、文献アプ
ライド・フィジックス・レターズ(Applied Physics Le
tters)38(10)、15May1981、pp779〜781に開示されて
いるように、Ge膜等のバッファ層を介して成長させた
り、文献 日経マイクロデバイス1986年1月号(昭和61
年1月1日発行)p.p.113〜127に開示されているよう
に、有機金属化合気相成長(以下MOCVDという)法や分
子線エピタキシャル(以下MBEという)法等によって前
記基板上に直接化合物半導体層を成長させたりしてい
る。
(Prior Art) Generally, gallium arsenide (hereinafter referred to as GaAs) is formed on a semiconductor substrate such as Si.
In the case of growing compound semiconductors, such as Applied Physics Le
38 (10), 15May1981, pp779-781, and growth through a buffer layer such as a Ge film, or literature Nikkei Microdevice January 1986 (Showa 61).
(Published January 1, 2013) As disclosed in pp113-127, a compound semiconductor layer is directly formed on the substrate by a metal organic chemical vapor deposition (hereinafter referred to as MOCVD) method or a molecular beam epitaxial (hereinafter referred to as MBE) method. Are growing.

(発明が解決しようとする問題点) しかしながらこのような化合物半導体の成長方法におい
て、一般に、化合物半導体の熱膨張係数は、Si等の半導
体基板の熱膨張係数よりも大きく化合物半導体の高い成
長温度から室温程度まで温度を下げると強い引っぱり応
力が化合物半導体成長層にかかっていた。このために、
基板が成長面の方向に凹に反ったり、また成長膜厚が厚
くなると、この応力のために成長層にクラックが入った
りするという問題があった。
(Problems to be Solved by the Invention) However, in such a method for growing a compound semiconductor, the thermal expansion coefficient of the compound semiconductor is generally larger than the thermal expansion coefficient of the semiconductor substrate such as Si, and the high growth temperature of the compound semiconductor When the temperature was lowered to about room temperature, a strong tensile stress was applied to the compound semiconductor growth layer. For this,
If the substrate warps concavely in the direction of the growth surface, or if the growth film becomes thick, there is a problem that the stress causes cracks in the growth layer.

本発明は、このSiの基板と化合物半導体の熱膨張係数の
差による応力を低減し、ウェハの反りや化合物半導体成
長層の膜圧を厚くした時のクラック等の発生を低減する
ことを目的とする。
The present invention aims to reduce the stress due to the difference in the coefficient of thermal expansion between the Si substrate and the compound semiconductor, and to reduce the occurrence of warpage of the wafer and cracks when the film pressure of the compound semiconductor growth layer is increased. To do.

(問題点を解決するための手段) 本発明は前記問題点を解決するために、Siの半導体基板
の裏面に、この半導体基板よりも熱膨張係数の小さいSi
O2等の裏面膜を所定の温度で被着させ、この半導体基板
の表面にGaAs等の化合物半導体層を前記所定温度より高
い温度で成長させるものである。
(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a backside of a Si semiconductor substrate with Si having a smaller coefficient of thermal expansion than the semiconductor substrate.
A backside film such as O 2 is deposited at a predetermined temperature, and a compound semiconductor layer such as GaAs is grown on the surface of this semiconductor substrate at a temperature higher than the predetermined temperature.

(作 用) 以上説明したように本発明によれば、半導体基板の裏面
に熱膨張係数の小さい裏面膜を所定温度で被着させてい
るので、この基板を化合物半導体の成長温度である前記
所定温度より高温にすることにより基板側に凸に反りが
生じ、さらにこの状態で化合物半導体を成長させている
ので、この凸に反った基板を室温程度まで温度を下げる
と元にもどる力が働き、平坦な基板を得ることができ
る。
(Operation) As described above, according to the present invention, the back surface film having a small thermal expansion coefficient is deposited on the back surface of the semiconductor substrate at a predetermined temperature. When the temperature is higher than the temperature, a convex warp occurs on the substrate side, and since the compound semiconductor is further grown in this state, when the temperature of the substrate warped by the convex is lowered to about room temperature, the force to return to the original works, A flat substrate can be obtained.

(実施例) 第1図(A)〜(C)は本発明の実施例を説明するため
の基板の断面図である。以下、図面に沿って説明する。
(Embodiment) FIGS. 1A to 1C are sectional views of a substrate for explaining an embodiment of the present invention. Hereinafter, description will be given with reference to the drawings.

まず第1図(A)に示すように、Si基板1を準備し、こ
のSi基板1の裏面にスパッタ法を用いて30℃程度の温度
でSiO2膜2を約1μm厚さに被着する。
First, as shown in FIG. 1 (A), a Si substrate 1 is prepared, and a SiO 2 film 2 is deposited on the back surface of the Si substrate 1 at a temperature of about 30 ° C. to a thickness of about 1 μm by using a sputtering method. .

次に、このSi基板1をGaAs層を成長させる装置内に入れ
てGaAs層の成長温度である600℃〜750℃にすると、Siの
熱膨張係数(2.4×10-6/deg)はSiO2の熱膨張係数(0.4
×10-6/deg)よりも大きいために、第1図(B)に示す
ように、Si基板1側に凸に反りが生ずる。
Next, when the Si substrate 1 is put into an apparatus for growing a GaAs layer and the growth temperature of the GaAs layer is 600 ° C. to 750 ° C., the coefficient of thermal expansion of Si (2.4 × 10 −6 / deg) is SiO 2 Coefficient of thermal expansion (0.4
Since it is larger than × 10 -6 / deg), as shown in FIG. 1 (B), a convex warp occurs on the Si substrate 1 side.

この状態で、GaAs層3をMOCVD法を用いて表面に成長さ
せた後、このSi基板1を室温(25℃)程度まで冷却する
と、凸に反っていたSi基板1は第1図(C)に示すよう
に平坦にもどる。実際にはGaAsの熱膨張係数は約6×10
-6/degであるため、もしSi基板1上にSiO2膜2を室温程
度で被着すると、GaAs層3を成長させた後、室温程度ま
で冷却すると、平坦よりもGaAs層3の成長面の方向にわ
ずかに凹になる。しかし、SiO2膜2を室温又は室温より
高く且つGaAs層3の成長温度より充分低い温度で被着し
た場合でも、SiO2膜2がない場合と比較すると、GaAs層
3を成長させる温度から室温まで降温した時の反りは少
なくなる。
In this state, the GaAs layer 3 is grown on the surface by the MOCVD method, and when the Si substrate 1 is cooled to room temperature (25 ° C.), the Si substrate 1 which is convexly warped is shown in FIG. 1 (C). Return to flat as shown in. Actually, the thermal expansion coefficient of GaAs is about 6 x 10
Since it is -6 / deg, if the SiO 2 film 2 is deposited on the Si substrate 1 at room temperature, the GaAs layer 3 is grown and then cooled to about room temperature. It becomes slightly concave in the direction of. However, the SiO 2 film 2 even when deposited at a sufficiently lower temperature than the growth temperature of higher and GaAs layer 3 at room temperature or at room temperature, when compared with the case where there is no SiO 2 film 2 at room temperature from the temperature of growing the GaAs layer 3 Warp when the temperature is lowered to

尚、本発明の実施例において、SiO2膜2の被着温度は室
温よりも低い方が望ましく、またその膜厚は厚い方が望
しい。
In the embodiment of the present invention, the deposition temperature of the SiO 2 film 2 is preferably lower than room temperature, and the film thickness thereof is preferably thick.

また、GaAs層3は600℃〜750℃の温度でMOCVD法により
成長させたが、400℃程度の温度で20nmくらいのGaAsを
成長させたのち750℃程度の温度で所定の厚さに成長さ
せる温度勾配を持たせた方法により成長させることもで
き、またMBE法等の良好なエピタキシャル成長法であれ
ば他の成長方法を用いることもできる。
The GaAs layer 3 was grown by the MOCVD method at a temperature of 600 ° C. to 750 ° C., but GaAs of about 20 nm was grown at a temperature of about 400 ° C. and then grown to a predetermined thickness at a temperature of about 750 ° C. The growth can be performed by a method having a temperature gradient, and another growth method can be used as long as it is a good epitaxial growth method such as the MBE method.

また、本発明の実施例ではSi基板上にGaAs層を成長させ
る場合について説明したが、化合物半導体はすべてSiよ
りも熱膨張係数が大きいため、他の化合物半導体を成長
させる場合にも適用できる。
Further, in the embodiments of the present invention, the case where the GaAs layer is grown on the Si substrate has been described, but since all compound semiconductors have a larger thermal expansion coefficient than Si, it can be applied to the case of growing other compound semiconductors.

(発明の効果) 以上説明したように、本発明によれば、Siの基板上に化
合物半導体を成長させた場合に、基板と化合物半導体成
長層との熱膨張係数の差による反りを低減できるので、
成長させた化合物半導体上に良好な素子を歩留り良く形
成することができ、また、大面積の基板に使用すること
も可能であるため高品質の大面積化合物半導体成長層を
得ることができ、さまざまな素子の製作に利用できる。
(Effects of the Invention) As described above, according to the present invention, when a compound semiconductor is grown on a Si substrate, it is possible to reduce warpage due to a difference in thermal expansion coefficient between the substrate and the compound semiconductor growth layer. ,
A good device can be formed on the grown compound semiconductor with a good yield, and since it can be used for a large area substrate, a high quality large area compound semiconductor growth layer can be obtained, It can be used to manufacture various devices.

【図面の簡単な説明】[Brief description of drawings]

第1図(A)〜(C)は本発明の実施例を説明するため
の基板の断面図である。 1……Si基板、2……SiO2膜、3……GaAs層。
1 (A) to 1 (C) are sectional views of a substrate for explaining an embodiment of the present invention. 1 ... Si substrate, 2 ... SiO 2 film, 3 ... GaAs layer.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】シリコンの半導体基板を準備する工程と、 該半導体基板の裏面に該半導体基板よりも熱膨張係数の
小さい裏面膜を所定温度で被着させる工程と、 該半導体基板の表面に化合物半導体層を前記所定温度よ
り高い温度で成長させる工程とを備えてなることを特徴
とする化合物半導体の成長方法。
1. A step of preparing a silicon semiconductor substrate, a step of depositing a backside film having a thermal expansion coefficient smaller than that of the semiconductor substrate at a predetermined temperature on the backside of the semiconductor substrate, and a compound on the surface of the semiconductor substrate. And a step of growing the semiconductor layer at a temperature higher than the predetermined temperature, the method of growing a compound semiconductor.
【請求項2】前記裏面膜はシリコン酸化膜であることを
特徴とする特許請求の範囲第1項記載の化合物半導体の
成長方法。
2. The method for growing a compound semiconductor according to claim 1, wherein the back surface film is a silicon oxide film.
【請求項3】前記化合物半導体層は砒化ガリウム層であ
ることを特徴とする特許請求の範囲第1項記載の化合物
半導体の成長方法。
3. The method for growing a compound semiconductor according to claim 1, wherein the compound semiconductor layer is a gallium arsenide layer.
JP3746686A 1986-02-24 1986-02-24 Method for growing compound semiconductor Expired - Lifetime JPH0752713B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3746686A JPH0752713B2 (en) 1986-02-24 1986-02-24 Method for growing compound semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3746686A JPH0752713B2 (en) 1986-02-24 1986-02-24 Method for growing compound semiconductor

Publications (2)

Publication Number Publication Date
JPS62196813A JPS62196813A (en) 1987-08-31
JPH0752713B2 true JPH0752713B2 (en) 1995-06-05

Family

ID=12498298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3746686A Expired - Lifetime JPH0752713B2 (en) 1986-02-24 1986-02-24 Method for growing compound semiconductor

Country Status (1)

Country Link
JP (1) JPH0752713B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002343717A (en) * 2001-05-18 2002-11-29 Matsushita Electric Ind Co Ltd Method for producing semiconductor crystal
JP4867137B2 (en) 2004-05-31 2012-02-01 住友化学株式会社 Compound semiconductor epitaxial substrate
JP4969607B2 (en) * 2009-05-25 2012-07-04 シャープ株式会社 Manufacturing method of semiconductor laminated structure
JP2013513944A (en) * 2009-12-11 2013-04-22 ナショナル セミコンダクター コーポレーション Backside stress compensation of gallium nitride or other nitride-based semiconductor devices
JP2015216329A (en) * 2014-05-13 2015-12-03 日本電信電話株式会社 Method for manufacturing semiconductor device
JP6827469B2 (en) * 2016-06-16 2021-02-10 株式会社サイオクス Nitride semiconductor template, method for manufacturing nitride semiconductor template, and method for manufacturing nitride semiconductor self-supporting substrate

Also Published As

Publication number Publication date
JPS62196813A (en) 1987-08-31

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