JPH04186824A - Semiconductor substrate and manufacture thereof - Google Patents

Semiconductor substrate and manufacture thereof

Info

Publication number
JPH04186824A
JPH04186824A JP31443290A JP31443290A JPH04186824A JP H04186824 A JPH04186824 A JP H04186824A JP 31443290 A JP31443290 A JP 31443290A JP 31443290 A JP31443290 A JP 31443290A JP H04186824 A JPH04186824 A JP H04186824A
Authority
JP
Japan
Prior art keywords
layer
formed
gaas
substrate
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31443290A
Inventor
Kuninori Kitahara
Nobuyuki Otsuka
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP31443290A priority Critical patent/JPH04186824A/en
Publication of JPH04186824A publication Critical patent/JPH04186824A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To obtain a semiconductor substrate with a GaAs layer, which is low in dislocation density and is formed on a substrate, by a method wherein the semiconductor substrate is formed into one of a substrate, wherein the GaAs layer is formed on the substrate, superlattice structure layers, which respectively consist of an AlAs layer and a GaAs layer, are formed on the GaAs layer and a GaAs layer is formed on the superlattice structure layer.
CONSTITUTION: A semiconductor substrate is formed into one of a structure wherein a GaAs layer 3 is formed on a substrate 1, superlattice structure layers 6, which respectively consist of an AlAs layer 4 and a GaAs layer 5, are formed on the layer 3 and a GaAs layer 7 is formed on the layer 6. For example, a polycrystal-shaped GaAs buffer layer 2 is grown on an Si substrate 1 in a thickness of about 10nm at 450°C and thereafter, the layer 2 is heated up to 700°C and a GaAs single crystal layer 3 is grown in a thickness of 2.0μm. Then, an AlAs layer 4 of a thickness of about 50nm is formed at 450°C using an ALE method and thereafter, the layer 4 is heated up to 700°C and a GaAs layer 5 of a thickness of about 100nm is grown using an MOCVD method. A growth process of a superlattice structure layer 6 consisting of the above layers 4 and 5 is repeatedly executed a plurality of times and after that, a GaAs layer 7 of a thickness required for a device is grown at 700°C using an MOCVD method.
COPYRIGHT: (C)1992,JPO&Japio
JP31443290A 1990-11-21 1990-11-21 Semiconductor substrate and manufacture thereof Pending JPH04186824A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31443290A JPH04186824A (en) 1990-11-21 1990-11-21 Semiconductor substrate and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31443290A JPH04186824A (en) 1990-11-21 1990-11-21 Semiconductor substrate and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH04186824A true JPH04186824A (en) 1992-07-03

Family

ID=18053287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31443290A Pending JPH04186824A (en) 1990-11-21 1990-11-21 Semiconductor substrate and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH04186824A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5441913A (en) * 1993-06-28 1995-08-15 Sumitomo Chemical Company, Limited Process of making a semiconductor epitaxial substrate
US6833161B2 (en) * 2002-02-26 2004-12-21 Applied Materials, Inc. Cyclical deposition of tungsten nitride for metal oxide gate electrode
US7732325B2 (en) 2002-01-26 2010-06-08 Applied Materials, Inc. Plasma-enhanced cyclic layer deposition process for barrier layers
US7781326B2 (en) 2001-02-02 2010-08-24 Applied Materials, Inc. Formation of a tantalum-nitride layer
US10280509B2 (en) 2001-07-16 2019-05-07 Applied Materials, Inc. Lid assembly for a processing system to facilitate sequential deposition techniques

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5441913A (en) * 1993-06-28 1995-08-15 Sumitomo Chemical Company, Limited Process of making a semiconductor epitaxial substrate
US7781326B2 (en) 2001-02-02 2010-08-24 Applied Materials, Inc. Formation of a tantalum-nitride layer
US10280509B2 (en) 2001-07-16 2019-05-07 Applied Materials, Inc. Lid assembly for a processing system to facilitate sequential deposition techniques
US7732325B2 (en) 2002-01-26 2010-06-08 Applied Materials, Inc. Plasma-enhanced cyclic layer deposition process for barrier layers
US6833161B2 (en) * 2002-02-26 2004-12-21 Applied Materials, Inc. Cyclical deposition of tungsten nitride for metal oxide gate electrode

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