JPH03247597A - Epitaxial growth method of iii-v compound semiconductor on silicon substrate - Google Patents
Epitaxial growth method of iii-v compound semiconductor on silicon substrateInfo
- Publication number
- JPH03247597A JPH03247597A JP4295190A JP4295190A JPH03247597A JP H03247597 A JPH03247597 A JP H03247597A JP 4295190 A JP4295190 A JP 4295190A JP 4295190 A JP4295190 A JP 4295190A JP H03247597 A JPH03247597 A JP H03247597A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- single crystal
- substrate
- semiconductor layer
- iii
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 title claims abstract description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 25
- 239000010703 silicon Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 19
- 150000001875 compounds Chemical class 0.000 title claims description 21
- 239000013078 crystal Substances 0.000 claims abstract description 23
- 230000000737 periodic effect Effects 0.000 claims description 3
- 238000005304 joining Methods 0.000 claims description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 9
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 abstract description 7
- 238000003486 chemical etching Methods 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 abstract 1
- 230000007704 transition Effects 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000000463 material Substances 0.000 description 5
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
シリコン基板上のＩＩＩ ｅ Ｖ族化合物半導体のエピ
タキシル成長方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for epitaxial growth of a group III e V compound semiconductor on a silicon substrate.
（従来の技術〉
シリコン単結晶基板上にガリウム砒素等のＩＩＩ−Ｖ族
化合物半導体層を成長させる再に、表面清浄化が困難で
あること、大きな格子定数差を有すること、シリコンが
共有結合結晶であるのに対しＩＩＩ ｅ Ｖ族化合物半
導体が分極性結晶であること等の問題がある。これらの
問題のためシリコン基板上に成長した化合物半導体層は
１０８ｃｍ−３程度の高い転位を有しデバイス作製に充
分な品質を得ることが困難であった。しかし、これらの
問題を低減する手法として、高温での基板表面清浄化、
歪超格子層からなるバッファ層、基板方位の傾斜等の方
法がある。これらの手法を用いたシリコン基板上への化
合物半導体層のエピタキシャル成長の例が応用電子物性
分科会研究報告（同報告書、Ｎｏ、 ４２４． ｐ、
１２）に報告されている。この従来例ではシリコン単結
晶基板上にＩｎＰ単結晶層を成長させており、エッチビ
ット密度として１０７ｃｍ−３が得られている。(Prior art) When growing a III-V compound semiconductor layer such as gallium arsenide on a silicon single crystal substrate, it is difficult to clean the surface, there is a large difference in lattice constant, and silicon is a covalently bonded crystal. However, there are problems such as the fact that Group IIIe V compound semiconductors are polarized crystals.Because of these problems, compound semiconductor layers grown on silicon substrates have high dislocations of about 108cm-3, making them difficult to use for devices. It has been difficult to obtain sufficient quality for fabrication.However, as a method to reduce these problems, cleaning the substrate surface at high temperature,
There are methods such as using a buffer layer made of a strained superlattice layer and tilting the substrate orientation. An example of epitaxial growth of a compound semiconductor layer on a silicon substrate using these methods is given in the Research Report of the Applied Electronic Materials Subcommittee (Report, No. 424. p.
12). In this conventional example, an InP single crystal layer is grown on a silicon single crystal substrate, and an etch bit density of 107 cm-3 is obtained.
（発明が解決しようとする課題）
しかしながら、転位が直接デバイス特性を左右する半導
体レーザや発光ダイオードでは１０５ｃｍ−３以下のエ
ッチビット密度に抑える必要があるため、従来の成長法
による結晶品質では発光素子への応用が困難であった。(Problem to be solved by the invention) However, in semiconductor lasers and light-emitting diodes, where dislocations directly affect device characteristics, it is necessary to suppress the etch bit density to 105 cm-3 or less. It was difficult to apply it to
本発明の目的はシリコン単結晶基板上に転位の少ないＩ
ＩＩ−Ｖ族化合物半導体層をエピタキシャル成長させる
ことを目的とする。The object of the present invention is to produce an I material with few dislocations on a silicon single crystal substrate.
The purpose is to epitaxially grow a II-V group compound semiconductor layer.
（課題を解決するための手段）
本発明のエピタキシャル成長方法はシリコン単結晶基板
上にＩＩＩ−Ｖ族化合物半導体層をエピタキシャル成長
する方法に於て、シリコン単結晶基板上に周期的にスト
ライプ状の開口部をもつ選択成長用マスクを形成する第
１の工程と前記ＩＩＩ−Ｖ族化合物半導体層をエピタキ
シャル成長させ隣接する前記開口部から成長した前記半
導体層の成長部側面を接合させシリコン基板面とほぼ平
行な平坦な前記化合物半導体表面を形成する第２の工程
とを備えることを特徴とする。(Means for Solving the Problems) The epitaxial growth method of the present invention is a method for epitaxially growing a III-V compound semiconductor layer on a silicon single crystal substrate. a first step of forming a mask for selective growth having a mask for selective growth; and a step of epitaxially growing the III-V compound semiconductor layer and joining the side surfaces of the growth portion of the semiconductor layer grown from the adjacent openings so as to be substantially parallel to the silicon substrate surface. and a second step of forming a flat surface of the compound semiconductor.
（作用）
本発明によるシリコン単結晶基板上へのＩＩＩ−Ｖ族化
合物半導体のエピタキシャル成長方法では、第一の工程
でシリコン基板上に周期的なストライプ状の開口部をも
つ選択成長用マスクを形成し、第２の工程で化合物半導
体層を選択的にエピタキシャル成長する。この場合、周
期的にストライプ状に開口されたシリコン単結晶表面か
ら成長した化合物半導体層は成長面と垂直方向への成長
と共に面内方向への側面成長を続は隣合うストライプ状
の半導体成長層と結合し、全体として基板面方位と平行
な方位を持つ平坦な成長表面を形成する。(Function) In the epitaxial growth method of a III-V compound semiconductor on a silicon single crystal substrate according to the present invention, a selective growth mask having periodic striped openings is formed on the silicon substrate in the first step. In the second step, a compound semiconductor layer is selectively epitaxially grown. In this case, a compound semiconductor layer grown from a silicon single crystal surface with periodic striped openings grows in the direction perpendicular to the growth plane and laterally grows in the in-plane direction. to form a flat growth surface with an overall orientation parallel to the substrate surface orientation.
以上のようにして形成された半導体層は内部にストライ
プ状の孔を持つ多孔質な単結晶半導体層となる。この多
孔質の半導体層は、シリコン基板と化合物半導体層との
７熱膨張率の違いにより発生する応力、および格子定数
差に起因する応力を軽減し、且つ、それらの応力によっ
て発生する転位の伝搬を阻止する。その結果この多孔質
の半導体層をバッファ層として用いることによりその上
に形成されるデバイス用の半導体層の転位の発生が低減
され、発光素子への応用が可能となる。The semiconductor layer formed as described above becomes a porous single crystal semiconductor layer having stripe-shaped pores inside. This porous semiconductor layer reduces the stress caused by the difference in coefficient of thermal expansion between the silicon substrate and the compound semiconductor layer and the stress caused by the difference in lattice constant, and also prevents the propagation of dislocations caused by these stresses. to prevent As a result, by using this porous semiconductor layer as a buffer layer, the occurrence of dislocations in a semiconductor layer for a device formed thereon is reduced, making it possible to apply the porous semiconductor layer to a light emitting element.
（実施例） 以下、図面を用いて本発明の詳細な説明する。(Example) Hereinafter, the present invention will be explained in detail using the drawings.
第１図は本発明の詳細な説明する工程図である。本実施
例ではシリコン単結晶基板上にインジウム燐単結晶層を
エピタキシャル成長させる場合について説明する。FIG. 1 is a detailed process diagram illustrating the present invention. In this embodiment, a case will be described in which an indium phosphorus single crystal layer is epitaxially grown on a silicon single crystal substrate.
まず第１の工程として４１０＞方向に２°傾けた（１０
０）面を表面とするシリコン単結晶基板上の上に熱ＣＶ
Ｄ法により厚さ２００ｎｍの５ｉ０２絶縁膜のマスク２
を積層したのち、通常のフォトリソグラフィーと化学エ
ツチングの手法により幅１ｐｍの（０１１）方向のスト
ライプ状の開口部３を周期５ｐｍで形成した（第１図（
ａ））。つぎに第２の工程として５ｉ０２絶縁膜層２を
選択成長マスクとして用い、シリコン単結晶表面が露出
している開口部３に選択的にガリウム砒素バッファ層４
をその表面が側面成長により全体として基板方位に平行
でかつ平坦な表面となるまでエピタキシャル成長を行な
い、続いて厚さ２ｐｍのインジウム燐層５を成長した（
第１図（ｂ））。ここではバッファ層４の厚さ４ｐｍ以
上で平坦化した。本実施例では選択成長特性を有するエ
ピタキシャル成長方法としてハイドライド気相成長法を
用いた。Ｖ族材料にはアルシン（分子式ＡｓＨ３）及び
ホスフィン（分子式ＰＨ３）を用い、ＩＩＩ族材料には
インジウム及びガリウムメタルを用い塩化水素との反応
により基板表面に導き成長させた。転位低減の効果を高
めるために、結晶成長前に高温（１０００’Ｃ）での表
面清浄化を行なった。First, as the first step, the 410> direction was tilted by 2 degrees (10
0) Thermal CV on the silicon single crystal substrate with the surface as the surface.
Mask 2 of 5i02 insulating film with a thickness of 200 nm by D method
After layering, stripe-shaped openings 3 with a width of 1 pm in the (011) direction were formed at a period of 5 pm using conventional photolithography and chemical etching methods (see Fig. 1).
a)). Next, in the second step, using the 5i02 insulating film layer 2 as a selective growth mask, a gallium arsenide buffer layer 4 is selectively formed in the opening 3 where the silicon single crystal surface is exposed.
Epitaxial growth was performed until the surface became a flat surface as a whole parallel to the substrate orientation by lateral growth, and then an indium phosphorus layer 5 with a thickness of 2 pm was grown (
Figure 1(b)). Here, the buffer layer 4 was flattened to a thickness of 4 pm or more. In this example, hydride vapor phase epitaxy was used as an epitaxial growth method having selective growth characteristics. Arsine (molecular formula: AsH3) and phosphine (molecular formula: PH3) were used as group V materials, and indium and gallium metal were used as group III materials, which were grown by being guided onto the substrate surface by reaction with hydrogen chloride. In order to enhance the effect of reducing dislocations, surface cleaning was performed at high temperature (1000'C) before crystal growth.
こうして形成したガリウム砒素バッファ層４は内部にス
トライプ状の孔を持つ多孔質な単結晶半導体層となる。The gallium arsenide buffer layer 4 thus formed becomes a porous single crystal semiconductor layer having stripe-shaped pores inside.
この多孔質の半導体層は、シリコン基板と化合物半導体
層との熱膨張率の違いにより発生する応力、および格子
定数差に起因する応力を軽減し、且つ、それらの応力に
よって発生する転位の伝搬を阻止する。その結果この多
孔質のガリウム砒素バッファ層４を用いることによりそ
の上に形成されるデバイス用のインジウム燐層５の転位
密度が１０５ｃｍ−３以下に低減され、転位に比較的敏
感なデバイスである半導体レーザや発光ダイオード等の
発光素子への応用が可能となる。This porous semiconductor layer reduces the stress caused by the difference in thermal expansion coefficient between the silicon substrate and the compound semiconductor layer and the stress caused by the difference in lattice constant, and also prevents the propagation of dislocations caused by these stresses. prevent. As a result, by using this porous gallium arsenide buffer layer 4, the dislocation density of the indium phosphide layer 5 for devices formed thereon is reduced to 105 cm-3 or less, and the semiconductor device is relatively sensitive to dislocations. Application to light-emitting elements such as lasers and light-emitting diodes becomes possible.
上記実施例ではガリウム砒素バッファ層４の上にインジ
ウム燐層５を成長させたがガリウム砒素等、他のＩＩＩ
ｅ Ｖ族化合物半導体層の場合においても同様の効果
が得られる。選択成長用マスクとして５ｉ０２膜を用い
たが窒化シリコン、アモルファスシリコン、カーボン等
でもよい。また開口部３の幅は１μｍ、周期５μｍとし
たが成長条件、材料により最適化すればよい。本実施例
の条件では幅１〜５１１ｍ、周期５〜１５ｐｍ程度で良
好な結果が得られる。またバッファ層４としてガリウム
砒素を用いたがインジウム燐、等地のＩＩＩ −Ｖ族化
合物でもよい。バッファ層はその上に積層する半導体層
と同じか、Ｓｉとその半導体層の中間の格子定数の半導
体であればよい。In the above embodiment, the indium phosphide layer 5 was grown on the gallium arsenide buffer layer 4, but other materials such as gallium arsenide, etc.
Similar effects can be obtained in the case of e V group compound semiconductor layer. Although a 5i02 film was used as a mask for selective growth, silicon nitride, amorphous silicon, carbon, etc. may also be used. Although the width of the opening 3 is 1 μm and the period is 5 μm, it may be optimized depending on the growth conditions and material. Under the conditions of this example, good results can be obtained with a width of 1 to 511 m and a period of about 5 to 15 pm. Further, although gallium arsenide is used as the buffer layer 4, it may also be a III-V group compound such as indium phosphorus. The buffer layer may be made of a semiconductor having a lattice constant that is the same as that of the semiconductor layer stacked thereon, or has a lattice constant between that of Si and the semiconductor layer.
上記実施例では選択成長特性を有する成長法としてハイ
ドライド気相成長法を用いたが、ケミカルビームエピタ
キシャル成長法ＭＯＶＰＥ成長法等の選択成長特性を有
する他の成長法を用いてもよい。In the above embodiment, hydride vapor phase epitaxy was used as a growth method having selective growth characteristics, but other growth methods having selective growth characteristics such as chemical beam epitaxial growth or MOVPE growth may be used.
（発明の効果）
Ｓｉ単結晶基板との熱膨張係数差、格子不整による転位
が多孔質な単結晶バッファ層の形成によって低減される
ために、従来技術に比べ結晶性が向上する。この結果転
位密度が１０５ｃｍ−３以下となり発光素子に応用する
ことができる。(Effects of the Invention) Since the difference in thermal expansion coefficient with the Si single crystal substrate and dislocations due to lattice misalignment are reduced by forming the porous single crystal buffer layer, crystallinity is improved compared to the conventional technology. As a result, the dislocation density becomes 10 5 cm -3 or less, which can be applied to light emitting devices.
第１図は本発明の詳細な説明する工程断面図である。
１・・・シリコン単結晶基板、２・・・マスク、３・・
・開口部、４・・・ガリウム砒素バッファ層、５・・・
インジウム燐層
を、それぞれ示す。FIG. 1 is a process cross-sectional view explaining the present invention in detail. 1...Silicon single crystal substrate, 2...Mask, 3...
- Opening, 4... Gallium arsenide buffer layer, 5...
Indium phosphorous layers are shown respectively.
Claims (1)
ピタキシャル成長する方法に於て、シリコン単結晶基板
上に周期的にストライプ状の開口部をもつ選択成長用マ
スクを形成する第一の工程と前記III−Ｖ族化合物半導
体層をエピタキシャル成長し、隣接する前記開口部から
成長した前記半導体層の成長部側面を接合させシリコン
基板面とほぼ平行な平坦な前記化合物半導体表面を形成
する第２の工程とを備えることを特徴とするシリコン基
板上へのIII−Ｖ族化合物半導体のエピタキシャル成長
方法。In a method for epitaxially growing a III-V compound semiconductor layer on a silicon single crystal substrate, a first step of forming a selective growth mask having periodic striped openings on the silicon single crystal substrate; a second step of epitaxially growing a III-V compound semiconductor layer and joining the side surfaces of the growth portions of the semiconductor layers grown from the adjacent openings to form the flat compound semiconductor surface substantially parallel to the silicon substrate surface; 1. A method for epitaxially growing a III-V compound semiconductor on a silicon substrate, the method comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4295190A JPH03247597A (en) | 1990-02-22 | 1990-02-22 | Epitaxial growth method of iii-v compound semiconductor on silicon substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4295190A JPH03247597A (en) | 1990-02-22 | 1990-02-22 | Epitaxial growth method of iii-v compound semiconductor on silicon substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03247597A true JPH03247597A (en) | 1991-11-05 |
Family
ID=12650331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4295190A Pending JPH03247597A (en) | 1990-02-22 | 1990-02-22 | Epitaxial growth method of iii-v compound semiconductor on silicon substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03247597A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2418531A (en) * | 2004-09-22 | 2006-03-29 | Univ Warwick | Formation of lattice-tuning semiconductor substrates |
| US9344200B2 (en) | 2014-10-08 | 2016-05-17 | International Business Machines Corporation | Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth |
| US9395489B2 (en) | 2014-10-08 | 2016-07-19 | International Business Machines Corporation | Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxially formed material |
-
1990
- 1990-02-22 JP JP4295190A patent/JPH03247597A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2418531A (en) * | 2004-09-22 | 2006-03-29 | Univ Warwick | Formation of lattice-tuning semiconductor substrates |
| US9344200B2 (en) | 2014-10-08 | 2016-05-17 | International Business Machines Corporation | Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth |
| US9395489B2 (en) | 2014-10-08 | 2016-07-19 | International Business Machines Corporation | Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxially formed material |
| US9590393B2 (en) | 2014-10-08 | 2017-03-07 | International Business Machines Corporation | Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth |
| US9726819B2 (en) | 2014-10-08 | 2017-08-08 | International Business Machines Corporation | Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth |
| US9864135B2 (en) | 2014-10-08 | 2018-01-09 | International Business Machines Corporation | Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxially formed material |
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