JP2503255B2 - Method for manufacturing compound semiconductor substrate - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a manufacturing technique of a compound semiconductor substrate having a single crystal gallium arsenide layer on a single crystal silicon substrate.

(Prior Art) A compound semiconductor composed of gallium (Ga) which is a group III element and arsenic (As) which is a group V element has a higher crystallinity than that of silicon (Si) which has been widely used in the past. The movement speed of electrons is high, and its application to optical devices and electronic devices is drawing attention.

As a compound semiconductor substrate used for manufacturing such various devices, vapor-phase growth of single-crystal GaAs on a single-crystal Si substrate has been widely performed at present. This is because it is difficult to obtain a large amount of bulk made of only compound semiconductors in a short time.

However, the lattice constant of single-crystal GaAs is about 4 (%) larger than the lattice constant of single-crystal Si, resulting in lattice mismatch. For this reason, single crystal GaAs on the surface of the single crystal Si substrate,
When the deposition is directly performed, the crystal defect density (Etch Pit Density: EPD) of the single crystal GaAs becomes large, and it is difficult to obtain a device having excellent characteristics.

As a technique for obtaining such a compound semiconductor substrate having a small EPD, for example, Document I: “Journal of Crystal Growth”
(Journal of Crystal Growth) ”(Vol.7
7, 490-497, published in 1986), a buffer layer made of, for example, an amorphous state or a polycrystalline state, or a GaAs in which these two states are mixed is formed at a low temperature on the surface of a single crystal Si substrate. After depositing in the process, this a-
A technique for depositing and growing single crystal GaAs on the surface of the GaAs buffer layer by a high temperature process is known. For the purpose of facilitating the understanding of the following description, gallium arsenide in which the crystal is in an amorphous state, a polycrystalline state, or a mixture of these two states is comprehensively represented as a-GaAs, and gallium arsenide in a single crystal state is referred to as Each of them is represented as GaAs.

Hereinafter, the technique disclosed in the above-mentioned document I will be described with reference to the drawings.

FIG. 3 is an explanatory view showing a schematic cross section of a compound semiconductor substrate for explaining the technique disclosed in the above-mentioned document. In the figure, 11 is made of silicon (Si),
A substrate having a (100) plane, 13 is an a-GaAs buffer layer, and 15 is a GaAs layer having a single crystal state. Further, some hatching showing the cross section is omitted.

First, the substrate 11 described above is prepared, and the natural oxide film formed on the substrate surface is removed using, for example, fluorine (HF).

Next, low pressure MOCVD (Metal Organic Chemical Vapor
The above-mentioned substrate 11 is loaded into the reaction tube of a Deposition (organic metal chemical vapor deposition) apparatus. After that, this reaction tube
The pressure is reduced to 90 to 100 (Torr), and then a mixed gas of arsine (AsH ₃ ) and hydrogen (H ₂ ) is introduced. In this mixed gas atmosphere, heat treatment is performed at a temperature of about 900 (° C.) or higher to clean the surface of the substrate 11.

After performing such processing, a buffer layer is formed. In the case of the technology disclosed in this document, trimethylgallium (Ga (CH ₃ ) ₃ : TMG) is used as a raw material of gallium, and AsH ₃ is used as a raw material of arsenic. (Å) a-GaAs layer 13 with the following film thickness
Put on.

Subsequently, the substrate 11 having the above-mentioned laminated state is heated.
The compound semiconductor substrate is obtained by raising the temperature to a relatively high temperature condition within the range of 650 to 750 (° C.) and depositing and growing the GaAs layer 15 using the source gas (TMG and AsH ₃ ).

In this way, Ga is deposited on the Si substrate through the a-GaAs buffer layer.
The technique for depositing As is generally called a two-step growth method. According to the principle of this method, a single crystal layer (Ga
A buffer layer (a-GaAs layer 13) deposited on the lower layer side during the growth of the As layer 15) by deposition.
Partially rearranges (transposes) into a single crystal state, and alleviates the lattice constant mismatch between single crystal silicon and single crystal gallium arsenide. It should be understood that FIG. 3 only shows the stacking relationship according to the manufacturing process and does not show the stacking state of the obtained compound semiconductor substrate.

The compound semiconductor substrate obtained by the above-mentioned technique is Si
The EPD on the surface of the GaAs layer can be made smaller than when the GaAs layer is directly grown on the surface of the substrate.
The greater the thickness of the GaAs layer 15 deposited and grown on the surface of the layer 13, the greater the degree of EPD reduction.

(Problems to be Solved by the Invention) As can be understood from the above description, it is possible to reduce the EPD by increasing the thickness of the gallium arsenide layer in the single crystal state via the buffer layer. . However, it is the conventional compound described above. However, in the above-described conventional method for forming a compound semiconductor substrate,
The difference in the coefficient of thermal expansion between single crystal silicon and single crystal gallium arsenide is large. Therefore, when the compound semiconductor substrate is formed by increasing the thickness of the GaAs layer, “warpage” occurs when the substrate is taken out at room temperature. For example, when a single-crystal gallium arsenide layer is grown to a thickness of about 4 to 5 (μm) or more under the deposition conditions of each layer described with reference to FIG. 3, cracks occur in the layer. However, there is a problem that the lattice defect density (EPD) cannot be sufficiently improved.

In view of the above-mentioned conventional problems, an object of the present invention is EP
Provided is a compound semiconductor substrate manufacturing method capable of avoiding the occurrence of cracks due to "warpage" of the substrate even when single-crystal gallium arsenide is grown to a large thickness in order to reduce D. Thus, it is possible to simply and easily provide a compound semiconductor substrate capable of producing various devices having excellent characteristics.

(Means for Solving the Problem) In order to achieve this object, according to the compound semiconductor substrate manufacturing method of the first invention of this application, a buffer layer is formed on the surface of a single crystal silicon (Si) substrate. In order to manufacture a compound semiconductor substrate by depositing and growing a single crystal gallium arsenide (GaAs) layer on the surface of this buffer layer at a high temperature, the above-mentioned deposition of the buffer layer is The method is characterized in that the first gallium arsenide buffer layer, the indium phosphide (InP) buffer layer, and the second gallium arsenide buffer layer are sequentially deposited from the surface.

Further, according to the method for manufacturing a compound semiconductor substrate in the second invention of this application, a buffer layer is deposited on the surface of a single crystal silicon (Si) substrate, and the surface of the buffer layer is made of single crystal gallium arsenide (GaAs). ) Layer is grown at a high temperature to manufacture a compound semiconductor substrate, the above-mentioned buffer layer is deposited from the surface of the above-mentioned silicon substrate to the first gallium arsenide buffer layer and the indium phosphide (InP) buffer layer. Sequentially depositing to form a first buffer layer, a step of depositing and growing a single crystal indium phosphide layer on the surface of the first buffer layer at a high temperature, and the single crystal indium phosphide described above. The step of depositing a second gallium arsenide buffer layer on the surface of the layer to form the second buffer layer is performed.

(Operation) In the method for manufacturing a compound semiconductor substrate according to this application, the thermal expansion coefficient α _Si of single crystal _silicon , the thermal expansion coefficient α _GaAs of single crystal gallium arsenide, and the thermal expansion coefficient α _InP of single crystal indium phosphide are α _GaAs > It is based on the fact that α _InP > α _Si .

First, according to the manufacturing method of the first invention of this application,
After the buffer layer consisting of the above-mentioned three layers is deposited on the surface of the silicon substrate, a single crystal gallium arsenide layer is deposited and grown at a high temperature. For this reason, the above-described two-step growth method is applied only once.

Further, according to the method of the second invention of this application, first, the first buffer layer consisting of the above-mentioned two layers is deposited on the surface of the silicon substrate, and then the single crystal indium phosphide layer is deposited at a high temperature. Grow. Following such a first two-step growth method, a second buffer layer composed of a second gallium arsenide buffer layer is deposited on the surface of the single crystal indium phosphide layer, and a second two-step growth method is performed. When applied, a single crystal gallium arsenide layer is deposited and grown.

Therefore, in the method according to this application, the stress (stress) generated between silicon and gallium arsenide is reduced by manufacturing the compound semiconductor substrate with a structure containing indium phosphide as the buffer layer, so that the thermal expansion coefficient of these two substances is reduced. The indium phosphide having an intermediate value of (3) as a coefficient of thermal expansion is caused to act so as to reduce the “warpage” of the substrate which causes cracks.

(Embodiment) An embodiment of the invention according to this application will be described below with reference to the drawings. In addition, in the following examples, in order to facilitate understanding of the invention, specific conditions are illustrated and described, but the invention is not limited to these specific conditions. Further, in the following examples, the compound constituting the buffer layer has the crystal in the amorphous state or the polycrystalline state, or these two, as described in the prior art.
The gallium arsenide in which the two states are mixed is referred to as a-GaAs, the gallium arsenide in the single crystal state is referred to as GaAs, and the indium phosphorus in the amorphous state or the polycrystalline state or a mixture of these two states is referred to as the a-InP. , Indium phosphide in a single crystal state will be described as InP. Further, in the following description, the method according to the first invention will be described as the first embodiment, and then the method according to the second invention will be described with the second embodiment.

First Embodiment FIG. 1 is an explanatory view showing a schematic cross section of a compound semiconductor substrate, similar to FIG. 3, for explaining an embodiment of the first invention. It should be understood that, like FIG. 3 described above, this figure illustrates the stacking relationship according to the manufacturing process, and does not show the stacking state of the obtained compound semiconductor substrate.

According to the procedure described as the prior art, the above (10
After removing the native oxide film formed on the surface of the substrate 11 made of silicon having a (0) surface, the substrate 11 is loaded into the reaction tube of the low pressure MOCVD apparatus, and the reaction tube is heated to 90 to 100 (Tor).
Reduce the pressure to r). Then, a mixed gas of AsH ₃ and H ₂ is introduced into the reaction tube, and heat treatment is performed at a temperature of about 900 (° C.) or higher to clean the surface of the substrate 11.

After such treatment, an a-GaAs layer 17 corresponding to the first gallium arsenide buffer layer is deposited at a low temperature of 450 (° C.) or lower and a film thickness of 200 (Å) or lower.

Then, on the surface of the a-GaAs layer 17 described above, about 300-550.
The a-InP layer 19 is deposited with a film thickness of 200 (Å) or less at a predetermined temperature within the range of (° C.). This a-InP layer 19 corresponds to an indium phosphide buffer layer, and in this embodiment, for example, Reference II: "Proceedings of the 35th Applied Physics Association Joint Lecture Meeting" (Page 213, Lecture No. 28a-Z). −1, 1988), the a-InP layer 19 was deposited under the deposition conditions disclosed in US Pat. That is, trimethyl indium (In (C
H ₃ ) ₃ : TMI) and phosphine (PH ₃ ) are used, and the molar ratio of these two source gases ([PH ₃ ] / [In (CH ₃ ) ₃ ]) is set to about 500, and flatness is obtained by the MOCVD method. The a-InP layer 19 was deposited.

Subsequently, an a-GaAs layer 21 corresponding to the second gallium arsenide buffer layer is deposited on the surface of the a-InP layer 19. This a-
The deposition of the GaAs layer 21 was performed under the same deposition conditions as for the a-GaAs layer 17 described above.

In this way, the a-GaAs layer 17, a-
After the InP layer 19 and the a-GaAs layer 21 are sequentially deposited to form the buffer layer 23, the temperature is raised to a relatively high temperature condition within the range of 650 to 750 (° C.) as in the conventional case. After that, the GaAs layer 25 is grown using the source gas (TMG and AsH ₃ ),
A compound semiconductor substrate is obtained.

A GaAs layer made of single-crystal gallium through the above steps
By depositing 25 with a film thickness of about 4 (μm), it is possible to prevent the occurrence of cracks by reducing the "warpage" of the substrate, and obtain a compound semiconductor substrate with a low lattice defect density (EPD). It was

Second Embodiment Next, regarding a second embodiment according to the second invention of this application,
Similar to the first embodiment, description will be made with reference to the drawings.

FIG. 2 is an explanatory view showing a schematic cross section of a compound semiconductor substrate, similar to FIGS. 1 and 3, for explaining the embodiment of the second invention. Only the stacking relationship according to is illustrated.

First, the (10
After removing the native oxide film formed on the (0) surface, low pressure MOCVD is performed.
The substrate 11 is loaded into the reaction tube of the device, and 90 to 100 (T
orr). Then, using a mixed gas of AsH ₃ and H ₂ , the substrate 11 was heated at a temperature of about 900 (° C) or higher.
Clean the surface of.

After this cleaning treatment, 200 at a low temperature of 450 (℃) or less
(Å) An a-GaAs layer 27 corresponding to the first gallium arsenide buffer layer is deposited with the following film thickness.

Next, on the surface of the a-GaAs layer 27 described above, similarly to the a-InP layer 19 of the first embodiment described above, a predetermined value within the range of about 300 to 550 (° C.) and 200 (Å) or less. An a-InP layer 29 is deposited with a film thickness.

As described above, the a-GaAs layer 27 and the a-InP are formed on the surface of the substrate 11.
By sequentially depositing layers 29 and 29, the first buffer layer 31
Is formed.

Next, on the surface of the first buffer layer 31 described above, about 600
The InP (single crystal indium phosphide) layer 33 is deposited and grown at a relatively high temperature within the range of ˜650 (° C.). This InP layer 33
Was grown by MOCVD technology to a film thickness of about 1 (μm) with the above-mentioned molar ratio of PH ₃ and TMI ([PH ₃ ] / [In (CH ₃ ) ₃ ]) being about 100. .

As is conventionally known, the lattice constant of InP is about 8 (%) larger than that of GaAs. Therefore, in the method according to the second invention of this application, the above-mentioned first buffer layer 31
Then, the InP layer 33 was grown on the surface of the layer 31 at a high temperature.

Then, under the same deposition conditions as for the a-GaAs layer 27 described above, by depositing the a-GaAs layer 35 corresponding to the second gallium arsenide buffer layer on the surface of the InP layer 33 described above, The buffer layer is formed. After that, 650-750 (℃)
The temperature is raised to a relatively high temperature condition within the range of, and the GaAs layer 37 is grown using TMG and AsH ₃ to obtain a compound semiconductor substrate.

Also in this second embodiment, the GaAs layer made of single crystal gallium
By depositing 35 with a film thickness of about 4 (μm), the occurrence of cracks can be avoided by reducing the warpage of the substrate, and a compound semiconductor substrate with a low lattice defect density (EPD) can be obtained. It was

Although the embodiments of the invention according to this application have been described in detail above, it is obvious that the invention is not limited to these embodiments.

For example, in the above-described embodiment, as a technique for depositing a compound semiconductor substrate in an amorphous state or a single crystal state, a case where a metalorganic chemical vapor deposition method using a source gas composed of a methylated compound of a Group III element is used is described. The example has been described.

However, the invention according to this application is not obtained only by such a deposition technique, and instead of the above-mentioned methylated compound, for example, triethylgallium (Ga (C ₂ H ₅ ) ₃ ) or triethylindium is used. (In (C ₂ H ₅ )
An ethylated compound of Group III element such as ₃ ) may be used.

Further, instead of the above-described metalorganic chemical vapor deposition method,
Molecular Beam Epitaxy (MBE)
It can also be implemented using the law.

It is clear that the numerical conditions relating to the deposition of the respective constituents such as these materials, the film thickness and the temperature, or other conditions can be arbitrarily modified and modified within the scope of the object of the invention according to this application. Is.

(Effects of the Invention) As is apparent from the above description, according to the method of manufacturing a compound semiconductor substrate according to this application, the thermal expansion coefficient α _Si of single crystal silicon and the thermal expansion coefficient α of single crystal gallium arsenide are
_Taking advantage of the fact that the thermal expansion coefficient α _InP of _GaAs and single crystal indium phosphorus is α _GaAs > α _InP > α _Si , by manufacturing a compound semiconductor substrate with a configuration containing indium phosphorus as a buffer layer, Indium phosphide, which has a coefficient of thermal expansion as an intermediate value between these two substances, acts to relax the stress generated between the gallium arsenide and the material, and reduces the warpage of the substrate that causes cracks. can do.

Therefore, even when the single crystal gallium arsenide is grown with a sufficient film thickness for the purpose of improving the lattice defect density (EPD), cracks can be avoided.

Therefore, a compound semiconductor substrate having a small EPD can be easily and easily manufactured, and in turn, various devices having excellent characteristics can be provided at low cost.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a schematic substrate cross section for explaining an embodiment of the method according to the first invention of this application, and FIG. 2 is an embodiment of the method according to the second invention of this application. For the purpose of explanation, an explanatory view is shown with a schematic substrate cross section, and FIG. 3 is an explanatory view with a schematic substrate cross section for explaining the conventional technique. 11 …… Substrate (single crystal silicon) 13,27 …… a-GaAs (first gallium arsenide buffer) layer 15,25,37 …… GaAs (single crystal gallium arsenide) layer 17 …… a-GaAs (first gallium gallium) Arsenic buffer) layer 19,29 …… a-InP (indium phosphide buffer) layer 21 …… a-GaAs (second gallium arsenide buffer) layer 23 …… buffer layer 31 …… first buffer layer 33 …… InP ( Single crystal indium phosphide) layer 35 ... a-GaAs (second gallium arsenide buffer (second buffer)) layer.

Claims (2)

(57) [Claims] 1. A compound semiconductor substrate is manufactured by depositing a buffer layer on the surface of a single crystal silicon (Si) substrate, and depositing and growing a single crystal gallium arsenide (GaAs) layer on the surface of the buffer layer at a high temperature. In doing so, the buffer layer is deposited by sequentially depositing a first gallium arsenide buffer layer, an indium phosphide (InP) buffer layer, and a second gallium arsenide buffer layer from the surface of the single crystal silicon substrate. A method of manufacturing a compound semiconductor substrate, comprising: 2. A compound semiconductor substrate is manufactured by depositing a buffer layer on a surface of a single crystal silicon (Si) substrate, and depositing and growing a single crystal gallium arsenide (GaAs) layer on the surface of the buffer layer at a high temperature. In doing so, depositing the buffer layer, and sequentially depositing a first gallium arsenide buffer layer and an indium phosphide (InP) buffer layer from the surface of the silicon substrate to form a first buffer layer. A step of depositing and growing a single crystal indium phosphide layer on the surface of the first buffer layer at a high temperature, and a second gallium arsenide buffer layer deposited on the surface of the single crystal indium phosphide layer to form a second buffer. A method of manufacturing a compound semiconductor substrate, comprising: performing a step of forming a layer.