JPH01120011A - Inp semiconductor thin film - Google Patents
Inp semiconductor thin filmInfo
- Publication number
- JPH01120011A JPH01120011A JP27568487A JP27568487A JPH01120011A JP H01120011 A JPH01120011 A JP H01120011A JP 27568487 A JP27568487 A JP 27568487A JP 27568487 A JP27568487 A JP 27568487A JP H01120011 A JPH01120011 A JP H01120011A
- Authority
- JP
- Japan
- Prior art keywords
- inp
- gaas
- single crystal
- semiconductor thin
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000010409 thin film Substances 0.000 title claims abstract description 27
- 239000013078 crystal Substances 0.000 claims abstract description 49
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000007547 defect Effects 0.000 abstract description 4
- 230000003746 surface roughness Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052710 silicon Inorganic materials 0.000 abstract 4
- 239000010703 silicon Substances 0.000 abstract 4
- 239000010410 layer Substances 0.000 description 47
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 11
- 239000007789 gas Substances 0.000 description 6
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 6
- 239000002994 raw material Substances 0.000 description 6
- OTRPZROOJRIMKW-UHFFFAOYSA-N triethylindigane Chemical compound CC[In](CC)CC OTRPZROOJRIMKW-UHFFFAOYSA-N 0.000 description 5
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- MGYGFNQQGAQEON-UHFFFAOYSA-N 4-tolyl isocyanate Chemical compound CC1=CC=C(N=C=O)C=C1 MGYGFNQQGAQEON-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- QLNWXBAGRTUKKI-UHFFFAOYSA-N metacetamol Chemical compound CC(=O)NC1=CC=CC(O)=C1 QLNWXBAGRTUKKI-UHFFFAOYSA-N 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はＩｎＰ半導体薄膜、更に詳細には、Ｓｉ基板上
にＩｎＰ単結晶層をＧａＡｓ層等を介して設けたＩｎＰ
半導体薄膜に関する。Detailed Description of the Invention (Industrial Application Field) The present invention relates to an InP semiconductor thin film, more specifically, an InP semiconductor thin film in which an InP single crystal layer is provided on a Si substrate with a GaAs layer interposed therebetween.
Regarding semiconductor thin films.
（従来の技術）
Ｓｉ基板上にＩｎＰ単結晶層を設けた半導体薄膜（本明
細書においてＩｎＰ半導体薄膜という）は、ＩｎＰ素子
の集積化を図る上で重要なものである。(Prior Art) A semiconductor thin film in which an InP single crystal layer is provided on a Si substrate (herein referred to as an InP semiconductor thin film) is important for integrating InP elements.
一第２図は、従来のＩｎＰ半導体薄膜の構造説明断面図
であって、図中、１は（１００）表面をもつＳｉ基板、
２はＩｎＰ単結晶層を示す。FIG. 2 is a cross-sectional view explaining the structure of a conventional InP semiconductor thin film, in which 1 indicates a Si substrate with a (100) surface;
2 indicates an InP single crystal layer.
このＩｎＰ半導体薄膜は、減圧ＭＯＣＶＤ法（Ｍｅｔａ
ｌ Ｏｒｇａｎｉｃ Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ
Ｄｅｐｏｓｉｔｉｏｎ ：有機金属化学蒸着法）を用い
、かつ、原料としてトリエチルインジウム（ＴＥＩ）及
びホスフィン（ＰＨｓ ）を用いて、Ｓｉ基板１の上に
ＩｎＰ単結晶層２を直接結晶成長させることにより得る
ことができる［応用物理学会予稿集 １９８６年（春）
、第７２３頁、嵐４ｐ−Ｗ−２］ 。This InP semiconductor thin film was produced using the low pressure MOCVD method (Meta
l Organic Chemical Vapor
The InP single crystal layer 2 can be obtained by directly growing the InP single crystal layer 2 on the Si substrate 1 using triethylindium (TEI) and phosphine (PHs) as raw materials. It is possible [Proceedings of the Japan Society of Applied Physics, Spring 1986]
, p. 723, Arashi 4p-W-2].
（発明が解決しようとする問題点）
しかしながら、従来のＩｎＰ半導体薄膜は、上記の如く
、格子定数が基板であるＳｉと比べて約８％大きいＩｎ
ＰをＳｉ基板上に直接結晶成長させて作成されていたた
め、この格子不整合に起因する結晶欠陥が得られたＩｎ
Ｐ層中に多く存在し、その結果、ＩｎＰ単結晶層の表面
が平坦、かつ、鏡面でない等、実用上満足のゆくものと
は云えなかった。(Problems to be Solved by the Invention) However, as mentioned above, the conventional InP semiconductor thin film has a lattice constant of about 8% larger than that of Si, which is the substrate.
Because P was created by direct crystal growth on a Si substrate, In
It exists in large amounts in the P layer, and as a result, the surface of the InP single crystal layer is not flat or mirror-finished, which is not practically satisfactory.
（問題点を解決するための手段）
本発明者は、かかる従来のＩｎＰ半導体薄膜における格
子不整合に起因する結晶欠陥及び表面荒れの問題点を解
決し、ＩｎＰ層の結晶性が更に良好なＩｎＰ半導体薄膜
を提供すべく種々検討の結果、本発明を完成した。(Means for Solving the Problems) The present inventor has solved the problems of crystal defects and surface roughness caused by lattice mismatch in such conventional InP semiconductor thin films, and has created an InP layer with even better crystallinity. As a result of various studies to provide a semiconductor thin film, the present invention was completed.
即ち本発明は、Ｓｉ基板上にＧａＡｓ層及びＩｎＰ層を
この順に重ねてなるＩｎＰ半導体薄膜である。That is, the present invention is an InP semiconductor thin film formed by stacking a GaAs layer and an InP layer in this order on a Si substrate.
（作用）
本発明のＩｎＰ半導体薄膜に使用されるＧａＡｓは、基
板に使用されるＳｉと表層となるＩｎＰの中間の格子定
数を有する。従って、ＧａＡｓは、Ｓｉ基板上に直接Ｉ
ｎＰ単結晶を成長させた場合の格子不整合を緩和する作
用を有する。(Function) GaAs used in the InP semiconductor thin film of the present invention has a lattice constant between that of Si used for the substrate and InP used as the surface layer. Therefore, GaAs can be directly deposited on the Si substrate.
It has the effect of alleviating lattice mismatch when growing an nP single crystal.
更に、かかる作用は、Ｓｉ基板とＧａＡｓ単結晶層、及
びＧａＡｓ単結晶層とＩｎＰ単結晶層間に形成されるバ
ッファ層によって増長される。Furthermore, this effect is enhanced by the buffer layer formed between the Si substrate and the GaAs single crystal layer, and between the GaAs single crystal layer and the InP single crystal layer.
（実施例） 以上、本発明を実施例を示す図面と共に説明する。(Example) The present invention will be described above with reference to drawings showing embodiments.
第１図は、本発明のＩｎＰ半導体薄膜の構造説明断面図
を示すものであって、図中、ｌは（１００）表面をもつ
Ｓｉ基板、２は第１ＧａＡｓバツフアＮ、３はＧａＡｓ
単結晶層、４は第２ＧａＡｓバッファ層、５はＩｎＰｎ
ラバ９フフ
明のＩｎＰ半導体薄膜は、その基本構成がＳｉ基板１の
上にＧａＡｓ単結晶層３及びＩｎＰ単結単結晶製６の順
に重ねたものであるが、第１図に示す如く、Ｓｉ基板１
の上に適宜バッファ層を用いて２〜６の各層をこの順に
重ねたものがより好ましいものとして上げられる。FIG. 1 shows a structural cross-sectional view of the InP semiconductor thin film of the present invention, in which l is a Si substrate with a (100) surface, 2 is a first GaAs buffer N, and 3 is a GaAs substrate.
Single crystal layer, 4 is second GaAs buffer layer, 5 is InPn
The basic structure of the InP semiconductor thin film shown in Lava 9 is that a GaAs single crystal layer 3 and an InP single crystal layer 6 are stacked on a Si substrate 1 in this order, but as shown in FIG. Board 1
More preferred is a structure in which 2 to 6 layers are laminated in this order using a buffer layer as appropriate.
第１図に示す構成のＩｎＰ半導体薄膜は、例えば次に示
す方法により製造することができる。The InP semiconductor thin film having the structure shown in FIG. 1 can be manufactured, for example, by the method shown below.
まず、（ｉｏｏ）を表面にもつＳｉ基板１上に第１ Ｇ
ａＡｓバッファ層、ＧａＡｓ単結晶層をこの順に重ねて
結晶成長させる。結晶成長は、例えば文献記載の方法に
従って行なうことができる［Ｊｏｕｒｎａｌ ｏｆ Ｃ
ｒｙｓｔａｌ Ｇｒｏｗｔｈ 、第７巻，第４９０〜４
９７頁（１ ９８６年）］。First, a first G
An aAs buffer layer and a GaAs single crystal layer are stacked in this order and crystal grown. Crystal growth can be carried out, for example, according to the method described in the literature [Journal of C
Rystal Growth, Volume 7, No. 490-4
97 pages (1986)].
Ｓｉ基板１をフッ酸による化学エツチングにより表面酸
化膜を除去した後、結晶成長装置に導入し、アルシンガ
ス（ＡｓＨｓ）と水素混合ガス中で９０℃以上の温度で
加熱処理する。次に、アルシンガス及びトリメチルガリ
ウム（ＴＭＧ）を原料として４５０℃以下の低温で第１
ＧａＡｓバッファ層２を膜厚２００Å以下に成膜する
。次いで、温度を７００〜７５０℃に上昇させた以外は
前記第１ＧａＡｓバツフア屡の場合と同様にして、Ｇａ
Ａｓ単結晶層３を膜厚的１μｍの厚さに結晶成長させる
。尚、Ｇａ源としては、前記ＴＭＧの代わりにトリエチ
ルガルラム（ＴＥＧ）を用いることができる。かくして
、Ｓｉ基板上の上に結晶性のよいＧａＡｓの単結晶層を
成長させることができる。After the surface oxide film of the Si substrate 1 is removed by chemical etching with hydrofluoric acid, the Si substrate 1 is introduced into a crystal growth apparatus and heat-treated at a temperature of 90° C. or higher in a mixed gas of arsine gas (AsHs) and hydrogen. Next, arsine gas and trimethyl gallium (TMG) are used as raw materials at a low temperature of 450°C or less.
A GaAs buffer layer 2 is formed to a thickness of 200 Å or less. Next, Ga
The As single crystal layer 3 is grown to a thickness of 1 μm. Note that triethyl gallum (TEG) can be used as the Ga source instead of TMG. In this way, a GaAs single crystal layer with good crystallinity can be grown on the Si substrate.
次いで、前記で得られたＧａＡｓ単結晶層３の上に第２
ＧａＡｓバッファ層４、ＩｎＰｎラバ９フフ
長させる．結晶成長は、常法に従って行なうことができ
、前記ＧａＡｓ単結晶層３の形成後、更に連続的に上層
４〜６を結晶成長させることができるが、また−度結晶
成長装置から結晶を取り出した後再度結晶成長を行なう
ことも可能である。次に後者の方法について説明する。Next, a second layer is formed on the GaAs single crystal layer 3 obtained above.
GaAs buffer layer 4 and InPn rubber 9 are made long. Crystal growth can be carried out according to a conventional method, and after the formation of the GaAs single crystal layer 3, the upper layers 4 to 6 can be continuously grown. It is also possible to perform crystal growth again afterwards. Next, the latter method will be explained.
まず、ＧａＡｓ単結晶層３をアルシンガスと水素混合ガ
ス中で６５０℃で約５分間加熱して、その表面の酸化物
を除去する。次に、温度を４５０’Ｃに下げ、アルシン
ガス及びＴＭＧ若しくはＴＥＧを原料として第２ＧａＡ
ｓバツフアＮ４を膜厚約２５０人となるように成膜する
。次いで、ホスフィン及びトリメチルインジウム（ＴＭ
Ｉ）若しくはトリエチルインジウム（ＴＥＩ）を原料と
して５００℃でＩｎＰｎラバ９フフ
ＩｎＰｎラバ９フフ
としてホスフィン及びＴＭＩ若しくはＴＥＩを使用する
点では同じであるが、次に示す如く組成比の異なる原料
を用いて、通常のＩｎＰの結晶成長に使用される温度、
即ち６００〜６５０℃でＩｎＰ単結晶層６を所定の厚さ
に成長させる。First, the GaAs single crystal layer 3 is heated at 650° C. for about 5 minutes in a mixed gas of arsine gas and hydrogen to remove oxides on its surface. Next, the temperature was lowered to 450'C, and a second GaA was prepared using arsine gas and TMG or TEG as raw materials.
A film of s-buffer N4 is formed to a thickness of about 250 layers. Then, phosphine and trimethylindium (TM
I) or InPn rubber 9 fluff using triethyl indium (TEI) as a raw material at 500 ° C. It is the same in that phosphine and TMI or TEI are used as InPn rubber 9 fluff, but using raw materials with different composition ratios as shown below. , the temperature used for normal InP crystal growth,
That is, the InP single crystal layer 6 is grown to a predetermined thickness at 600 to 650°C.
原料中のホスフィンとＴＭＩのモル比（ＰＨ３／ＴＭ
Ｉ ）は、ＩｎＰバッファ層５の成長においては、約５
００と非常に大きくとる必要があるのに対し、通常のＩ
ｎＰ結晶成長においては、約１００となるようにする。Molar ratio of phosphine and TMI in the raw material (PH3/TM
I) is approximately 5 in the growth of the InP buffer layer 5.
00, which must be very large, whereas the normal I
In nP crystal growth, it should be approximately 100.
（発明の効果）
本発明のＩｎＰ半導体薄膜は、叙上の如く、Ｓｉ基板上
にまず結晶性がよく格子定数がＩｎＰとＳｉの中間にあ
るＧａＡｓ層を成長させ、その上にＩｎＰ層を成長させ
てなるものであるため、本発明によればＳｉ基板上に直
接ＩｎＰ単結晶層を成長させた従来ＩｎＰ半導体薄膜に
比べ、格子不整合を緩和し、結晶欠陥の発生を低減する
ことができる。又、ＧａＡｓ単結晶層上にＧａＡｓバッ
ファ層、ＩｎＰｎツバ９フを重ねた上にＩｎＰ単結晶層
を結晶成長させて得られる本発明のＩｎＰ半導体薄膜は
、ＧａＡｓ結晶とＩｎＰ結晶の格子不整合による歪みが
極めて緩和されたもので、ＩｎＰ単結晶層の結晶性の極
めて良好なものである。(Effects of the Invention) As described above, the InP semiconductor thin film of the present invention is produced by first growing a GaAs layer with good crystallinity and a lattice constant between InP and Si on a Si substrate, and then growing an InP layer on top of the GaAs layer. Therefore, the present invention can alleviate lattice mismatch and reduce the occurrence of crystal defects compared to conventional InP semiconductor thin films in which an InP single crystal layer is grown directly on a Si substrate. . Furthermore, the InP semiconductor thin film of the present invention obtained by crystal-growing an InP single-crystal layer on a GaAs single-crystal layer, a GaAs buffer layer, and an InPn buffer layer is due to the lattice mismatch between the GaAs crystal and the InP crystal. The strain is extremely relaxed, and the crystallinity of the InP single crystal layer is extremely good.
第１図は本発明ＩｎＰ半導体薄膜の構造説明断面図、第
２図は従来のＩｎＰ半導体薄膜の構造説明断面図を示す
。
１ ・・・Ｓ ｉ基板、２・・・第１ＧａＡｓバツフｙ
Ｍ、３・・・ＧａＡｓ単結晶層、
４・・・第２ＧａＡｓバッファ層、
５・・・ＩｎＰｎツバ９フ、６・・・ＩｎＰ単結晶層。
特許出願人 沖電気工業株式会社FIG. 1 is a sectional view showing the structure of an InP semiconductor thin film according to the present invention, and FIG. 2 is a sectional view showing the structure of a conventional InP semiconductor thin film. 1... Si substrate, 2... First GaAs buffer y
M, 3...GaAs single crystal layer, 4...Second GaAs buffer layer, 5...InPn flange 9, 6...InP single crystal layer. Patent applicant Oki Electric Industry Co., Ltd.
Claims (1)
ねたことを特徴とするＩｎＰ半導体薄膜。 ２、前記ＧａＡｓ層が第１ＧａＡｓバッファ層、ＧａＡ
ｓ単結晶層、第２ＧａＡｓバッファ層をこの順に重ねた
ものである特許請求の範囲第１項記載のＩｎＰ半導体薄
膜。[Claims] 1. An InP semiconductor thin film, characterized in that a GaAs layer and an InP layer are stacked in this order on a Si substrate. 2. The GaAs layer is a first GaAs buffer layer, GaAs
2. The InP semiconductor thin film according to claim 1, wherein an s single crystal layer and a second GaAs buffer layer are stacked in this order.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62275684A JPH0775222B2 (en) | 1987-11-02 | 1987-11-02 | Method for manufacturing InP semiconductor thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62275684A JPH0775222B2 (en) | 1987-11-02 | 1987-11-02 | Method for manufacturing InP semiconductor thin film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01120011A true JPH01120011A (en) | 1989-05-12 |
| JPH0775222B2 JPH0775222B2 (en) | 1995-08-09 |
Family
ID=17558910
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62275684A Expired - Fee Related JPH0775222B2 (en) | 1987-11-02 | 1987-11-02 | Method for manufacturing InP semiconductor thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0775222B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01189909A (en) * | 1988-01-26 | 1989-07-31 | Nippon Telegr & Teleph Corp <Ntt> | Composite semiconductor substrate |
| JP2019517732A (en) * | 2016-04-07 | 2019-06-24 | アイクストロン、エスイー | Formation of layers on semiconductor substrates |
| CN111668090A (en) * | 2020-07-31 | 2020-09-15 | 广东省大湾区集成电路与系统应用研究院 | Semiconductor structure and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6453407A (en) * | 1987-05-13 | 1989-03-01 | Sharp Kk | Compound semiconductor substrate |
-
1987
- 1987-11-02 JP JP62275684A patent/JPH0775222B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6453407A (en) * | 1987-05-13 | 1989-03-01 | Sharp Kk | Compound semiconductor substrate |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01189909A (en) * | 1988-01-26 | 1989-07-31 | Nippon Telegr & Teleph Corp <Ntt> | Composite semiconductor substrate |
| JP2019517732A (en) * | 2016-04-07 | 2019-06-24 | アイクストロン、エスイー | Formation of layers on semiconductor substrates |
| CN111668090A (en) * | 2020-07-31 | 2020-09-15 | 广东省大湾区集成电路与系统应用研究院 | Semiconductor structure and manufacturing method thereof |
| CN111668090B (en) * | 2020-07-31 | 2023-03-14 | 广东省大湾区集成电路与系统应用研究院 | Semiconductor structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0775222B2 (en) | 1995-08-09 |
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